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Data Types 1682830998

The document discusses data types in SystemVerilog. It describes two-state data types like bit and byte, four-state types like reg and logic, and non-integer types like time and real. It also covers user-defined types like enum, typedef, struct and union. Examples are provided to demonstrate how these types can be used for digital design and verification. In conclusion, SystemVerilog provides a range of data types for different kinds of information to help with design representation and efficient verification code.

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Sandeep Reddy
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19 views17 pages

Data Types 1682830998

The document discusses data types in SystemVerilog. It describes two-state data types like bit and byte, four-state types like reg and logic, and non-integer types like time and real. It also covers user-defined types like enum, typedef, struct and union. Examples are provided to demonstrate how these types can be used for digital design and verification. In conclusion, SystemVerilog provides a range of data types for different kinds of information to help with design representation and efficient verification code.

Uploaded by

Sandeep Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SYSTEM VERILOG

DATA TYPES
System Verilog
Data Types
Introduction

Data types in User-defined


SystemVerilog Data Types

TWO-STATE

FOUR-STATE Conclusion

NON-INTEGER TYPES
Data Types
TWO-STATE

bit: A single bit of data that can store either 0 or 1

byte: An 8-bit data type that can store integer values between 0 and 255.

shortint: A 16-bit signed integer data type.

int: A 32-bit signed integer data type.

longint: A 64-bit signed integer data type


Data Types
FOUR-STATE

reg: A reg is a data type that can model a storage element or a state.
They need to be driven by an always block and cannot be driven by a
continuous assignment statement. Reg can be used to model both
sequential and combinational logic

Logic: A Logic is a new data type in SystemVerilog that can be used to


model both wires and state information (reg). It also is a 4-state
variable and hence can hold 0, 1, x, and z values. If a wire is declared as
a logic (wire logic), then it can be used to model multiple drivers and the
last assignment will take the value

integer: A integer is a data type used to represent signed or unsigned


integers with a bit width of 32 bits. It is used for arithmetic and logical
operations.
Data Types
NON-INTEGER TYPES

time: represents a time value, measured in simulation time units.

shortreal: represents a floating-point value with a precision of 6 decimal


places.

real: represents a floating-point value with a precision of at least 6


decimal places.

realtime: represents the current simulation time in simulation time units.


User-defined
Data Types

enum: This is used to define a list of named values that can be used as
constants in the code.

typedef: This is used to define a new data type based on an existing data
type. The new data type can be used anywhere the original data type
could be used.

struct: This is used to define a collection of related variables, known as


members, as a single data type. The members can be of any data type,
including other user-defined data types.

union: This is similar to a struct, but only one member can be active at a
time.
enum example

typedef example
struct example union example
Conclusion
Explored data types in SystemVerilog for 2-state and 4-state data

SystemVerilog provides a range of data types for different kinds


of information

Examples demonstrated usage in digital design and verification

Understanding data types in SystemVerilog leads to better design


representation and efficient verification code
the
What is the difference between a reg, wire and logic in SystemVerilog?

What is the difference between logic[7:0] and byte variable in SystemVerilog?

What is the Two state and Four state Data Types?

What are Signed and Unsigned numbers and their range?

What is the difference between a STRUCTURE and UNION?

What are the basic data types in SystemVerilog?

What is an integer, real and time data type in SystemVerilog?

What is a packed and unpacked data type in SystemVerilog?


Jairaj Mirashi

Thank you

FOR YOUR SUPPORT

[email protected]

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