A Novel 8T SRAM Cell With Improved Read-SNM

Abhijit Sil, Soumik Ghosh, Magdy Bayoumi

The Center for Advanced Computer Studies
University of Louisiana at Lafayette
Lafayette, Louisiana 70504
Email: {axs2021,sxg5317,mab}@cacs.louisiana.edu

Abstract—As the MOSFET’s channel length is scaling down, Write Word-line

SRAM stability becomes the major concern for future technology.
The cell becomes more susceptible to both process induced
variation in device geometry and threshold voltage variability
due to dopant fluctuation in the channel region. In this paper ,
a novel highly stable 8T SRAM cell is proposed which eliminate M2 M4
any noise induction during read operation and keep the Read
SNM as high as 468mV at VDD = 1.2 V in 120nm technology . Qbar ='0' Q='1'
The cell also supports low power operation at Cell VDD as low
as 0.34V.This new asymmetric cell structure is capable of using M6 M5
differential sense technique for high speed read operation. Bitbar
M1 M3 Bit
I. I NTRODUCTION
SRAM memory has become the key area of technology
scaling as memory block becomes the main die area consumer
in high performance system [10]. Traditionally SRAM cell was
Fig. 1. Schematic diagram of the conventional 6T SRAM cell shows the
scaled according to the layout design rules. But as the feature current flow during read
size is going below 100nm range, the variability issue becomes
prominent. To increase cell density, minimum size transistors
are used in making SRAM cell. This makes the SRAM cell, the requires single ended sensing circuit for read operation which
most susceptible to both process induced variation in device is 56 % slower than differential sensing in 90nm technology
geometry and threshold voltage variability due to dopant [3] .
fluctuation in the channel region. These atomic level intrinsic To overcome the cell instability as well as speed up the read
fluctuations cannot be eliminated by external control of the operation, a novel highly stable 8T SRAM cell is proposed. It
manufacturing process [1]. The effect of variability becomes eliminates any noise induction during read operation and keeps
more prominent since SRAM requires well matched MOSFET the Read SNM as high as 468mV at VDD = 1.2V in 120nm
for cross-coupled inverters [1]. Moreover, since advanced technology. Moreover, it can be embedded with differential
fabrication technologies are heading towards a steady increase sensing technique to speed up the Read operation. The cell
in the speed of microprocessors, the speed of SRAM, used as a also supports ultra-low power operation at Cell VDD as low
cache memory, needs to be increased to synchronize with the as 0.34V.The cell requires only one bit-line which reduces the
processor operation. Increasing the speed, however, requires active power consumption by a large margin compared to 6T
the threshold voltage of the MOSFET to be decreased. But and 8T [6] cells where two and three bit-lines are introduced,
due to the intrinsic fluctuation, a limit is drawn to which the respectively.
threshold voltage can be lowered. Moreover, this threshold The rest of the paper is organized as follows. Section II
fluctuation contributes in large reduction of static noise margin introduces the proposed cell structure and describes its read
(SNM). Noise margin becomes worse at the time of read and write operation. In section III, cell layout is discussed.
operation compared to hold operation, so it is required to Section IV reports the dependence of Read SNM on different
design a smart SRAM cell where read operation does not factors. In section V, the ultra-low power operation of the
disturb the cell stability; which means no reduction in SNM proposed cell is discussed. Sections VI and VII describe the
during read. simulation results and compare them with five other SRAM
To achieve higher cell stability, the 8T SRAM with im- cells. Finally, section VIII offers a brief conclusion.
proved SNM was proposed [6]. In this cell structure, the read
operation can be performed without disturbing the cell stability II. NOVEL 8T SRAM
which makes it possible to lower the Vth of the MOSFET In 6T SRAM, The fundamental stability problem occurs
in SRAM cell by the same proportion as in CMOS logic during the read operation. In order to reduce leakage power
transistor. However, this 8T SRAM cell [6] uses three bit consumption by reducing worst case VDS of M5 and M6 pass
lines, which increases power consumption and cell area. It also transistor, pre-charge voltage for bit-lines is kept much lower

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 Write_Word_Line
than the cell supply voltage When the pass transfer transistors
(M5 & M6,Fig 1) are turned on, which pull the ‘0’ logic node
to a poor ’0’ level and ‘1’logic node to a poor ‘1’ logic level, it
may lead to flip the cell data. In our novel 8T SRAM cell, three
extra transistors are used to separate the read and write current M2 M4
path and avoid accidental cell flipping during read operation.
This novel cell provides significant large SNM during Read Q
Qbar
operation.
Write Operation: In the proposed cell, single bitline is used M5
for write operation which reduces write power consumption M1 M3 Bit_Line
compared to 6T SRAM write operation. During write ‘1’ op-
eration, M5 (Fig. 2) turns-on by enabling the ‘write word line
Read_Word_Line
signal’. As the ‘Bit Line’ is charged to logic ‘1’, the ‘Q’ node
starts charging and turns on M1 which leads to flip ‘Qbar’ node
to logic ‘0’ . Now ‘Qbar’ node helps enabling the M4 which
facilitates writing good logic ‘1’ at ‘Q’ node. On the other M6
M7
hand, during write ‘0’ operation, the ‘Bit Line’ is charged M8
to logic ‘0’ and M5 turns-on by enabling ‘write word line’
signal. The ‘Q’ node starts dis-charging and turns on M2 which
in turn flipped ‘Qbar’ node to logic ‘1’. Now ‘Qbar’ node helps
Fig. 2. Schematic diagram of proposed 8T SRAM cell
turing M3 on , which facilitates discharging ‘Q’ node properly
and consequently logic ‘0’ is obtained at ‘Q’ node.
Read Operation: Read operation is performed by using
MOSFETs M6, M7 and M8. Node ‘Qbar’ is connected to
the gates of M7 and M8. In this case, a current flows in
and out of the read circuit by turning on transistor M6
using Read Word Line. The cell data is read by sensing the
Bit-Line voltage fluctuation using differential current mode
sense amplifier. The amplifier detects the voltage difference
of its inputs: Bit Line and local reference line which are
both precharged to 450mV before the read operation starts
.During read ‘1’ operation, M5 and M6 are turned off and
on respectively. As ‘Qbar’ node stores ‘0’ logic, it enables
the M8 (PMOS) transistor which in turn charges the Bit Line Fig. 3. Read butterfly curves for 6T and proposed 8T cells
through M8 and M6. The sense amplifier detects the bit
swing and output ‘1’ is obtained. During read ‘0’ operation,
Read Word Line signal enables the M6 and as ‘Qbar’ node data [2], [7]. Simulations are performed during Read ’1’ and
stores logic ‘1’, so it turns on M7 (NMOS) which discharges Standby operation .During Standby, the SNM of 468mV is
the Bit-Line through M7 and M6. This effect builds a voltage recorded for both conventional 6T SRAM and proposed 8T
difference between the Bit Line and the local reference line SRAM, but during Read ’1’ operation , the proposed cell has
which is sensed by the differential amplifier, and logic ‘0’ is the SNM of 468mV which is four times higher than that of
obtained at the output. 6T SRAM(115mV). The Figure 3shows the sharp contranst in
read butterfly curve of conventional 6T and proposed 8T cell
III. C ELL L AYOUT .
The proposed 8T SRAM cell uses one bit-line but has The Independent current path for read operation which
to provide one extra word-line (Read Word Line) for read doesn’t include ‘Q’ and ‘Qbar’ node, leads to an increase
operation, so the cost of the wire connection is almost the same in the Read SNM. Figure 4 shows the effect of temperature
as that of the conventional 6T SRAM cell. A total of three variation over Read SNM at different Cell VDD and by varying
metal layers are employed to design the cell. The proposed temperature from −40◦C to 120◦ C, Read SNM varies only
cell size is 4.41µm × 3.53µm which consumes an area of by 30mV at cell VDD = 1.2V .
15.57µm2 in 120nm technology and it results in 34% area
overhead compared to the conventional 6T SRAM cell. V. U LTRA -L OW POWER OPERATION
The proposed cell is capable of operating at cell supply
IV. S TATIC N OISE M ARGIN (SNM) voltage as low as 340 mV . Cell consumes extremely low
The SNM is the maximum amount of noise voltage that power of (0.29µW ) with a satisfactory Read SNM of 133
can be introduced at ‘Q’ and ‘Qbar’ without flipping the cell mV which enables the cell to be used in ultra - low power

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 500 500
6T SRAM
450 New 8T SRAM
400
400
SNM(VDD=1.2V)
350 SNM(VDD=.6V)

SNM(mV)
300

SNM(mv)
300 SNM(VDD=.34V)

250 200

200
100
150

100 0
0 100 200 0.4 0.6 0.8 1 1.2
T(C) Cell VDD(V)

Fig. 4. Read SNM of the proposed cell versus temperature at different cell Fig. 7. .Read SNM Variation over different Cell VDD for 6T and proposed
supply voltages 8T SRAM

TABLE I
1.4 P ERFORMANCE COMPARISON BETWEEN 6T AND PROPOSED 8T CELL AT
VDD = 1.2V CELL VDD = 1.2V
1.2

1
Parameter Name 6T Proposed 8T
0.8 Cell Leakage current (nA) 88 17
Q(V)

VDD=.6V
Write Current (µA) 9 5.4
0.6
Read Current (µA) 17.2 6.1
0.4 VDD =.34V Ig ON(nA) 10 17.7
Ig off(nA) 86.5 293
0.2 Cell Power (µW ) 9.7 10.1
0
Read time(psec) 544 531
0 0.2 0.4 0.6 0.8 1 1.2 1.4 Write time(psec) 409 593
Qbar(V) SNM Hold (mV) 468 468
SNM Read (mV) 115 468
Fig. 5. Read butterfly curves of the proposed cell at different cell supply
voltages

cell becomes 0.45µW which is less than that of 6T cell

application like remote data sensing where the power is the ( 0.62µW , fig 6) and it also provides a Read SNM of
most critical constraint.The figure 5 shows the butterfly curves 253mV(fig 7) which is almost twice of 6T cell’s Read SNM
of the proposed cell at different cell supply voltages. at Cell VDD = 1.2V .The write time of the proposed cell
is higher than conventional cell due to its single bit-line
VI. PARAMETER COMPARISON WITH CONVENTIONAL 6T
structure.Here write time is considered as the time gap between
SRAM CELL
worline active and data stored in ‘Q’ or ‘Qbar’ node ,which
Table I shows , the Read SNM of proposed cell is 468mv ever occurs later .
which is four times higher than the conventional cell (115
mV), but it pays overhead in cell power consumption which VII. PARAMETER COMPARISON AMONG
is 10.1µW compare to 9.7µW for 6T SRAM .But from the DIFFERENT SRAM CELL
simulation, it is observed that when the cell supply voltage is We have compared our proposed 8T SRAM cell with
reduced to 600mV, the cell power consumption of proposed five different SRAM cell and simulation results reveal our
proposed cell shows promising results in most of the parameter
reading. Fig 8 shows that the proposed cell has the highest read
10
6T SRAM
SNM among other cells (5T [8],6T,7T [9],8T-LL [4],8T-zero
New 8T SRAM [5]).The cell leakage current (Fig 9) of the proposed cell is
Cell Power Consumption(uW)

0
0.4 0.6 0.8 1 1.2
Cell VDD(V)

Fig. 6. Cell Power Consumption variation over different Cell Supply VDD
for 6T and proposed 8T SRAM Fig. 8. Hold and Read SNM for different SRAM Cells

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 [2] B. Calhoun and Chandrakasan, “A.Static noise margin variation for sub-
threshold SRAM in 65-nm CMOS”, Solid-State Circuits, IEEE Journal
of, 2006, 41, 1673-1679
[3] Y. Ye, M. Khellah, D. Somasekhar and V. De, “Evaluation of differential
vs. single-ended sensing and asymmetric cells in 90 nm logic technology
for on-chip caches”, Circuits and Systems, 2006. ISCAS 2006. Proceed-
ings. 2006 IEEE International Symposium on, 2006, 4pp.
[4] S. Jain and P. Agarwal, “A low leakage and SNM free SRAM cell design
in deep sub micron CMOS technology VLSI Design”, 2006. Held jointly
with 5th International Conference on Embedded Systems and Design.,
Fig. 9. Cell leakage current for different SRAM cells 19th International Conference on, 2006, 4pp.
[5] Y. Chang, F. Lai and C. Yang, “Zero-aware asymmetric SRAM cell for
reducing cache power in writing zero”, Very Large Scale Integration
(VLSI) Systems, IEEE Transactions on, 2004 , 12, 827-836
[6] L. Chang, D. Fried and J. Hergenrother, “Stable SRAM cell design for the
32 nm node and beyond”, VLSI Technology, 2005. Digest of Technical
Papers. 2005 Symposium on, 2005, 128-129
[7] E. Seevink and F. List, “Static Noise Margin Analysis of MOS SRAM
Cells”, Solid-State Circuits, IEEE Journal of, 1987, 5, 748-754
[8] Carlson, I. , Andersson, S. , Natarajan, S. and Alvandpour, A. “A
high density, low leakage, 5T SRAM for embedded caches” Solid-
State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th
European, 2004, 215-218
Fig. 10. Read Time and Write Time for different SRAM cells [9] Takeda, K., Hagihara, Y., Aimoto, Y., Nomura, M., Nakazawa, Y., Ishii,
T. and Kobatake, H. “A read-static-noise-margin-free SRAM cell for low-
VDD and high-speed applications”,Solid-State Circuits, IEEE Journal of,
2006, 41, 113-121
less than the other cells due to its single bit-line structure [10] Aly, R. E.,Bayoumi, M. A. “Low-Power Cache Design Using 7T SRAM
which reduces the bit-line sub-threshold leakage.The write Cell ” Circuit and Systems II , IEEE Transaction on, April 2007, 318-322
time(Fig 10) of the proposed cell is higher than other cells
due to its single bit-line structure.

VIII. C ONCLUSION
In this paper, a novel highly stable 8T SRAM was pre-
sented in 120nm technology. Even with cell ratio of 1.7,
the proposed SRAM cell operates with Read SNM of 468
mV at VDD =1.2V which is highest among all SRAM cell.
The cell occupies an area of 15.54µm2 which is 34% more
than the conventional 6T SRAM cell.The cell can perform
normal operation in the sub threshold regime where cell
supply VDD is reduced to as low as 340mV. The paper has
explored the impact of temperature variation on Read SNM
and suggests a satisfactory Read SNM deviation of 30mV and
14mV at VDD = 1.2V and VDD = .34V respectively, when
temperature varies from −40◦C to 120◦ C. The proposed cell
pays an overhead in cell power consumption which is 10.1µW
compare to 9.7µW for conventional 6T cell .But, when cell
supply voltage is reduced to 0.6V , the cell power consumption
of the proposed cell becomes .45µW which is less than that of
6T cell ( .62µW ) and it also provides a read SNM of 253mV
which is almost twice that of 6T cell’s read SNM at 1.2 V .

ACKNOWLEDGMENT
The authors acknowledge the support of the Governor’s
Information Technology Initiative, the U.S Department of
Energy award DE-FG02-04ER46136, the Louisiana Board
of Regents contract DOE/LEQSF (2004-07)-ULL, and the
NSF,INF 6-001-006, INF 9-001-001, OISE-0512403.

R EFERENCES
[1] A. Bhavnagarwala, X. Tang, and J. Meindl, “The impact of intrinsic
device fluctuations on CMOS SRAM cell stability”, Solid-State Circuits,
IEEE Journal of, 2001, 36, 658-665

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