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    22R01A0446

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    nramakrishnareddy23
    This document is a micro project report submitted by N. Jah to CMR Institute of Technology on arithmetic circuits. It was completed to fulfill the requirements of the Digital Logic Design Lab course. The report covers the design and implementation of basic arithmetic circuits like half adder, full adder, half subtractor, full subtractor, and 2-bit and 4-bit comparators using Verilog HDL. It includes an introduction, descriptions of each circuit, references, and certificates confirming the project was completed under the guidance of Mrs. A. Padma Priya.

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    22R01A0446

    Uploaded by

    nramakrishnareddy23
    8 views5 pages
    This document is a micro project report submitted by N. Jah to CMR Institute of Technology on arithmetic circuits. It was completed to fulfill the requirements of the Digital Logic Design Lab course. The report covers the design and implementation of basic arithmetic circuits like half adder, full adder, half subtractor, full subtractor, and 2-bit and 4-bit comparators using Verilog HDL. It includes an introduction, descriptions of each circuit, references, and certificates confirming the project was completed under the guidance of Mrs. A. Padma Priya.

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    This document is a micro project report submitted by N. Jah to CMR Institute of Technology on arithmetic circuits. It was completed to fulfill the requirements of the Digital Logic Design Lab course. The report covers the design and implementation of basic arithmetic circuits like half adder, full adder, half subtractor, full subtractor, and 2-bit and 4-bit comparators using Verilog HDL. It includes an introduction, descriptions of each circuit, references, and certificates confirming the project was completed under the guidance of Mrs. A. Padma Priya.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    8 views5 pages

    22R01A0446

    Uploaded by

    nramakrishnareddy23
    This document is a micro project report submitted by N. Jah to CMR Institute of Technology on arithmetic circuits. It was completed to fulfill the requirements of the Digital Logic Design Lab course. The report covers the design and implementation of basic arithmetic circuits like half adder, full adder, half subtractor, full subtractor, and 2-bit and 4-bit comparators using Verilog HDL. It includes an introduction, descriptions of each circuit, references, and certificates confirming the project was completed under the guidance of Mrs. A. Padma Priya.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 5

    A micro project report on

    ARITHMETIC CIRCUITS
    Submitted to CMR Institute of Technology in partial fulfillment of the requirement for the
    award of laboratory Digital Logic Design Lab Through Verilog HDL of II B. Tech I semester

    CMR INSTITUTE OF TECHNOLOGY


    (UGC AUTONOMOUS)
    (Approved by AICTE, Affiliated to JNTUH, Kukatpally, Hyderabad)
    Kandlakoya, Medchal Road, Hyderabad (2022-2023)

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

    Submitted by

    N.JAH 22R01A0436

    Under the Guidance of

    Mrs. A. Padma Priya


    CMR INSTITUTE OF TECHNOLOGY
    (UGC AUTONOMOUS)
    (Approved by AICTE, Affiliated to JNTUH, Kukatpally, Hyderabad)
    Kandlakoya, Medchal Road, Hyderabad (2022-2023)

    2022-2023
    DEPARTMENT OF ELECTRONICS AND COMMUNICATION
    ENGINEERING

    CERTIFICATE
    This to certify that a Micro Project entitled with “ARITHMETIC CIRCUITS” is being

    Submitted by

    L.JAYA KUSUMA 22R01A0436

    In partial fulfilment of the requirement for award of the “Digital Logic Design Lab through
    Verilog HDL” of II B. Tech I semester in ECE to the CMRIT, Hyderabad is a record of a
    bonafide work carried out under our guidance and supervision.

    Signature of Faculty Signature of HOD


    Mrs.A.Padma Priya Dr. K. Niranjan Reddy
    (Assistant professor) (Head Of
    Department)

    ACKNOWLEDGEMENT

    We are extremely grateful to Dr. M. Janga Reddy, Director, Dr. B. Satya Narayana, principal
    and Dr.K.Nirangan Reddy, Head of Department, Dept of computer Science and Engineering,
    CMR Institute of their inspiration and valuable guidance during entire duration.

    We are extremely thankful to our DDVH Lab faculty in-charge Mrs.A.Padma Priya, dept of
    Electronics and Communication Engineering, CMR Institute of Technology for her constant
    guidance, encouragement and moral support throughout the project.

    We express our thanks to all staff members and friends for all the help and coordination
    extended in bringing out this project successfully in time.

    Finally, we are very much thankful to our parents and relatives who guided directly or
    indirectly for successful completion of the project.

    L.JAYA KUSUMA 22R01A0436


    TABLE OF CONTENTS:

    S.NO Particulars Page No

    1 Introduction 5

    2 Half adder 5

    3 Full adder 6

    4 Half subtractor 7

    5 Full subtractor 8

    6 2 bit comparator 10

    7 4 bit comparator 11

    8 References 12

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