Asynchronous Communication Interface:

The block diagram of an asynchronous communication interface is displayed in the figure. It

works as both a sender and a receiver. The interface is boot up for a specific mode of transfer
using a control byte that is loaded into its control register. The transmitter register receives a
data byte from the CPU by the data bus. This byte is sent to a shift register for serial
transmission.
The receiver portion receives serial information into another shift register, and when a finalize
data byte is acquired, it is moved to the receiver register. The CPU can choose the receiver
register to read the byte through the data bus. The bits in the status register are utilized for input
and output flags and for recording specific errors that can appear during the transmission.
The CPU can read the status register to determine the status of the flag bits and to decide if any
errors have appeared. The chip chooses and the read and write control lines connect with the
CPU. The chip select (CS) input can select the interface by the address bus.
The register select (RS) is related to the read (RD) and write (WR) controls. Two registers are
write-only and two are read-only. The register selected is a service of the RS value and the RD
and WR status, as recorded in the table following the diagram.

The operation of the asynchronous communication interface is boot up by the CPU by sharing a
byte to the control register. The initialization process locates the interface in a particular mode
of operation as it represents specific parameters including the baud rate to use, how many bits
are in each character, whether to create and check parity and how many stop bits are joined to
each character.
Two bits in the status register are used as flags. One bit can signify whether the sender register is
null and another bit can signify whether the receiver register is full.
The operation of the transmitter portion of the interface is as follows. The CPU reads the status
register and determines the flag to view if the sender register is null. If it is null, the CPU sends
a character to the sender register and the interface clears the flag to denote the register full.
The first bit in the transmitter shift register is set to 0 to create a start bit. The character is shared
in parallel from the transmitter register to the shift register and the suitable number of stop bits
are joined into the shift register. The sender register is then signified null. The character can now
be sent one bit at a time by transferring the information in the shift register at the definite baud
rate.

CS RS Operation Register Selected

0 X X None : Data bus in high impedance

1 0 WR Transmitter Register

1 1 WR Control Register

1 0 RD Receiver Register

1 1 RD Status Register

Methods in Asynchronous Communication Data transfer

The internal operations in an individual unit of a digital system are synchronized using
clock pulse. It means clock pulse is given to all registers within a unit. And all data
transfer among internal registers occurs simultaneously during the occurrence of the
clock pulse. Now, suppose any two units of a digital system are designed independently,
such as CPU and I/O interface.

If the registers in the I/O interface share a common clock with CPU registers, then
transfer between the two units is said to be synchronous. But in most cases, the internal
timing in each unit is independent of each other, so each uses its private clock for its
internal registers. In this case, the two units are said to be asynchronous to each other,
and if data transfer occurs between them, this data transfer is called Asynchronous
Data Transfer.

The asynchronous data transfer between two independent units requires that control
signals be transmitted between the communicating units to indicate when they send the
data. Thus, the two methods can achieve the asynchronous way of data transfer.
1. Strobe Control Method

The Strobe Control method of asynchronous data transfer employs a single control line
to time each transfer. This control line is also known as a strobe, and it may be achieved
either by source or destination, depending on which initiate the transfer.

a. Source initiated strobe: In the below block diagram, you can see that strobe is
initiated by source, and as shown in the timing diagram, the source unit first places the
data on the data bus.

After a brief delay to ensure that the data resolve to a stable value, the source activates
a strobe pulse. The information on the data bus and strobe control signal remains in the
active state for a sufficient time to allow the destination unit to receive the data.
The destination unit uses a falling edge of strobe control to transfer the contents of a
data bus to one of its internal registers. The source removes the data from the data bus
after it disables its strobe pulse. Thus, new valid data will be available only after the
strobe is enabled again.
In this case, the strobe may be a memory-write control signal from the CPU to a
memory unit. The CPU places the word on the data bus and informs the memory unit,
which is the destination.
b. Destination initiated strobe: In the below block diagram, you see that the
strobe initiated by destination, and in the timing diagram, the destination unit
first activates the strobe pulse, informing the source to provide the data.
 The source unit responds by placing the requested binary information on the
data bus. The data must be valid and remain on the bus long enough for the
destination unit to accept it.
The falling edge of the strobe pulse can use again to trigger a destination
register. The destination unit then disables the strobe. Finally, and source
removes the data from the data bus after a determined time interval.
In this case, the strobe may be a memory read control from the CPU to a memory
unit. The CPU initiates the read operation to inform the memory, which is a
source unit, to place the selected word into the data bus.

2. Handshaking Method

The strobe method has the disadvantage that the source unit that initiates the
transfer has no way of knowing whether the destination has received the data that was
placed in the bus. Similarly, a destination unit that initiates the transfer has no way of
knowing whether the source unit has placed data on the bus.

So this problem is solved by the handshaking method. The handshaking method

introduces a second control signal line that replays the unit that initiates the transfer.

In this method, one control line is in the same direction as the data flow in the bus from
the source to the destination. The source unit uses it to inform the destination unit
whether there are valid data in the bus.

The other control line is in the other direction from the destination to the source. This is
because the destination unit uses it to inform the source whether it can accept data.
And in it also, the sequence of control depends on the unit that initiates the transfer. So
it means the sequence of control depends on whether the transfer is initiated by source
and destination.
o Source initiated handshaking: In the below block diagram, you can see that two
handshaking lines are "data valid", which is generated by the source unit, and
"data accepted", generated by the destination unit.

The timing diagram shows the timing relationship of the exchange of signals
between the two units. The source initiates a transfer by placing data on the bus
and enabling its data valid signal. The destination unit then activates the data
accepted signal after it accepts the data from the bus.
The source unit then disables its valid data signal, which invalidates the data on
the bus.
After this, the destination unit disables its data accepted signal, and the system
goes into its initial state. The source unit does not send the next data item until
after the destination unit shows readiness to accept new data by disabling the
data accepted signal.
This sequence of events described in its sequence diagram, which shows the
above sequence in which the system is present at any given time.
o Destination initiated handshaking: In the below block diagram, you see that
the two handshaking lines are "data valid", generated by the source unit, and
"ready for data" generated by the destination unit.
 Note that the name of signal data accepted generated by the destination unit has
been changed to ready for data to reflect its new meaning.
o

o
The destination transfer is initiated, so the source unit does not place data on the
data bus until it receives a ready data signal from the destination unit. After that,
the handshaking process is the same as that of the source initiated.
The sequence of events is shown in its sequence diagram, and the timing
relationship between signals is shown in its timing diagram. Therefore, the
sequence of events in both cases would be identical.
 Modes of Transfer:
The mode of transferring information between internal storage and
external I/O devices is known as I/O interface or input/output interface. Data
transfer between the central computer to I/O devices may be handled in
variety of modes.

–Programmed I/O

–Interrupt Initiated I/O

–Direct Memory Access (DMA)

Programmed I/O:
 CPU requests I/O operation
 I/O module performs operations.
 I/O module sets status bits
 CPU checks status bits periodically
 I/O module does not inform CPU directly
 I/O module does not interrupt CPU
 CPU may wait or come back later
 Under programmed I/O data transfer is very like memory access (CPU
viewpoint)
 Each device is given an unique identifier
 CPU commands contain identifier (address)

Dis-advantage of Programmed I/O:

 The problem with programmed I/O is that the processor has to wait a long time
for the I/O module of concern to be ready for either reception or transmission
of data.
 The processor, while waiting, must repeatedly interrogate the status of the I/O
module.
 Performance of the entire system is severely degraded.

Interrupt Initiated I/O:

 An interrupt facility an interrupt command is used to inform the device
about the start and end of transfer.
 In the programmed I/O method the CPU stays in the program loop until the
I/O unit indicates that it is ready for data transfer. This is time consuming
process because it keeps the processor busy needlessly.
 This problem can be overcome by using interrupt initiated I/O. In this when
the interface determines that the peripheral is ready for data transfer, it
generates an interrupt. After receiving the interrupt signal, the CPU stops
the task which it is processing and service the I/O transfer and then returns
back to its previous processing task.
 The main advantage is reduced latency. The processor has to temporarily
halt it's work in programmed I/O, whereas in interrupt I/O, the processor
continues to perform and only halts when interrupt is received.
DMA(Direct Memory Access):
 It is a feature of computer systems that allows certain hardware
subsystems to access main system memory (random-access memory)
independent of the central processing unit (CPU).
 During the DMA transfer, the CPU is idle and has no control of the memory
buses. A DMA Controller takes over the buses to manage the transfer
directly between the I/O device and memory.
Read And Write Control Lines:
 The read and write control lines running through the data buses have
control signals. The microprocessor can read data from memory or write
 data to the memory so the data buses are bidirectional. One direction is
needed to write the data while another direction is required for the read
command to fetch the data.

Working of DMA Controller

The DMA controller registers have three registers as follows.

 Address register – It contains the address to specify the desired location in
memory.
 Word count register – It contains the number of words to be transferred.
 Control register – It specifies the transfer mode.
Note: All registers in the DMA appear to the CPU as I/O interface registers. Therefore,
the CPU can both read and write into the DMA registers under program control via the
data bus.
The figure below shows the block diagram of the DMA controller. The unit
communicates with the CPU through the data bus and control lines. Through the use of
the address bus and allowing the DMA and RS register to select inputs, the register
within the DMA is chosen by the CPU. RD and WR are two-way inputs. When BG (bus
grant) input is 0, the CPU can communicate with DMA registers. When BG (bus grant)
input is 1, the CPU has relinquished the buses and DMA can communicate directly with
the memory.

DMA Transfer: