Switch – Level Modeling

Introduction
• Switch-level description is the lowest HDL logic level that can be used
to simulate digital systems
• Only small-scale systems can be simulated using pure switch-level
description.
• Switch-level description is used along with other types of modeling to
describe digital systems.
• Verilog has built-in code for NMOS and PMOS switches.
 MOS switches
pmos nmos cmos

cmos cl(out, data, ncontrol, pcontrol);

pmos pl(out, data, control) nmos nl (out, data, control)

drain,source,gate
Logic Tables for NMOS and PMOS
Tables

The nmos switch conducts when its control signal is I. If control signal is 0, the output
assumes a high impedance value.
Similarly, a pmos switch conducts if the control signal is 0
Power and Ground
The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed
when transistor-level circuits are designed.
Power and ground sources are defined with keywords supply1 and
supply0.
supply1 is equivalent to Vdd in circuits and place a logical 1 on a net.
supply0 is equivalent to ground or Vss and place a logical 0 on a net.

supply1 vdd;
supply0 gnd;
CMOS Inverter
symbol
Switch-Level description of NOT Gate
module invert (y, a);
input a;
output y;
supply1 vdd; //supply1 is a predefined word for the high voltage

supply0 gnd; //supply0 is a predefined word for the ground

pmos p1(y, vdd, a) ; //the name “p1” is optional; it can be omitted

nmos n1(y, gnd, a); //the name “n1” is optional; it can be omitted

endmodule
CMOS NOR Gate
Gate level and Switch level
Switch-Level description for NOR Gate
module nor2 (out, a, b) ;
output out;
input a, b;
wire c;
supply1 vdd;
supply0 gnd ;
//instantiate pmos switches
pmos (c, vdd, a);
pmos (out, c, b);
//instantiate nmos switches
nmos (out, gnd, a);
nmos (out, gnd, b);
endmodule
Stimulus
module stimulus;
reg A, B;
wire OUT;
nor2 nl(OUT, A, B);
initial
begin
A = 1'b0; B = 1'b0;
#5 A = 1'b0; B = 1'b1;
#5 A = 1'b1; B = 1'b0;
#5 A = 1'b1; B = 1'b1;
end
initial
$monitor($time, " OUT = %b, A = %b, B = %b", OUT, A, B);
endmodule
Switch-Level description of NAND Gate
module NAND2gate (a, b, y);
input a, b;
output y;
wire s1;
supply1 vdd;
supply0 gnd;
nmos (s1, gnd, a);
nmos (y, s1, b);
pmos (y, vdd, a);
pmos (y, vdd, b);
endmodule
Switch-Level description of AND Gate
module and2gate (a, b, y);
input a, b;
output y;
supply1 vdd;
supply0 gnd;
//NAND
nmos n1(s1, gnd, a);
nmos n2(y1, s1, b);
pmos p1(y1, vdd, a);
pmos p2(y1, vdd, b);
//inverter
nmos n3(y, gnd, y1);
pmos p3(y, vdd, y1);
endmodule
Switch-Level description of OR Gate
module OR2gate (a, b, y);
input a, b;
output y;
supply1 vdd;
supply0 gnd;
//NOR
nmos n1(y1, gnd, a);
nmos n2(y1, gnd, b);
pmos p1(s1, vdd, a);
pmos p2(y1, s1, b);
//inverter
nmos n3(y, gnd, y1);
pmos p3(y, vdd, y1);
endmodule
SOP a+bc
module soptb;
reg a,b,c;
module sop(input a,b,c,output y); wire y;
sop x1(a,b,c,y);
initial
supply1 vdd; begin
supply0 gnd; a=0;
repeat(8)
#10 a = ~a;
nmos n1(y,gnd,a); end
nmos n2(s1,gnd,b); initial
begin
nmos n3(y,s1,c); b=0;
repeat(4)
#20 b = ~b;
pmos p1(s2,vdd,a); end
pmos p2(y,s2,b); initial
pmos p3(y,s2,c); begin
c=0;
repeat(2)
endmodule #40 c = ~c;
end
initial
$monitor ($time, " a=%b,b=%b,c=%b,y=%b", a, b,c,y);
endmodule
Stimulus waveforms
0 a=0,b=0,c=0,y=1
10 a=1,b=0,c=0,y=0
20 a=0,b=1,c=0,y=1
30 a=1,b=1,c=0,y=0
40 a=0,b=0,c=1,y=1
50 a=1,b=0,c=1,y=0
60 a=0,b=1,c=1,y=0
70 a=1,b=1,c=1,y=0
80 a=0,b=0,c=0,y=1
POS a(b+c)
module pos(input a,b,c, output y);

supply1 vdd;
supply0 gnd;

nmos n1(s1,gnd,a);
nmos n2(y,s1,b);
nmos n3(y,s1,c);

pmos p1(y,vdd,a);
pmos p2(s2,vdd,b);
pmos p3(y,s2,c);

endmodule
Stimulus waveforms
0 a=0,b=0,c=0,y=1
10 a=1,b=0,c=0,y=1
20 a=0,b=1,c=0,y=1
30 a=1,b=1,c=0,y=0
40 a=0,b=0,c=1,y=1
50 a=1,b=0,c=1,y=0
60 a=0,b=1,c=1,y=1
70 a=1,b=1,c=1,y=0
80 a=0,b=0,c=0,y=1
Switch-Level description of simple combinational logic
module simple_logic (a, b, c, d, e, y);
input a, b, c, d, e;
output y;
supply1 vdd;
supply0 gnd;
nmos n3(s1, gnd, c);
nmos n2 (s2, s1, b);
nmos n1 (y, s2, a);
nmos n5(s3, gnd, e);
nmos n4(y, s3, d);
pmos p1(y, s4, a);
pmos p2(y, s4, b);
pmos p3(y, s4, c);
pmos p4(s4, vdd, d);
pmos p5(s4, vdd, e);
endmodule
2-to-1 Multiplexer
Blk diagram
Switch-Level description of 2 to 1 mux
module mux (s,a,b,y);
output y;
input s,a,b;
wire sbar;
not n1(sb,s);
cmos c1(y, a, sb, s);
cmos c2(y, b, s, sb);
endmodule
Using switches
module mux_switch(
input a,b,s,
output y);
not x(sb,s);
nmos n1(y,a,sb);
pmos p1(y,a,s);

nmos n2(y,b,s);
pmos p2(y,b,sb);

endmodule
Switch-Level description of 2 to 1 mux
module mux(input a,b,s, output y); //stimulus
wire sb; module muxtb;
supply1 vdd; reg a,b,s;
wire y;
supply0 gnd;
mux c(a,b,s,y);
not x1(sb,s); initial
nmos n1 (yb,s1,a); begin
nmos n2 (s1,gnd,sb); s=0;a=0;b=1;
nmos n3 (yb,s2,b); #10 a=1;
nmos n4 (s2,gnd,s); #10 s=1;
nmos n5 (y,gnd,yb); #10 b=0;
#50 $stop;
pmos p1 (s3,vdd,a);
end
pmos p2 (s3,vdd,sb);
pmos p3 (yb,s3,b); initial
pmos p4 (yb,s3,s); $monitor($time, " s= %b,a=%b,b=%b,y=%b", s,a,b,y);
pmos p5 (y,vdd,yb); endmodule
endmodule
Stimulus output
0 s= 0,a=0,b=1,y=0
10 s= 0,a=1,b=1,y=1
20 s= 1,a=1,b=1,y=1
30 s= 1,a=1,b=0,y=0
SR Latch
Logic diagram Switch-level logic diagram
Switch-Level description of Latch
module SR_latch (S, R, Q, Qbar);
input S, R;
output Q, Qbar;
supply1 vdd;
supply0 gnd;
nmos n1 (Qbar, gnd, S);
nmos n2 (Qbar, gnd, Q);
pmos p1 (s0, vdd, Q);
pmos p2 (Qbar, s0, S);
nmos n3 (Q, gnd, Qbar);
nmos n4 (Q, gnd, R);
pmos p3 (s1, vdd, R);
pmos p4 (Q, s1, Qbar);
endmodule
Bidirectional Switches
Bidirectional switches conduct in both directions.
Three keywords are used to define bidirectional switches:
tran tran t1(inout1,inout2);

tranifo
tranifO (inoutl, inout2, control);

tranif1 tranifl (inoutl, inout2, control);

Combinational function
module combi(input a,b,c,d,e,output y );
supply1 vdd;
supply0 gnd;
tranif1 (s1, gnd, c);
tranif1 (s2, s1, b);
tranif1 (y, s2, a);
tranif1 (s3, gnd, e);
tranif1 (y, s3, d);
tranif0 (y, s4, a);
tranif0 (y, s4, b);
tranif0 (y, s4, c);
tranif0 (s4, vdd, d);
tranif0 (s4, vdd, e);
endmodule
Resistive Switches
MOS, CMOS, and bidirectional switches can be modeled as
corresponding resistive devices.
Resistive switches have higher source-to-drain impedance than regular
switches and reduce the strength of signals passing through them.
Resistive switches are declared with keywords that have an "r" prefixed
to the corresponding keyword for the regular switch.

rnmos rpmos //resistive nmos and pmos switches

rcmos //resistive cmos switch
rtran rtranif0 rtranifl //resistive bidirectional switches.
Delay Specification on Switches
Delays can be specified for signals that pass through these switch-level
elements.
Delays are optional and appear immediately after the keyword for the
switch.
Delay Specification on MOS and CMOS Switches
Delay specification for Bidirectional pass switches
Delay specification is interpreted slightly differently for bidirectional
pass switches.
These switches do not delay signals passing through them.
They have turn-on and turn-off delays while switching.
Resistive devices have a high source-to-drain impedance.
Regular switches have a low source-to-drain impedance.
Resistive switches reduce signal strengths when signals pass through
them.
Regular switches retain strength levels of signals from input to output.
The exception is that if the input is of strength supply, the output is of
strength strong.
Strength Reduction by Resistive Switches
D-FF

FF
CMOS Flip-flop
module cff ( q, qbar, d, clk);
output q, qbar;
input d, clk;
wire e;
wire nclk;
my-not nt(nclk, clk);
cmos (e, d, clk, nclk) ;
cmos (e, q, nclk, clk) ;
my-not ntl(qbar, e) ;
my-not nt2(q, qbar) ;
endmodule