MODULE-2

Combinational Logic
(Chapter-4)

Sequential Logic
(Chapter-5)

Combinational Logic
(Chapter-4)
 INTRODUCTION
• Logic circuits for digital systems may be combinational or
sequential.

• A combinational circuit consists of logic gates whose outputs at

any time are determined from only the present combination of
inputs. A combinational circuit performs an operation that can be
specified logically by a set of Boolean functions.

• Sequential circuits employ storage elements in addition to logic

gates. Their outputs are a function of the inputs and the state of
the storage elements.

• The outputs of a sequential circuit depend not only on present

values of inputs, but also on past inputs, and the circuit behavior
must be specified by a time sequence of inputs and internal states.

COMBINATIONAL CIRCUITS
• A combinational circuit consists of an interconnection of logic
gates. Combinational logic gates react to the input signals and
produce the value of the output signal, transforming binary
information from the given input data to a required output data.

For n input variables, there are 2n possible combinations of the

binary inputs. For each possible input combination, there is one
possible value for each output variable. Thus, a combinational circuit
can be specified with a truth table that lists the output values for
each combination of input variables.
 COMBINATIONAL CIRCUITS
A combinational circuit also can be described by m Boolean
functions, one for each output variable. Each output function is
expressed in terms of the n input variables.

There are several combinational circuits that are employed

extensively in the design of digital systems. These circuits are
available in integrated circuits and are classified as standard
components. They perform specific digital functions commonly
needed in the design of digital systems.

In this chapter, we introduce the most important standard

combinational circuits, such as adders, subtractors, comparators,
decoders, encoders, and multiplexers. These components are
available in integrated circuits as medium-scale integration (MSI)
circuits.

DESIGN PROCEDURE
The procedure for the design of combinational circuits involves the
following steps:
1. From the specifications of the circuit, determine the required
number of inputs and outputs and assign a symbol to each.
2. Derive the truth table that defines the required relationship
between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a
function of the input variables.
4. Draw the logic diagram and verify the correctness of the design
(manually or by simulation).

• A truth table for a combinational circuit consists of input columns

and output columns.
• The input columns are obtained from the 2n binary numbers for
the n input variables.
• The output functions specified in the truth table give the exact
definition of the combinational circuit.
 DESIGN PROCEDURE
Code Conversion Example: The circuit design procedure to convert
binary coded decimal (BCD) to the excess-3 code for the decimal
digits.
The truth table relating the input and output variables is shown in
Table below:

DESIGN PROCEDURE
The maps are plotted to obtain simplified Boolean functions for the
outputs.
 DESIGN PROCEDURE
The expressions obtained from Karnaugh maps may be manipulated
algebraically for the purpose of using common gates for two or more
outputs.

DESIGN PROCEDURE
 BINARY ADDER-SUBTRACTOR
• A combinational circuit that performs the addition of two bits is
called a half adder .

• A combinational circuit that performs the addition of three bits

(two significant bits and a previous carry) is called a full adder .

• The two half adders can be employed to implement a full adder.

• A binary adder–subtractor is a combinational circuit that performs

the arithmetic operations of addition and subtraction with binary
numbers.

Half Adder
The Half Adder circuit needs two binary inputs and two binary
outputs. The input variables designate the augend and addend bits;
the output variables produce the sum and carry.

We assign symbols x and y to the two inputs and S (for sum) and C
(for carry) to the outputs. The truth table for the half adder is listed
in the Table given below . The C output is 1 only when both inputs
are 1. The S output represents the least significant bit of the sum.

The simplified sum-of-products expressions are

S = xy’ + x’y
C = xy
 Half Adder
Implementation of half adder

Full Adder
A full adder is a combinational circuit that forms the arithmetic sum of
three bits. It consists of three inputs and two outputs. Two of the input
variables, denoted by x and y , represent the two significant bits to be
added. The third input, z , represents the carry from the previous lower
significant position.

The two outputs are designated by the symbols S for sum and C for
carry. The binary variable S gives the value of the least significant bit of
the sum. The binary variable C gives the output carry formed by adding
the input carry and the bits of the words.
 Full Adder
Implementation using basic gates.

The simplified expressions are

S = x’y’z + x’yz’ + xy’z’ + xyz
C = xy + xz + yz

Full Adder
 Binary Adder
A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers. It can be constructed with full adders
connected in cascade, with the output carry from each full adder
connected to the input carry of the next full adder in the chain.

Four-bit binary ripple carry adder:

• An n -bit adder requires n full adders, with each output carry
connected to the input carry of the next higher order full adder.

Binary Adder
• The augend bits of A and the addend bits of B are denoted by
subscript numbers from right to left. The carries are connected in a
chain through the full adders. The input carry to the adder is C0, and
it ripples through the full adders to the output carry C4. The S
outputs generate the required sum bits.
• An n -bit adder requires n full adders, with each output carry
connected to the input carry of the next higher order full adder.

Consider the two binary numbers A = 1011 and B = 0011. Their sum
S = 1110 is formed with the four-bit adder as follows:

The bits are added with full adders, starting from the least significant position (subscript
0), to form the sum bit and carry bit.
 Binary Adder
Carry Propagation:
As in any combinational circuit, the signal must propagate through the
gates before the correct output sum is available in the output
terminals. The total propagation time is equal to the propagation
delay of a typical gate, times the number of gate levels in the circuit.
• The longest propagation delay time in an adder is the time it takes
the carry to propagate through the full adders.
• Since each bit of the sum output depends on the value of the input
carry, the value of Si at any given stage in the adder will be in its
steady-state final value only after the input carry to that stage has
been propagated.

Binary Adder
Carry Propagation:
• The signals at Pi and Gi settle to their steady-state values after they
propagate through their respective gates. These two signals are common to
all half adders and depend on only the input augend and addend bits
• The signal from the input carry Ci to the output carry Ci+1 propagates
through an AND gate and an OR gate, which constitute two gate levels.
• If there are four full adders in the adder, the output carry C4 would have
2 x 4 = 8 gate levels from C0 to C4. For an n -bit adder, there are 2n gate
levels for the carry to propagate from input to output.
 Binary Adder
Carry lookahead logic : Consider the circuit of the full adder shown below:

Binary Adder
carry lookahead logic : Consider the circuit of the full adder shown below:
We now write the Boolean functions for the carry outputs of each stage and
substitute the value of each Ci from the previous equations:

C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1
= G1 + P1(G0 + P0C0)
= G1 + P1G0 + P1P0C0
C3 = G2 + P2C2
= G2 + P2(G1 + P1G0 + P1P0C0 )
= G2 + P2G1 + P2P1G0 +P2P1P0C0

The three Boolean functions

for C1, C2, and C3 are
Implemented in the carry
lookahead generator
shown in Fig.
 Binary Adder
The construction of a four-bit adder with a carry lookahead scheme is shown in Fig.

Binary Subtractor
• The subtraction of unsigned binary numbers can be done by means
of complements.
• The subtraction A - B can be done by taking the 2’s complement of
B and adding it to A .
The 2’s complement can be obtained by taking the 1’s complement and
adding 1 to the least significant pair of bits. The 1’s complement can be
implemented with inverters, and a 1 can be added to the sum through
the input carry.
 Overflow
• When two numbers with n digits each are added and the sum is a number
occupying n + 1 digits, we say that an overflow occurred.
• The detection of an overflow after the addition of two binary numbers
depends on whether the numbers are considered to be signed or
unsigned.
• When two unsigned numbers are added, an overflow is detected from the
end carry out of the most significant position.
• In the case of signed numbers, two details are important:
 the leftmost bit always represents the sign, and
 negative numbers are in 2’s-complement form
• When two signed numbers are added, the sign bit is treated as part of the
number and the end carry does not indicate an overflow.
• An overflow may occur if the two numbers added are both positive or both
negative.
• An overflow condition can be detected by observing the carry into the
sign bit position and the carry out of the sign bit position. If these two
carries are not equal, an overflow has occurred.

Overflow
The binary adder–subtractor circuit with outputs C and V is shown in Fig. 4.13 .
• If the two binary numbers are unsigned, then the C bit detects a carry after
addition or a borrow after subtraction.
• If the numbers are signed, then the V bit detects an overflow.
 If V = 0 after an addition or subtraction, then no overflow occurred and the
n -bit result is correct.
 If V = 1, then the result of the operation contains n + 1 bits, but only the
rightmost n bits of the number fit in the space available, so an overflow has
occurred.
• The (n + 1) th bit is the actual sign and has been shifted out of position.
 DECODERS
• Discrete quantities of information are represented in digital
systems by binary codes. A binary code of n bits is capable of
representing up to 2n distinct elements of coded information.
• A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique output
lines.
• If the n-bit coded information has unused combinations, the
decoder may have fewer than 2n outputs.

• These decoders are called n -to- m -line decoders, where m <= 2n.
Their purpose is to generate the 2n (or fewer) minterms of n input
variables. Each combination of inputs will assert a unique output.

• The name decoder is also used in conjunction with other code

converters, such as a BCD-to-seven-segment decoder.

DECODERS
As an example, a three-to-eight-line decoder circuit is shown in Fig. The
three inputs are decoded into eight outputs, each representing one of
the minterms of the three input variables.
 DECODERS
Two-to-four-line decoder with enable input:
Some decoders are constructed with NAND gates. Decoders include one
or more enable inputs to control the circuit operation. A two-to-four-
line decoder with an enable input constructed with NAND gates is
shown in Fig. The circuit operates with complemented outputs and a
complement enable input. The decoder is enabled when E is equal to 0
(i.e., active-low enable).

DECODERS
Design of Larger Decoders:
Decoders with enable inputs can be connected together to form a larger
decoder circuit. Figure 4.20 shows two 3-to-8-line decoders with enable
inputs connected to form a 4-to-16-line decoder.
• When w = 0, the top
decoder is enabled and the
other is disabled.
• The bottom decoder
outputs are all 0’s, and the
top eight outputs generate
minterms 0000 to 0111.
• When w = 1, the enable
conditions are reversed: The
bottom decoder outputs
generate minterms 1000 to
1111, while the outputs of
the top decoder are all 0’s.
 DECODERS
Combinational Logic Implementation: Any Boolean function can be
expressed in sum-of-minterms form. A decoder with an external OR gate
will form their logical sum. Hence it provides a hardware implementation of
the function.
In this way, any combinational circuit with n inputs and m outputs can be
implemented with an n -to-2n -line decoder and m OR gates.
Example: To implement a full-adder circuit. From the truth table of the full
adder, we obtain the functions for the combinational circuit in sum-of-minterms
form:

Since there are three

inputs and a total of eight
minterms, we need a
three-to-eight-line
decoder.

ENCODERS
• An encoder is a digital circuit that performs the inverse operation of a
decoder. An encoder has 2n (or fewer) input lines and n output lines. The
output lines, as an aggregate, generate the binary code corresponding to
the input value.
• An example of an encoder is the octal-to-binary encoder whose truth
table is given in Table 4.7 . It has eight inputs (one for each of the octal
digits) and three outputs that generate the corresponding binary number.
• It is assumed that only one input has a value of 1 at any given time.
 ENCODERS
The encoder can be implemented with OR gates whose inputs are
determined directly from the truth table.
Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
Output y is 1 for octal digits 2, 3, 6, or 7, and
Output x is 1 for digits 4, 5, 6, or 7.

These conditions can be expressed by the following Boolean output

functions:

The encoder can be implemented with three OR gates.

ENCODERS
Ambiguity:
1. The encoder defined in Table 4.7 has the limitation that only one input can
be active at any given time. If two inputs are active simultaneously, the
output produces an undefined combination. To resolve this ambiguity,
encoder circuits must establish an input priority to ensure that only one
input is encoded.
2. An output with all 0’s is generated when all the inputs are 0; but this output
is the same as when D0 is equal to 1. The discrepancy can be resolved by
providing one more output to indicate whether at least one input is equal
to 1.
 Priority Encoder
A priority encoder is an encoder circuit that includes the priority
function. The operation of the priority encoder is such that if two or
more inputs are equal to 1 at the same time, the input having the
highest priority will take precedence.

The truth table of a four-input priority encoder is given in Table 4.8 .

In addition to the two outputs x and y , the circuit has a third output
designated by V ; this is a valid bit indicator that is set to 1 when one
or more inputs are equal to 1. If all inputs are 0, there is no valid
input and V is equal to 0.

The other two outputs are not inspected when V equals 0 and are
specified as don’t-care conditions.

Priority Encoder
A priority encoder is an encoder circuit that includes the priority function.
The operation of the priority encoder is such that if two or more inputs are
equal to 1 at the same time, the input having the highest priority will take
precedence.

The truth table of a four-input priority encoder is given in Table 4.8 . In

addition to the two outputs x and y , the circuit has a third output
designated by V ; this is a valid bit indicator that is set to 1 when one or
more inputs are equal to 1. If all inputs are 0, there is no valid input and V is
equal to 0.
The other two outputs are
not inspected when V
equals 0 and are specified
as don’t-care conditions.
 Priority Encoder
• According to Table 4.8 , the higher the subscript number, the higher the
priority of the input.
• Input D3 has the highest priority, so, regardless of the values of the other
inputs, when this input is 1, the output for xy is 11 (binary 3).
• D2 has the next priority level. The output is 10 if D2 = 1, provided that D3
= 0, regardless of the values of the other two lower priority inputs.
• The output for D1 is generated only if higher priority inputs are 0, and so
on down the priority levels.

Priority Encoder
• The maps for simplifying outputs x and y are shown in Fig. 4.22 .
• The minterms for the two functions are derived from Table 4.8.
 Priority Encoder
• The simplified Boolean expressions for the priority encoder are obtained
from the maps.
• The condition for output V is an OR function of all the input variables.
• The priority encoder is implemented in Fig. 4.23 according to the
following Boolean functions:

MULTIPLEXERS