Embedded Systems with ARM Cortex-M Microcontrollers in

Assembly Language and C

CSE331: Microprocessor Interfacing and

Embedded Systems

Lecture#19: Analog-to-Digital Converter (ADC)

Part#2- Chapter 20
Summer, 2023

Mohammad A. Qayum, Ph.D.

ECE, NSU, Dhaka, Bangladesh

1
Successive-approximation (SAR) ADC

2
 Determining Minimum Sampling Time

Sampling time is software

programmable!

Smaller sampling error

Larger sampling time Tradeo
Slower ADC speed
ff
3
Successive-approximation (SAR) ADC

• Binary search algorithm to

gradually approaches the
input voltage
• Settle into ±½ LSB bound
within the time allowed

is software configurable

4
SAR: Successive Approximation Register

The binary weights

assigned to each bit,
(Dx) starting with the
MSB, are 2.5, 1.25,
0.625, 0.3125, 0.15625,
0.078125, 0.0390625,
0.01953125,
0.009765625,
0.0048828125. All of
these add up to
4.9951171875, meaning
binary 1111111111, or
one LSB less than 5.

5
ADC Conversion Time

Suppose ADCCLK = 16 MHz and Sampling time = 4 cycles

For 12-bit ADC

For 6-bit ADC

6
Programming ADC Sampling Time

4 cycles
9 cycles
HSI Clock ADC Clock
Prescaler 16 cycles

Selection
16 MHz /1, /2, /4
24 cycles
default prescaler = 1 48 cycles
96 cycles
192 cycles
384 cycles

ADC sample time register (SMPR)

7
Data Alignment

8
ADC: Regular vs injected

9
ADC Mode

10
ADC Mode
Regular channel:
1. Set SWSTART in ADC_CR2
2. The channel is selected by SQ1[4:0]
in SQR5
3. Result is stored in ADC_DR
4. EOC is set after conversion
5. Interrupt is generated if EOCIE is set

Injected channel:
1. Set JSWSTART in ADC_CR2
2. The channel is selected by JSQ1[4:0]
in JSQR
3. Result is stored in ADC_JDR1
4. JEOC is set after conversion
5. Interrupt is generated if JEOCIE is set

11
ADC Mode
Channels are
selected by
ADC_SQRx
registers for
regular channels,
and by ADC_JSQR
register for
injected channel

All channels in a
regular group
share the same
result register
ADC_DR. Make
sure to read data
between
consecutive
sampling.

12
Analog Watchdog
Analog voltage
Two programmable thresholds

Higher threshold (HTR)

Guarded Area
Lower threshold (LTR)

If V < VLTR or V > VHTR, the analog watchdog (AWD) flag (in ADC Status Register)
is set, generating an interrupt to the processor
The monitor is automatically performed by hardware, not software
Convenient and efficient feature
Help processor detect exceptions and recover from specific situations
For example, monitor sensor data and raise alarm on some level.

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Example: ADC with Timer Interrupts
Main program

ADC
Set up timer timer
interrupt
interrupt
Timer ADC
Timer ISR
Peripheral Peripheral

Wait for Set ADC_Done flag ADC ISR

DAC_Done = 1

Process Data
ISR = Interrupt Service Routine
TIMER ISR starts ADC
Repeat ADC samples multiple channels
ADC ISR copies ADC data register to memory

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Example: ADC with Timer and DMA
Main program
Set up DMA
Set up timer timer
sampling
interrupt
channels DMA
Timer ADC Controller
Timer ISR
Peripheral Peripheral

Wait for Set DMA_Done flag

DMA_Done = 1

Process Data
Timer ISR starts ADC and DMA
DMA automatically copies ADC results
Repeat
of multiple channels to memory after
each conversion

15