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Endterm - HKII 2022 2023

The document is an exam for a digital system design course. It contains 5 questions testing knowledge of Verilog HDL, including writing code for structural, behavioral and procedural modeling of a full adder, designing a single port RAM with a testbench, differences between modules and tasks, and anticipating synthesis results for code snippets.

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Lien Mai
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34 views2 pages

Endterm - HKII 2022 2023

The document is an exam for a digital system design course. It contains 5 questions testing knowledge of Verilog HDL, including writing code for structural, behavioral and procedural modeling of a full adder, designing a single port RAM with a testbench, differences between modules and tasks, and anticipating synthesis results for code snippets.

Uploaded by

Lien Mai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIVERSITY OF INFORMATION END TERM EXAMINATION

TECHNOLOGY 2nd Semester 2022-2023


FACULTY OF COMPUTER ENGINEERING CE213- DIGITAL SYSTEM DESIGN
WITH HDL
(Students are allowed to use document in only Time:80 mins
one A4 paper)

Students need only do Question 1, 2, 3, 4. Question 5 is done and reported on class.


Question 1 (1.5 pts):

Write Verilog code for a Full adder 3-bits in three ways:

- Use structural modeling (assume module FullAdder1bit is available)


- Use behavioral modeling with continuous assignment
- Use behavioral modeling with procedural assignment

Question 2 (2.5 pts)

a) Write a single port RAM as in image below:

Assume: Clock: Positive edge, en: as chip_select (allow read/write), we = 1: write enable,
we = 0: read enable, addr: address (3-bit ), din, dout: data 8-bit
b) Write a testbench to check the design (must use $display or $monitor to observe the
result)
Question 3 (1 pt):

Describe the difference between a module and a task in Verilog.

Write a function to calculate the maximum of two input values, then create a Verilog
module to call that function.

Question 4 (2 pts): Anticipate synthesis result for the Verilog codes below. Draw the
circuit after synthesis.

1
a)

b)

Question 5 (3pts)

Design circuit for LIFO/FIFO/image processing algorithm/simple pipeline micro-processor using


Verilog (done and reported in class)

This examination’s learning outcomes (LO) (matching to subject syllabus’s LO)

Question LO Description
1, 3, 4 G2.2 Understand the basic and advanced knowledge of the
computer engineering major.
2, 5 G4.1 Be able to design a basic digital system
1, 2, 3, 4, 5 G6.2 Be able to read to understand, present, discuss the
technical issues by English

Approved by Head of Subject Designed by

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