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DSA Programs

The document describes a 4-bit gray code generator module called GD_4b that takes in 4 input bits gc3, gc2, gc1, gc0 and outputs the corresponding 4-bit gray code values b3, b2, b1, b0 with different propagation delays. It also contains a module called GE_4b that performs the inverse operation of converting a 4-bit binary value to its gray code equivalent. The document contains the Verilog code implementation and description of logic for these gray code conversion modules.

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Thekkepat Sankalp
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15 views6 pages

DSA Programs

The document describes a 4-bit gray code generator module called GD_4b that takes in 4 input bits gc3, gc2, gc1, gc0 and outputs the corresponding 4-bit gray code values b3, b2, b1, b0 with different propagation delays. It also contains a module called GE_4b that performs the inverse operation of converting a 4-bit binary value to its gray code equivalent. The document contains the Verilog code implementation and description of logic for these gray code conversion modules.

Uploaded by

Thekkepat Sankalp
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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oduLe HA(

input A,B,
output suR, GOUt
Xor(sun, A,B);
and(Cout,A,D);
endnodule

nodule FA
output Sum,CoUt,
input in1, in2, cin
wire w1, w2, w3;.
HA HA1(
.A (in1)
.B (in2).
.SUM (w1),
.Cout (w2)

A (ein),
(w1),
SUM
Cout

or(covt,W2,w3)
podule HA_delay(
input A,B,
output sum, Cout

xor #( ) (sum,A,B);
and #1) (Cout,A,B);
endrodule

nodule FA_delay(
output sum,cout,
input in1,in2, cin
wire w1,w2, w3;
HA_delay HA_delay1(
.A (in1),
B (in2),
-SUM (w1),
.Cout (w2)
HA_delay HA_delay2(
.A (cin),
.B (w1),
"SUm
Cout
(sum)
(w3)
or #1) (cout,w2,w3)a
67 MUX in1,
input
Output
FA_ in2,cin,
sum,
mOdule
68
W1,W2
69 [7:0]
70 input
71
72 MUX8_1 SUM( Cini,in2,
(W1), cin}),
73)3 .X
-sel
74
75 .Y
(sun)
76
77
78
79 MUX8 1 cOUT(
(W2),
80
81
.X
.sel
((in1,in2,cin}),
82 (cout)
83
84
Nodule MUX8_1(
output out,
input [2:0]sel,
input [7:0]d in
wire wl,w2;
MUX4_1 M1(
.X
Sel
({d_in[3],C
({sel[1], sel
(w1)

MUX4 1 M2(
.X ({d in[7], d_ in[6
.sel ({sel[1], sel[01})
(w2)
);
MUX2 1M3(
.X ({w2, w1}),
.sel (sel[2]),
(out)
Activities D Text Editor Dec 111:52
Open
GD_ 4bv Save
-/Desktop/code/DLD/Labs_2022csb1137
1hodule GD_ 4b(
2 output b3,b2,b1, b0,
3 input gc3,gc2,9c1,gc0
4);
5
6assign b3 = gc3;
assign #2 b2 = ((gc3)&(gc2)) | ((~gc3)&(gc2) );
sassign #4 b1 = ((gc3)&(gc2)&(gc1)) I((gc3)&(-gc2)& (~gc1)) | ((~gc3)&(~gc2)&(gc1)) | ((-gc3)&(gc2) &(~gc1));
9assign #6 bo = (9c3)&(gc2)&(gc1)&(-gco))| (gc3)&(gc2)&(-gc1)&(gco))I((gc3)&(-gc2)&(gc1)&(gc0)) *((-gc3)&(gc2)&(gc1)&(gc®)) I((-g3)&(-gc2)&(-gc1)8(gcO))|
(-gc3)&(-gc2)&(gc1)&(-gcO) )| ((~gc3)&(gc2)&(~gc1)&(~gc0))| ((gc3)&(gc2)&(~gc1)&(~gco));
10endmodule

Veriloav TabWidth8
Activities O Text Editor
Open
1 mOdu le GE_4b(
2 output gc3,gc2,gc1,gc0,
3 input b3,b2,b1, bo
4);
5 assign gc3 = b3;
6 assign #2 gc2 = ((b3)&(-b2))1((-b3)& (b2) );
7 assign #2 gc1 = ((b2)&(~b1))|((-b2) &(b1) );
=

assign #2 gco = ((b1)&(~bO))1((-b1)&(b0) );


9 endmodule

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