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Current Mirrors

This document discusses current mirror circuits. It begins by introducing basic NMOS current mirrors and analyzing them using large and small signal models. It then examines four different current mirror topologies: 1) A cascode current mirror that provides high output impedance but requires large voltage headroom. 2) A high swing cascode that improves voltage swing but introduces a systematic error from mismatched drain voltages. 3) A cascade with drain voltage matching to remove the systematic error but new errors from process variations in the matching resistor. 4) An improved high swing cascode that directly sets the gate voltages of M2 and M5 to equalize drain voltages and minimize errors.

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147 views15 pages

Current Mirrors

This document discusses current mirror circuits. It begins by introducing basic NMOS current mirrors and analyzing them using large and small signal models. It then examines four different current mirror topologies: 1) A cascode current mirror that provides high output impedance but requires large voltage headroom. 2) A high swing cascode that improves voltage swing but introduces a systematic error from mismatched drain voltages. 3) A cascade with drain voltage matching to remove the systematic error but new errors from process variations in the matching resistor. 4) An improved high swing cascode that directly sets the gate voltages of M2 and M5 to equalize drain voltages and minimize errors.

Uploaded by

bommena vishwa teja
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Analog VLSI Circuits

E3 238
Current Mirrors
 References:
• BR – Design of Analog CMOS Integrated Circuits by Behzad Razavi
• A-H: CMOS analog circuit design by Allen and Holdberg
Overview
• Basic current mirrors
̶ Large signal analysis
̶ Small signal analysis
• Cadcode current mirrors

IISc, Analog VLSI Circuits E3 238 2


NMOS diode
• Device is in saturation (why?)
̶ 𝑉𝑉𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉

𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊 2 𝛽𝛽 2
• 𝐼𝐼𝐷𝐷 = 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 = 𝑉𝑉 − 𝑉𝑉𝑇𝑇
2 𝐿𝐿 2 𝑉𝑉𝑇𝑇
2𝐼𝐼𝐷𝐷
• 𝑉𝑉 = 𝑉𝑉𝑇𝑇 +
𝛽𝛽

• Large signal behavior similar to a PN diode

IISc, Analog VLSI Circuits E3 238 3


NMOS diode small signal analysis
𝑣𝑣
• 𝑖𝑖 = 𝑔𝑔𝑚𝑚 𝑣𝑣 + 𝑔𝑔𝑚𝑚𝑚𝑚𝑚𝑚 𝑣𝑣𝑏𝑏𝑏𝑏 +
𝑟𝑟𝑑𝑑𝑑𝑑
• For NMOS diode from ground,
𝑣𝑣𝑏𝑏𝑏𝑏 = 0
• Impedance of a NMOS diode
𝑣𝑣 1
𝑅𝑅𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 = =
𝑖𝑖 𝑔𝑔 + 1
𝑚𝑚 𝑟𝑟𝑑𝑑𝑑𝑑

1 1
• For 𝑔𝑔𝑚𝑚 ≫ , 𝑅𝑅𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 =
𝑟𝑟𝑑𝑑𝑑𝑑 𝑔𝑔𝑚𝑚

IISc, Analog VLSI Circuits E3 238 4


Current sink – NMOS current mirror (1)
• Used for biasing amplifier, active load
• M1 is diode-connected NMOS
𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊1 2
̶ 𝐼𝐼𝑖𝑖 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇
2 𝐿𝐿1

• For M2, same gate voltage is applied


𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊2 2
̶ 𝐼𝐼𝑜𝑜 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇
2 𝐿𝐿2
𝐼𝐼𝑜𝑜 𝑊𝑊2 ⁄𝐿𝐿2 𝑉𝑉𝐺𝐺 −𝑉𝑉𝑇𝑇𝑇 2
• =
𝐼𝐼𝑖𝑖 𝑊𝑊1 ⁄𝐿𝐿1 𝑉𝑉𝐺𝐺 −𝑉𝑉𝑇𝑇𝑇 2
• If threshold voltages are equal 𝑉𝑉𝑇𝑇𝑇 = 𝑉𝑉𝑇𝑇2 (process variation!)
𝐼𝐼𝑜𝑜 𝑊𝑊2 ⁄𝐿𝐿2
• =
𝐼𝐼𝑖𝑖 𝑊𝑊1 ⁄𝐿𝐿1
→ current can be scaled and mirrored by adjusting W/L ratio
IISc, Analog VLSI Circuits E3 238 5
Current sink – NMOS current mirror (2)
• Ideal current source
→ Large output impedance, independent of applied voltage

𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊1 2


• 𝐼𝐼𝑖𝑖 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇 1 + 𝜆𝜆𝑉𝑉𝐺𝐺
2 𝐿𝐿1
𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊2 2
• 𝐼𝐼𝑜𝑜 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇 1 + 𝜆𝜆𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜
2 𝐿𝐿2
• If threshold voltages are equal 𝑉𝑉𝑇𝑇𝑇 = 𝑉𝑉𝑇𝑇2
𝐼𝐼𝑜𝑜 𝑊𝑊2 ⁄𝐿𝐿2 𝐼𝐼𝑜𝑜
• ≈ 1 + 𝜆𝜆 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 − 𝑉𝑉𝐺𝐺 = 1 + 𝜖𝜖
𝐼𝐼𝑖𝑖 𝑊𝑊1 ⁄𝐿𝐿1 𝐼𝐼𝑖𝑖 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖

• Output current gain error 𝜖𝜖 = 𝜆𝜆 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 − 𝑉𝑉𝐺𝐺


𝑉𝑉 −𝑉𝑉
̶ 𝑟𝑟𝑑𝑑𝑑𝑑,𝑜𝑜𝑜𝑜𝑜𝑜 = 1⁄𝜆𝜆𝐼𝐼𝑜𝑜𝑜𝑜𝑜𝑜 ⇒ 𝜖𝜖 = 𝑜𝑜𝑜𝑜𝑜𝑜 𝐺𝐺
𝐼𝐼𝑜𝑜𝑜𝑜𝑜𝑜 𝑟𝑟𝑑𝑑𝑑𝑑,𝑜𝑜𝑜𝑜𝑜𝑜
̶ Large 𝑟𝑟𝑑𝑑𝑑𝑑,𝑜𝑜𝑜𝑜𝑜𝑜 reduces error 𝜖𝜖
IISc, Analog VLSI Circuits E3 238 6
Current sink – NMOS current mirror (3)
• Similar conclusion from small signal analysis
• Output impedance = 𝑟𝑟𝑑𝑑𝑑𝑑𝑑 (How?)
̶ Large!!
̶ Can we make it larger??
• Small signal gain
𝑖𝑖𝑜𝑜𝑜𝑜𝑜𝑜 𝑔𝑔𝑚𝑚𝑚
̶ =
𝑖𝑖𝑖𝑖𝑖𝑖 𝑔𝑔𝑚𝑚𝑚

• Output impedance is large only if the M2 stays in saturation


→ 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 > 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇 , Smaller minimum 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 allows larger output swing!
IISc, Analog VLSI Circuits E3 238 7
Current sink – NMOS current mirror (4)
• What if there is mismatch in the threshold voltage?
̶ Spatial variation in doping density, oxide thickness, trapped oxide density
̶ Mirror ratio wanders off the designed value
• Solution
̶ Smart layout: Arrange mirror devices to minimize average VT variation
̶ Smart design

𝐼𝐼𝑜𝑜 𝑊𝑊2 ⁄𝐿𝐿2 𝑉𝑉𝐺𝐺 −𝑉𝑉𝑇𝑇𝑇 2 𝑥𝑥 2 𝛽𝛽𝑅𝑅 =


𝑊𝑊2 ⁄𝐿𝐿2
, 𝑉𝑉 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇 ,
• R= = = 𝛽𝛽𝑅𝑅 1 + 𝑊𝑊1 ⁄𝐿𝐿1 𝑜𝑜𝑜𝑜
𝐼𝐼𝑖𝑖 𝑊𝑊1 ⁄𝐿𝐿1 𝑉𝑉𝐺𝐺 −𝑉𝑉𝑇𝑇𝑇 2 𝑉𝑉𝑜𝑜𝑜𝑜 𝑥𝑥 = 𝑉𝑉𝑇𝑇𝑇 − 𝑉𝑉𝑇𝑇𝑇

• Goal: minimize sensitivity of R wrt. 𝑥𝑥


𝜕𝜕𝜕𝜕⁄𝜕𝜕𝜕𝜕 𝜕𝜕 ln 𝑅𝑅 2 2
̶ Sensitivity 𝑆𝑆𝑅𝑅 = = = ≈
𝑅𝑅 𝜕𝜕𝜕𝜕 𝑉𝑉𝑜𝑜𝑜𝑜 +𝑥𝑥 𝑉𝑉𝑜𝑜𝑜𝑜

• Choose W/L for specific current such that 𝑉𝑉𝑜𝑜𝑜𝑜 is large enough to reduce 𝑆𝑆𝑅𝑅
̶ Maintaining ratio of W/L (𝛽𝛽𝑅𝑅 ) is not enough!!
IISc, Analog VLSI Circuits E3 238 8
Topology 1: Cascode current mirror

• Good: Output cascode → Large output impedance


̶ 𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑔𝑔𝑚𝑚𝑚 𝑟𝑟𝑂𝑂𝑂 𝑟𝑟𝑂𝑂1
̶ Requires M1 and M2 in saturation
• Bad: Large required voltage headroom, low swing
̶ 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑉𝑉𝑇𝑇 + 2𝑉𝑉𝑜𝑜𝑜𝑜
• What happens as 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 decreases below 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚
̶ M2 goes into linear region first, then M1

Ref: A-H
IISc, Analog VLSI Circuits E3 238 9
Topology 2: High swing cascode
• Generate Vb for the cascode device M2 such
that 𝑉𝑉𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝑜𝑜𝑜𝑜
̶ 𝑉𝑉𝑏𝑏 = 𝑉𝑉𝑇𝑇 + 2𝑉𝑉𝑜𝑜𝑜𝑜
𝑊𝑊 1 𝑊𝑊
̶ Sizing: =
𝐿𝐿 𝑀𝑀𝑀 4 𝐿𝐿 𝑀𝑀2

• Good: High swing 𝑉𝑉𝑏𝑏


̶ 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜,𝑚𝑚𝑚𝑚𝑚𝑚 = 2𝑉𝑉𝑜𝑜𝑜𝑜
• Bad: Systematic error as 𝑉𝑉𝐷𝐷𝐷𝐷𝐷 ≠ 𝑉𝑉𝐷𝐷𝐷𝐷𝐷
̶ 𝑉𝑉𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝑜𝑜𝑜𝑜 , 𝑉𝑉𝐷𝐷𝐷𝐷3 = 𝑉𝑉𝑇𝑇 + 𝑉𝑉𝑜𝑜𝑜𝑜

IISc, Analog VLSI Circuits E3 238 Ref: A-H 10


Topology 3: High swing cascade with VDS
nominally matched
• To make 𝑉𝑉𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷𝐷
• Use R3 such that 𝑉𝑉𝑇𝑇 = 𝐼𝐼𝑅𝑅𝑅𝑅𝑅𝑅 𝑅𝑅3

• Good: Systematic error removed


• Bad: Systematic error comes back
due to a) variation in R3 b) VT and
R3 does not track in temperature
and process

IISc, Analog VLSI Circuits E3 238 11


Topology 4: Improved high swing cascode
• 𝑉𝑉𝐺𝐺𝑆𝑆5 = 𝑉𝑉𝐺𝐺𝑆𝑆2 → 𝑉𝑉𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷𝐷
• Good: M2 and M5 can be matched
better over process and
temperature → no systematic error 𝑉𝑉𝑏𝑏

• Bad: Need a separate biasing leg


which require excess current

Ref: A-H
IISc, Analog VLSI Circuits E3 238 12
Topology 5: Self-biased high-swing cascode
• Good: Self-biased i.e., does not require a
separate biasing current leg
̶ Widely used current mirror topology

• Design requirement: 𝑉𝑉𝑜𝑜𝑜𝑜 = 𝐼𝐼𝑅𝑅𝑅𝑅𝑅𝑅 𝑅𝑅


̶ Same issue of variability, but is it that bad??
̶ 𝑉𝑉𝐷𝐷𝐷𝐷𝐷 ≠ 𝑉𝑉𝐷𝐷𝐷𝐷𝐷 in general; 𝑉𝑉𝐷𝐷𝐷𝐷𝐷 varies with 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂
̶ Conservative design: 𝐼𝐼𝑅𝑅𝑅𝑅𝑅𝑅 𝑅𝑅 > 𝑉𝑉𝑜𝑜𝑜𝑜 for all process
and temperature variations
• Bad: For small 𝐼𝐼𝑅𝑅𝑅𝑅𝑅𝑅 , 𝑅𝑅 can be large
̶ Additional pole, to be understood later..

Ref: A-H
IISc, Analog VLSI Circuits E3 238 13
Current mirror device sizing (design)
• Sizing (W/L) of mirror
𝑊𝑊
devices M1 & M3 depends on
𝐿𝐿 1
̶ Mirroring ratio = 𝑊𝑊
𝐿𝐿 3
̶ VT mismatch sensitivity dictates values of Vod and W/L for target IREF
̶ L larger than minimum size, for large rO1
• Sizing (W/L) of cascode 𝑊𝑊
devices M2 & M4 depends on
𝐿𝐿 2
̶ Same mirroring ratio = 𝑊𝑊 , Why? Keep same VDS for M1 and M3
𝐿𝐿 4
̶ Dependent on VT mismatch, but not as strongly as mirror devices
• VT mismatch of M2 & M4 creates VDS mismatch for M1 and M3
• Same sensitivity analysis can be performed
̶ Usually, cascode devices use small L, small Vod2;
Why? Larger bandwidth, smaller head room
IISc, Analog VLSI Circuits E3 238 14
Layout considerations
• Best practices
̶ Symmetric layout of mirror devices around the reference device
̶ Break reference devices (if possible) in multiple fingers and interdigitate with
mirror devices
̶ Use same basic unit for reference and mirror devices
̶ Use dummy devices at the end
• Purpose
̶ Reduce mismatches

IISc, Analog VLSI Circuits E3 238 15

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