5-1 Chapter 5 - Datapath and Control

Computer Architecture and Organization

Chapter 6 – Datapath and Control

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-2 Chapter 5 - Datapath and Control

Chapter Contents

➢ Basics of the Microarchitecture

➢ The Datapath
➢ The Control Section – Microprogrammed
➢ Developing the Microprogram

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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The Fetch-Execute Cycle

• The steps that the control unit carries out in executing a
program are:
(1) Fetch the next instruction to be executed from memory.
(2) Decode the opcode.
(3) Read operand(s) from main memory, if any.
(4) Execute the instruction and store results, if any.
(5) Go to step 1.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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High Level View of Microarchitecture

• The microarchitecture consists of the control unit and the
programmer-visible registers, functional units such as the
ALU, and any additional registers that may be required by
the control unit.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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A More Detailed View

Microarchitecture consists of a data section (datapath) which contain registers and an ALU
and a control section. Microprogrammed control uses a special-purpose microprogram not
visible to the user, to implement operations on the registers an other parts of the machine.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-6 Chapter 5 - Datapath and Control

ARC Instruction Subset

There are 15 instructions that are grouped into four format according to the leftmost two bits
of the coded instruction. The processor status register %psr is also shown.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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ARC Instruction Formats

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-8 Chapter 5 - Datapath and Control
Always contains the
value 0,cannot be
changed

A, B and C → simply register selection

The six-bit inputs to the decode select
a single register for each of the A, B, C
buses.
26 = 64 possible output from decode
but only 38 register

ARC
Datapath
Program counter, which
keeps track of the next
instruction to be read
from the main memory Are used in interpreting
the ARC instruction set
and not visible to the
User has direct access to user.
%pc only through call
and jmpl instruction
Holds the current
instruction that is being
executed. Not visible to
the user.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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ARC ALU Operations

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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ARC ALU Operations

Operation Description
ANDCC and AND Perform a bit by bit logical AND of corresponding bits on the A and B
buses
ORCC and OR Perform a bit by bit logical OR of corresponding bits on the A and B
buses
ORNCC and ORN Perform a bit by bit logical A + B not of corresponding bits on the A
and B buses
ADDCC and ADD ADDCC and ADD operations carry out addition using two’s
complement arithmetic on the A and B buses
SRL (shift right location) Operation shifts the contents of the A bus to right by the amount
specified on the B bus (from 0 to 31 bits). Zero are copied into
leftmost bits of the shifted result and the rightmost bits of the result
are discarded.
LSHIFT2 and LSHIFT10 Shift the contents of the A bus to the left by two and 10 bits,
respectively Zeros are copied into the rightmost bits.
SIMM13 Retrieves the least significant 13 bits of the A bus, and places zeros
in the 19 most significant bits.
SEXT13 Performs a sign extension of the 13 least significant bits on the A bus
to form a 32 bit word
INC Increments the value on the A bus by 1
INCPC Increments the value on the A bus by 4, which is used in
incrementing the PC register by one word (four bytes). INCPC can
be used on anyr register placed on the A bus.
RSHIFT5 Shifts the operand on the A bust to the right by five bits. Copying the
leftmost bit (the sign bit) into the five new bits on the left. This has
the effect of performing a five-bit sign extension.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Outputs to Control Unit from

Register %ir

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Microarchitecture of the ARC

➢ Read only memory (2048-word x

41 bit) that contains values for all
of the lines that must be
controlled to implement each
user-level instruction.
➢ Each 41-bit word is called a
microinstruction

➢ Responsible for fetching

microinstructions and executing
them.
➢ Microinstruction execution is
controlled by the microprogram
instruction register (MIR), the
processor status register (%psr)
and a mechanism to be executed;
the control branch logic (CBL) unit
and the control store (CS) address
MUX.

When the microarchitecture begins operation ( at power on time, cth), a rest circuit (not shown) places
the microword at location 0 In the control store into the MIR and executes it. From that point onward,
a microword is selected for execution from either the next, the decode or the jump inputs to the CS
address MUX, according to the setting in the COND field of the MIR and the output of the CBL logic.
After each microword is placed in the MIR…datapath perform operations..

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Microword Format

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Settings for the COND Field of the Microword

000 – no jump taken

001, 010, 011, 100 or 101 – then a conditional jump is taken
to the control store location in the JUMP ADDR field
n, z, v,or c flag or bit 13 of %ir
IR[13] = bit 13 of the insruction register %ir
COND filed 110 the unconditional jump is taken
111 when an instruction is being decoded

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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DECODE Format for Microinstruction

Address

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Partial
ARC
Micro-
program

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Partial ARC
Microprogram
(cont’)

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Translating the Microprogram

0: R[ir] ← AND(R[pc],R[pc]); READ;

1: DECODE; /256-way jump according to opcode

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Assembled
ARC
Microprogram

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Assembled
ARC
Microprogram
(cont’)

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Example: Add the subcc Instruction

• Consider adding instruction subcc (subtract) to the ARC instruction set.
subcc uses the Arithmetic format and op3 = 001100.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring