UNIT III

Key elements of a computer (components/modules) are processor, memory and I/O

devices. I/O module contains logic for performing a communication function between the
peripheral and the bus.
Generic Model of an I/O Module

Need for an I/O module

a. A variety of peripherals uses various operating methods. It is difficult for the processor to
control a vast range of devices.
b. Data transfer rates of peripherals is slower than that of the processor. Thus it is impractical
to use high speed system bus to directly communicate with the peripherals.
c. The data transfer rate of some peripherals is faster than that of the memory or processor.
Again, the mismatch would lead to inefficiencies if not managed properly.

This module has two major functions

1. Interface to the processor and memory via the system bus or central switch
2. Interface to one or more peripheral devices by tailored data links

External devices
External devices(Peripheral) help in I/O operations by exchanging data between the
external environment and the computer. The external devices are attached to the computer
through an I/O module as shown in the figure. The link is used to exchange control, status, and
data between the I/O module and the external device.
External devices are broadly classified into three categories:
1. Human readable: Suitable for communicating with the user. Ex. Video Display
Terminals (VDTs) and printers.
2. Machine readable: Suitable for communicating with equipment. Ex. magnetic disk and
tape systems, and sensors and actuators(used in robotics application).
3. Communication: Suitable for communicating with remote devices. They may be a
human-readable device or a machine-readable device or even another computer.
Note: From a functional point of view, disks and tapes are part of the memory hierarchy. From a
structural point of view, these devices are controlled by I/O modules.
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 BLOCK DIAGRAM OF AN EXTERNAL DEVICE

Control signals determine the function that the device will perform, such as send data to
the I/O module (READ), accept data from the I/O module (WRITE), report status, or perform
some control function particular to the device (e.g., position a disk head). Data (a set of bits) are
to be sent to or received from the I/O module. Status signals indicate the state of the device.
Examples are READY/NOT-READY for data transfer. Control logic controls the operation of
the device according to the direction from the I/O module. The transducer converts data from
electrical to other forms of energy during output and from other forms to electrical during input.
Buffer is associated with the transducer to temporarily hold data being transferred between the
I/O module and the external environment; a buffer size of 8 to 16 bits is common.
Keyboard/Monitor
The most common means of computer/user interaction is a keyboard/monitor
arrangement. The user provides input through the keyboard. The monitor displays data provided
by the computer. The basic unit of exchange is the character. Associated with each character is a
code, typically 7 or 8 bits in length. The most commonly used text code is the ACSII. Each
character in this code is represented by a unique 7-bit binary code; thus, 128 different characters
can be represented.
Characters are of two types: printable and control. Printable characters are the alphabetic,
numeric, and special characters that can be printed on paper or displayed on a screen. Some of
the control characters have to do with controlling the printing or displaying of characters; an
example is carriage return. Other control characters are concerned with communications
procedures.
For keyboard input, when the user depresses a key, this generates an electronic signal that
is interpreted by the transducer in the keyboard and translated into the bit pattern of the
corresponding ACSII code. This bit pattern is then transmitted to the I/O module in the
computer. At the computer, the text can be stored in the same ASCII code. On output, ASCII
code characters are transmitted to an external device from the I/O module. The transducer at the
device interprets this code and sends the required electronic signals to the output device either to
display the indicated character or perform the requested control function.
Disk Drive
A disk drive contains electronics for exchanging data, control, and status signals with an
I/O module plus the electronics for controlling the disk read/write mechanism. In a fixed-head
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disk, the transducer is capable of converting between the magnetic patterns on the moving disk
surface and bits in the device’s buffer. A moving-head disk must also be able to cause the disk
arm to move radially in and out across the disk’s surface.

I/O Modules
The major functions or requirements for an I/O module fall into the following categories:
i. Control and timing
ii. Processor communication
iii. Device communication
iv. Data buffering
v. Error detection
[At any time, the processor may communicate with one or more external devices in
unpredictable patterns, depending on the program’s need for I/O. The internal resources,
such as main memory and the system bus, must be shared among a number of activities,
including data I/O. Thus,] the I/O function includes a control and timing requirement, to
coordinate the flow of traffic between internal resources and external devices. For
example, the control of the transfer of data from an external device to the processor might
involve the following sequence of steps:
1. The processor interrogates the I/O module to check the status of the attached device.
2. The I/O module returns the device status.
3. If the device is operational and ready to transmit, the processor requests the transfer
of data, by means of a command to the I/O module.
4. The I/O module obtains a unit of data (e.g., 8 or 16 bits) from the external device.
5. The data are transferred from the I/O module to the processor.
The I/O module must communicate with the processor and with the external device. Processor
communication involves the following:
1. Command decoding: The I/O module accepts commands from the processor,
typically sent as signals on the control bus. [For example, an I/O module for a disk
drive might accept the following commands: READ SECTOR, WRITE SECTOR,
SEEK track number, and SCAN record ID. The latter two commands each include a
parameter that is sent on the data bus.]
2. Data are exchanged between the processor and the I/O module over the data bus.
3. Status reporting: Because peripherals are so slow, it is important to know the status
of the I/O module. For example, if an I/O module is asked to send data to the
processor (read), it may not be ready to do so because it is still working on the
previous I/O command. This fact can be reported with a status signal.
Common status signals are BUSY and READY. There may also be signals to report
various error conditions.
4. Address recognition: Each I/O device has an address. Thus, an I/O module must
recognize one unique address for each peripheral it controls.
Device communication involves commands, status information, and data.
Data buffering is required because the transfer rate into and out of main memory or the
processor is quite high compared to that of many peripheral devices. Data coming from main
memory are sent to an I/O module in a rapid burst. The data are buffered in the I/O module and
then sent to the peripheral device at its data rate. In the opposite direction, data are buffered so as
not to tie up the memory in a slow transfer operation. Thus, the I/O module must be able to
operate at both device and memory speeds.
Error detection reports errors to the processor. One class of errors includes mechanical and
electrical malfunctions reported by the device (e.g., paper jam, bad disk track). Another class is
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the change in the bit pattern as it is transmitted from device to I/O module. Some form of error-
detecting code is often used to detect transmission errors. A simple example is the use of a parity
bit on each character of data. For example, the ASCII code occupies 7 bits of a byte. The eighth
bit is set so that the total number of 1s in the byte is even (even parity) or odd (odd parity).When
a byte is received, the I/O module checks the parity to determine whether an error has occurred.

I/O Module Structure

I/O modules vary in complexity and the number of external devices that they control. Figure
below provides a general block diagram of an I/O module. The module connects to the rest of the
computer through a set of signal lines (e.g., system bus lines). Data transferred to and from the
module are buffered in one or more data registers. There may also be one or more status registers
that provide current status information. A status register may also function as a control register.

BLOCK DIAGRAM OF AN I/O MODULE

The logic within the module interacts with the processor via a set of control lines. The processor
uses the control lines to issue commands to the I/O module. The module must also be able to
recognize and generate addresses associated with the devices it controls. Each I/O module has a
unique address. If it controls more than one external device then it has a unique set of addresses.
An I/O module that takes the processing burden is usually referred to as an I/O channel or I/O
processor. An I/O module that requires detailed control is usually referred to as an I/O controller
or device controller. I/O controllers are commonly seen on microcomputers, whereas I/O
channels are used on mainframes.

I/O Techniques
Three techniques are possible for I/O operations.
1. Programmed I/O - data are exchanged between the processor and the I/O module.
2. Interrupt-driven I/O
3. DMA
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With programmed I/O, when the processor issues a command to the I/O module, it must wait
until the I/O operation is complete. If the processor is faster than the I/O module, this is wasteful
of processor time. With interrupt-driven I/O, the processor issues an I/O command, continues to
execute other instructions, and is interrupted by the I/O module when the latter has completed its
work. With both programmed and interrupt I/O, the processor is responsible for extracting data
from main memory for output and storing data in main memory for input. In direct memory
access (DMA), the I/O module and main memory exchange data directly, without processor
involvement.
Relationship between I/O Techniques

Programmed I/O
When an instruction related to I/O is encountered by the processor, it executes that
instruction by issuing a command to the I/O module. The I/O module will perform the requested
action and then set the appropriate bits in the I/O status register. The I/O module does not
interrupt the processor. Thus, the processor must periodically check the status of the I/O module
until it finds that the operation is complete. I/O commands issued by the processor to the I/O
module are of 4 types.
i. Control: Used to activate a peripheral and tell it what to do. For example, a magnetic-tape
unit may be instructed to rewind or to move forward one record.
ii. Test: Used to test various status conditions associated with an I/O module and its
peripherals. ie. is powered on and available for use, or if the most recent I/O operation is
completed and if any errors occurred.
iii. Read: Causes the I/O module to obtain an item of data from the peripheral and place it in an
internal buffer. The processor can then obtain the data item by requesting that the I/O module
place it on the data bus.
iv. Write: Causes the I/O module to take an item of data (byte or word) from the data bus and
subsequently transmit that data item to the peripheral.

Figure (a) gives an example of programmed I/O to read in a block of data from a peripheral
device (e.g., a record from tape) into memory. Data are read in one word (e.g., 16 bits) at a time.
For each word that is read in, the processor must remain in a status-checking cycle until it
determines that the word is available in the I/O module’s data register. The main disadvantage is
this is a time-consuming process that keeps the processor busy needlessly.
I/O Instructions
The I/O-related instructions that the processor fetches from memory are easily mapped
into I/O commands, and there is often a simple one-to-one relationship. The form of the
instruction depends on the addresses of the external devices. Typically, there will be many I/O
devices connected through I/O modules to the system. Each device is given a unique identifier or
address. When the processor issues an I/O command, the command contains the address of the
desired device. Thus, each I/O module must interpret the address lines to determine if the
command is for itself.
When the processor, main memory, and I/O share a common bus, two modes of
addressing are possible: memory mapped and isolated. With memory-mapped I/O, there is a

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single address space for memory locations and I/O devices. The processor treats the status and
data registers of I/O modules as memory locations and uses the same machine instructions to

access both memory and I/O devices. So, for example, with 10 address lines, a total of 1024
memory locations and I/O addresses can be supported, in any combination. With memory-
mapped I/O, a single read line and a single write line are needed on the bus. Alternatively, the
bus may be equipped with memory read and write plus input and output command lines. Now,
the command line specifies whether the address refers to a memory location or an I/O device.
The full range of addresses may be available for both. Again, with 10 address lines, the system
may now support both 1024 memory locations and 1024 I/O addresses. Because the address
space for I/O is isolated from that for memory, this is referred to as isolated I/O.
Thus, an advantage of memory-mapped I/O is that it can use a large number of
instructions, allowing more efficient programming. A disadvantage is that valuable memory
address space is used up. Both memory-mapped and isolated I/O are in common use.
The problem with programmed I/O is that the processor has to wait a long time for the
I/O module of concern to be ready for either reception or transmission of data. The processor,
while waiting, must repeatedly interrogate the status of the I/O module. As a result, the level of
the performance of the entire system is severely degraded.

INTERRUPT-DRIVEN I/O
In this method, the processor issues an I/O command to a module and then go on to do
some other work. The I/O module will then interrupt the processor to request service when it is
ready to exchange data with the processor. The processor then executes the data transfer and then
resumes its former processing.
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 For input, the I/O module receives a READ command from the processor. The I/O
module then proceeds to read data from the associated peripheral. Once the data are in the
module’s data register, the module signals an interrupt to the processor over a control line. The
module then waits until its data are requested by the processor. When the request is made, the
module places its data on the data bus and is then ready for another I/O operation.
From the processor’s point of view, the action for input is as follows. The processor
issues a READ command. It then goes off and does something else (e.g., the processor may be
working on several different programs at the same time). At the end of each instruction cycle, the
processor checks for interrupts. When the interrupt from the I/O module occurs, the processor
saves the context (e.g., program counter and processor registers) of the current program and
processes the interrupt. In this case, the processor reads the word of data from the I/O module
and stores it in memory. It then restores the context of the program it was working on (or some
other program) and resumes execution(figure b). Interrupt I/O is more efficient than programmed
I/O because it eliminates needless waiting. However, interrupt I/O still consumes a lot of
processor time, because every word of data that goes from memory to I/O module or from I/O
module to memory must pass through the processor.
Interrupt Processing
The occurrence of an interrupt triggers a number of events, both in the processor
hardware and in software. The role of the processor in interrupt-driven I/O : When an I/O device
completes an I/O operation, the following sequence of hardware events occurs:
1. The device issues an interrupt signal to the processor.
2. The processor finishes execution of the current instruction before responding to the
interrupt.
3. The processor tests for an interrupt, determines that there is one, and sends an
acknowledgment signal to the device that issued the interrupt. The acknowledgment allows
the device to remove its interrupt signal.
4. The processor now needs to prepare to transfer control to the interrupt routine. To begin, it
needs to save information needed to resume the current program at the point of interrupt.
The minimum information required is (a) the status of the processor, which is contained in
a register called the program status word (PSW), and (b) the location of the next instruction
to be executed, which is contained in the program counter. These can be pushed onto the
system control stack.

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 5. The processor now loads the program counter with the entry location of the interrupt-
handling program that will respond to this interrupt. If there is more than one interrupt-
handling routine, the processor must determine which one to invoke. This information
must be included in the original interrupt signal, or the processor may have to issue a
request to the device that issued the interrupt. The device responses with the needed
information.
Once the program counter has been loaded, the processor proceeds to the next instruction cycle,
which begins with an instruction fetch. The execution of this program results in the following
operations:
6. The program counter and PSW relating to the interrupted program have been saved on
the system stack. However, in particular, the contents of the processor registers need to
be saved, because these registers may be used by the interrupt handler.
7. The interrupt handler next processes the interrupt. This includes an examination of status
information relating to the I/O operation or other event that caused an interrupt. It may
also involve sending additional commands or acknowledgments to the I/O device.
8. When interrupt processing is complete, the saved register values are retrieved from the
stack and restored to the registers.
9. The final act is to restore the PSW and program counter values from the stack.
As a result, the next instruction to be executed will be from the previously interrupted program.

Note that it is important to save all the state information about the interrupted program
for later resumption. This is because the interrupt is not a routine called from the program.
Rather, the interrupt can occur at any time and therefore at any point in the execution of a user
program. Its occurrence is unpredictable.

Design Issues
Two design issues arise in implementing interrupt I/O. First, the processor must
determine which device has issued the interrupt and second, if multiple interrupts have occurred,
the processor must decide which one to process.
Four general categories of techniques are in common use for device identification:
• Multiple interrupt lines
• Software poll
• Daisy chain (hardware poll, vectored)
• Bus arbitration (vectored)
The most straightforward approach to the problem is to provide multiple interrupt lines
between the processor and the I/O modules. However, it is impractical to dedicate more than a
few bus lines or processor pins to interrupt lines. Consequently, even if multiple lines are used,
each line will have multiple I/O modules attached to it. Thus, one of the other three techniques
must be used on each line.
Software poll: When the processor detects an interrupt, it branches to an interrupt-
service routine whose job it is to poll each I/O module to determine which module caused the
interrupt. The poll could be in the form of a separate command line (e.g., TESTI/O). In this case,
the processor raises TESTI/O and places the address of a particular I/O module on the address
lines. The I/O module responds positively if it set the interrupt. The processor then reads the
status register of each I/O module to identify the interrupting module. Once the correct module is
identified, the processor branches to a device-service routine specific to that device.
Disadvantage: It is time consuming.
A more efficient technique is to use a daisy chain, which provides a hardware poll. For
interrupts, all I/O modules share a common interrupt request line. The interrupt acknowledge line
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is daisy chained through the modules. When the processor senses an interrupt, it sends out an
interrupt acknowledge. This signal propagates through a series of I/O modules until it gets to a
requesting module. The requesting module typically responds by placing a word on the data
lines. This word is referred to as a vector and is either the address of the I/O module or some
other unique identifier. In either case, the processor uses the vector as a pointer to the appropriate
device-service routine. This avoids the need to execute a general interrupt-service routine first.
This technique is called a vectored interrupt.
There is another technique that makes use of vectored interrupts which is bus
arbitration. With bus arbitration, an I/O module must first gain control of the bus before it can
raise the interrupt request line. Thus, only one module can raise the line at a time. When the
processor detects the interrupt, it responds on the interrupt acknowledge line. The requesting
module then places its vector on the data lines.
The above mentioned techniques serve to identify the requesting I/O module. They also
provide a way of assigning priorities when more than one device is requesting interrupt service.
With multiple lines, the processor just picks the interrupt line with the highest priority. With
software polling, the order in which modules are polled determines their priority. Similarly, the
order of modules on a daisy chain determines their priority.
Drawbacks of Programmed and Interrupt-Driven I/O
Interrupt-driven I/O, though more efficient than simple programmed I/O, still requires the
active intervention of the processor to transfer data between memory and an I/O module, and any
data transfer must traverse a path through the processor. Thus, both these forms of I/O suffer
from two inherent drawbacks:
1. The I/O transfer rate is limited by the speed of the processor and a device.
2. For I/O transfer, the processor has to execute a number of instructions.

DIRECT MEMORY ACCESS (DMA)

When large volumes of data are to be moved, a more efficient technique is required i:
DMA. DMA involves an additional module on the system bus. The DMA module is capable of
mimicking the processor and, indeed, of taking over control of the system from the processor. It
needs to do transfer data to and from memory over the system bus. For this purpose, the DMA
module must use the bus only when the processor does not need it, or it must force the processor
to suspend operation temporarily. The latter technique is more common and is referred to as
cycle stealing, because the DMA module in effect steals a bus cycle.
DMA Block Diagram

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When the processor wishes to read or write a block of data, it issues a command to the DMA
module, by sending to the DMA module the following information:
1. Whether a read or write is requested, using the read or write control line between the
processor and the DMA module.
2. The address of the I/O device involved
3. The starting location in memory to read from or write to.
4. The number of words to be read or written, communicated via the data lines and stored in
the data count register
The processor assigns this I/O operation to the DMA module. The DMA module transfers the
entire block of data, one word at a time, directly to or from memory, without going through the
processor. When the transfer is complete, the DMA module sends an interrupt signal to the
processor. Thus, the processor is involved only at the beginning and end of the I/O transfer. In
each case, the processor is suspended just before it needs to use the bus. The DMA module then
transfers one word and returns control to the processor. Note that this is not an interrupt; the
processor does not save a context and do something else. Rather, the processor pauses for one
bus cycle. For a multiple-word I/O transfer, DMA is far more efficient than interrupt-driven or
programmed I/O.

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 The DMA mechanism can be configured in a variety of ways. Some possibilities are
shown in the Figure. In figure a, all modules share the same system bus. The DMA module uses
programmed I/O to exchange data between memory and an I/O module. This configuration,
although inexpensive, is clearly inefficient. As with processor-controlled programmed I/O, each
transfer of a word consumes two bus cycles. The number of required bus cycles can be cut
substantially by integrating the DMA and I/O functions. As Figure b indicates, there is a path
between the DMA module and one or more I/O modules that does not include the system bus.
The DMA logic may actually be a part of an I/O module, or it may be a separate module that
controls one or more I/O modules. This concept can be taken one step further by connecting I/O
modules to the DMA module using an I/O bus as in Figure c. This reduces the number of I/O
interfaces in the DMA module to one and provides an easily expandable configuration. In cases
of b and c, the system bus that the DMA module shares with the processor and memory is used
by the DMA module only to exchange data with memory. The exchange of data between the
DMA and I/O modules takes place off the system bus.

Intel 8237A DMA Controller

The Intel 8237A DMA controller interfaces to the 80x86 family of processors and to
DRAM memory to provide a DMA capability. When the DMA module needs to use the system
buses (data, address, and control) to transfer data, it sends a signal called HOLD to the processor.
The processor responds with the HLDA (hold acknowledge) signal, indicating that the DMA
module can use the buses. For example, if the DMA module is to transfer a block of data from
memory to disk, it will do the following:
1. The peripheral device (such as the disk controller) will request the service of DMA by pulling
DREQ (DMA request) high.
2. The DMA will put a high on its HRQ (hold request), signaling the CPU through its HOLD pin
that it needs to use the buses.
3. The CPU will finish the present bus cycle (not necessarily the present instruction) and respond
to the DMA request by putting high on its HDLA (hold acknowledge), thus telling the 8237
DMA that it can go ahead and use the buses to perform its task. HOLD must remain active high
as long as DMA is performing its task.
4. DMA will activate DACK (DMA acknowledge), which tells the peripheral device that it will
start to transfer the data.
8237 DMA Usage of System Buses

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5. DMA starts to transfer the data from memory to peripheral by putting the address of the first
byte of the block on the address bus and activating MEMR, thereby reading the byte from
memory into the data bus; it then activates IOW to write it to the peripheral. Then DMA
decrements the counter and increments the address pointer and repeats this process until the
count reaches zero and the task is finished.
6. After the DMA has finished its job it will deactivate HRQ, signaling the CPU that it can regain
control over its buses.
The 8237 contains four DMA channels that can be programmed independently, and any
one of the channels may be active at any moment. These channels are numbered 0, 1, 2, and 3.
The 8237 has a set of five control/command registers to program and control DMA operation
over one of its channels
• Command: The processor loads this register to control the operation of the DMA. D0 enables
a memory-to-memory transfer, in which channel 0 is used to transfer a byte into an 8237
temporary register and channel 1 is used to transfer the byte from the register to memory. When
memory-to-memory is enabled, D1 can be used to disable increment/decrement on channel 0 so
that a fixed value can be written into a block of memory. D2 enables or disables DMA.
• Status: The processor reads this register to determine DMA status. Bits D0–D3 are used to
indicate if channels 0–3 have reached their TC (terminal count). Bits D4–D7 are used by the
processor to determine if any channel has a DMA request pending.
Mode: The processor sets this register to determine the mode of operation of the DMA. Bits D0
and D1 are used to select a channel. The other bits select various operation modes for the
selected channel. Bits D2 and D3 determine if the transfer is a from an I/O device to memory
(write) or from memory to I/O (read), or a verify operation. If D4 is set, then the memory address
register and the count register are reloaded with their original values at the end of a DMA data
transfer. Bits D6 and D7 determine the way in which the 8237 is used. In single mode, a single
byte of data is transferred. Block and demand modes are used for a block transfer, with the
demand mode allowing for premature ending of the transfer. Cascade mode allows multiple
8237s to be cascaded to expand the number of channels to more than 4.
• Single Mask: The processor sets this register. Bits D0 and D1 select the channel. Bit D2 clears
or sets the mask bit for that channel. It is through this register that the DREQ input of a specific
channel can be masked (disabled) or unmasked (enabled).While the command register can be
used to disable the whole DMA chip, the single mask register allows the programmer to disable
or enable a specific channel.
• All Mask: This register is similar to the single mask register except that all four channels can
be masked or unmasked with one write operation. In addition, the 8237A has eight data registers:
one memory address register and one count register for each channel. The processor sets these
registers to indicate the location of size of main memory to be affected by the transfers.

I/O CHANNELS AND PROCESSORS

The Evolution of the I/O Function
1. The CPU directly controls a peripheral device. This is seen in simple microprocessor-
controlled devices.
2. A controller or I/O module is added. The CPU uses programmed I/O without interrupts.
3. The same configuration as in step 2 is used, but now interrupts are employed. The CPU need
not spend time waiting for an I/O operation to be performed, thus increasing efficiency.
4. The I/O module is given direct access to memory via DMA. It can now move a block of data
to or from memory without involving the CPU, except at the beginning and end of the transfer.
5. The I/O module is enhanced to become a processor in its own right, with a specialized
instruction set tailored for I/O. The CPU directs the I/O processor to execute an I/O program in
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memory. The I/O processor fetches and executes these instructions without CPU intervention.
This allows the CPU to specify a sequence of I/O activities and to be interrupted only when the
entire sequence has been performed.
6. The I/O module has a local memory of its own and is a computer in its own right. With this
architecture, a large set of I/O devices can be controlled, with minimal CPU involvement. A
common use for such an architecture has been to control communication with interactive
terminals. The I/O processor takes care of most of the tasks involved in controlling the terminals.
With this evolutionary path, more and more of the I/O function is performed without
CPU involvement. The CPU is increasingly relieved of I/O-related tasks, improving
performance. With the last two steps (5–6), a major change occurs with the concept of an I/O
module capable of executing a program. For step 5, the I/O module is often referred to as an I/O
channel. For step 6, the term I/O processor is often used. However, both terms are on occasion
applied to both situations. In what follows, we will use the term I/O channel.

Characteristics of I/O Channels

The I/O channel represents an extension of the DMA concept. An I/O channel has the
ability to execute I/O instructions, which gives it complete control over I/O operations. In a
computer system with such devices, the CPU does not execute I/O instructions. Such instructions
are stored in main memory to be executed by a special-purpose processor in the I/O channel
itself. Thus, the CPU initiates an I/O transfer by instructing the I/O channel to execute a program
in memory. The program will specify the device or devices, the area or areas of memory for
storage, priority, and actions to be taken for certain error conditions. The I/O channel follows
these instructions and controls the data transfer.

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 Two types of I/O channels are common, as illustrated in the above Figure. A selector
channel controls multiple high-speed devices and, at any one time, is dedicated to the transfer of
data with one of those devices. Thus, the I/O channel selects one device and effects the data
transfer. Each device, or a small set of devices, is handled by a controller, or I/O module. Thus,
the I/O channel serves in place of the CPU in controlling these I/O controllers. A multiplexor
channel can handle I/O with multiple devices at the same time. For low-speed devices, a byte
multiplexor accepts or transmits characters as fast as possible to multiple devices. For high-speed
devices, a block multiplexor interleaves blocks of data from several devices.

ALU – Arithmetic and Logic Unit

The ALU is that part of the computer that actually performs arithmetic and logical
operations on data. All of the other elements of the computer system—control unit, registers,
memory, I/O—are there mainly to bring data into the ALU for it to process and then to take the
results back out. An ALU and all electronic components in the computer are based on the digital
logic devices that can store binary digits and perform simple Boolean logic operations.

Figure indicates how the ALU is stored in registers within the processor. The
interconnected with the processor. Data are control unit provides signals that control the
presented to the ALU in registers, and the operation of the ALU and the movement of
results of an operation are stored in registers. the data into and out of the ALU.
These registers are temporary storage
locations within the processor. The ALU
may also set flags as the result of an
operation. For example, an overflow flag is
set to 1 if the result of a computation
exceeds the length of the register into which
it is to be stored. The flag values are also

INTEGER REPRESENTATION
In the binary number system, numbers can be represented with just the digits zero and
one, the minus sign, and the period, or radix point. This is also called as fixed point
representation because the radix point (binary point) is fixed.
-1101.01012 = -13.312510
For purposes of computer storage and processing, we do not have the benefit of minus signs and
periods. Only binary digits (0 and 1) may be used to represent numbers. If we are limited to
nonnegative integers, the representation is straightforward.
An 8-bit word can represent the numbers from 0 to 255, including
00000000 = 0
00000001 = 1
00101001 = 41
10000000 = 128
11111111 = 255
In general, if an n-bit sequence of binary digits a n-1an-2 … a1a0 is interpreted as an unsigned
integer A, its value is

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Sign-Magnitude Representation
To represent negative as well as positive integers, we treate the most significant
(leftmost) bit in the word as a sign bit. If the sign bit is 0, the number is positive; if the sign bit is
1, the number is negative.
The simplest form of representation that employs a sign bit is the sign-magnitude representation.
In an n-bit word, the rightmost bits hold the magnitude of the integer.
+18 = 00010010
-18 = 10010010 (sign magnitude)
The general case can be expressed as follows:

There are several drawbacks to sign-magnitude representation. One is that addition and
subtraction require a consideration of both the signs of the numbers and their relative magnitudes
to carry out the required operation. Another drawback is that there are two representations of 0:
+ 0 = 00000000
- 0 = 10000000 (sign magnitude)
This is inconvenient because it is slightly more difficult to test for 0 (an operation performed
frequently on computers) than if there were a single representation. Because of these drawbacks,
sign-magnitude representation is rarely used in implementing the integer portion of the ALU.
Instead, the most commonly used is twos complement representation.

Twos Complement Representation

Twos complement representation uses the most significant bit as a sign bit, making it
easy to test whether an integer is positive or negative. It differs from the use of the sign-
magnitude representation in the way that the other bits are interpreted.
Characteristics of Twos complement Representation and Arithmetic

Table above highlights key characteristics of twos complement representation and arithmetic.
This method of representing is best understood by defining it in terms of a weighted sum of bits.

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The advantage of this is that the rules for arithmetic operations in twos complement notation may
work for all cases. Consider an n-bit integer, A, in twos complement representation. If A is
positive, then the sign bit an-1, is zero. The remaining bits represent the magnitude of the number
in the same fashion as for sign magnitude:

The number zero is identified as positive and therefore has a 0 sign bit and a magnitude of all
0s.We can see that the range of positive integers that may be represented is from 0 (all of the
magnitude bits are 0) through 2n-1 - 1 (all of the magnitude bits are 1). Any larger number would
require more bits. Now, for a negative number A, (A<0), the sign bit, a n-1, is one. The remaining
n -1 bits can take on any one of 2 n-1 values. Therefore, the range of negative integers that can be
represented is from -1 to -2n-1. We would like to assign the bit values to negative integers in such
a way that arithmetic can be handled in a straightforward fashion, similar to unsigned integer
arithmetic. In unsigned integer representation, to compute the value of an integer from the bit
representation, the weight of the most significant bit is +2n-1. For a representation with a sign bit,
the weight of the most significant bit is -2n-1. The below equation defines the twos complement
representation or both positive and negative numbers. For a n-1 = 0, the term -2n-1an-1 = 0 and the
equation defines a nonnegative integer. When a n-1 = 1, the term 2n-1 is subtracted from the
summation term, yielding a negative integer.

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Table compares the sign-magnitude and twos complement representations for 4-bit integers.
Twos complement facilitates the most important arithmetic operations, addition and subtraction.
For this reason, it is almost universally used as the processor representation for integers.
A useful illustration of the nature of twos complement representation is a value box, in
which the value on the far right in the box is 1 (2 0) and each succeeding position to the left is
double in value, until the leftmost position, which is negated. As you can see in Figure 9.2a, the
most negative twos complement number that can be represented is -2n-1; if any of the bits other
than the sign bit is one, it adds a positive amount to the number. Also, it is clear that a negative
number must have a 1 at its leftmost position and a positive number must have a 0 in that
position. Thus, the largest positive number is a 0 followed by all 1s, which equals 2n-1 – 1. Figure
b and c, illustrates the use of the value box to convert from twos complement to decimal and
from decimal to twos complement.

Converting between Different Bit Lengths

It is sometimes desirable to take an n-bit integer and store it in m bits, where m > n. In
sign-magnitude notation, this is easily accomplished.
+18 = 00010010 (sign magnitude, 8 bits)
+18 = 0000000000010010 (sign magnitude, 16 bits)
-18 = 10010010 (sign magnitude, 8 bits)
-18 = 1000000000010010 (sign magnitude, 16 bits)
This procedure will not work for twos complement negative integers. Using the same example,
+18 = 00010010 (twos complement, 8 bits)
+18 = 0000000000010010 (twos complement, 16 bits)
-18 = 1111111111101110 (twos complement, 16 bits)
-18 = 11101110 (twos complement, 8 bits)
-32,658 = 1000000001101110 (twos complement, 16 bits)
The next to last line is easily seen using the value box of Figure above. The last line can be
verified using a 16-bit value box or using the following equation

INTEGER ARITHMETIC
Negation : In sign-magnitude representation, the rule for forming the negation of an integer is
simple: invert the sign bit. In twos complement notation, the negation of an integer can be
formed with the following rules: (two complement of the integer)
1. Take the Boolean complement of each bit of the integer (including the sign bit).That is, set
each 1 to 0 and each 0 to 1.
2. Treating the result as an unsigned binary integer, add 1.
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Example
+18 = 00010010
bitwise complement = 11101101
+1
11101110 = -18
The negative of the negative of that number is itself:
-18 = 11101110
bitwise complement = 00010001
+1
00010010 = +18
There are two special cases to consider. First, consider A = 0. In that case, for an 8-bit
representation:
0 = 00000000
bitwise complement = 11111111
+1
100000000 = 0
There is carry out of the most significant bit position, which is ignored. The result is that the
negation of 0 is 0. The second special case is, if we take the negation of the bit pattern of 1
followed by zeros, we get back the same number. For example, for 8-bit words,
-128 = 10000000
bitwise complement = 01111111
+1
10000000 = -128
Some such anomaly is unavoidable. The number of different bit patterns in an n-bit word is
which is an even number. We wish to represent positive and negative integers and 0. If an equal
number of positive and negative integers are represented (sign magnitude), then there are two
representations for 0. If there is only one representation of 0 (twos complement), then there must
be an unequal number of negative and positive numbers represented. In the case of twos
complement, for an n-bit length, there is a representation for -2n-1 but not for +2n-1 instead +2n-1 - 1.

Addition and Subtraction

Addition in twos complement is illustrated in the Figure below.

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Note (e) and (f) are examples of overflow which can occur whether or not there is a carry.
Addition proceeds as if the two numbers were unsigned integers. The first four examples
illustrate successful operations. If the result of the operation is positive, we get a positive number
in twos complement form, which is the same as in unsigned-integer form. If the result of the
operation is negative, we get a negative number in twos complement form. Note that, in some
instances, there is a carry bit beyond the end of the word (indicated by shading), which is
ignored. On any addition, the result may be larger than can be held in the word size being used.
This condition is called overflow. When overflow occurs, the ALU must signal this fact so that
no attempt is made to use the result. To detect overflow, the overflow rule is observed:
If two numbers are added, and they are both positive or both negative, then overflow
occurs if and only if the result has the opposite sign.
SUBTRACTION RULE: To subtract one number (subtrahend) from another (minuend), take
the twos complement (negation) of the subtrahend and add it to the minuend.
Thus, subtraction is achieved using addition, as illustrated in the Figure below. The last two
examples demonstrate that the overflow rule still applies.

Figure below suggests the data paths and The Data Paths and Hardware Elements
hardware elements needed for addition and for Addition and Subtraction
subtraction. The central element is a binary
adder, which accepts two unsigned integers
for addition and produces a sum and an
overflow indication. For addition, the input
to the adder are from two registers, here,
from A and B registers. The result may be
stored in one of these registers or in a third.
The overflow indication is stored in a 1-bit
overflow flag (0–no overflow; 1–overflow).
For subtraction, the subtrahend (B register)
is passed through a twos complementer so
that its twos complement is presented to the
adder. Only the data paths are shom in the
figure. Control signals to indicate the use of
complementer is used, depending on the
operation addition or subtraction.

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Multiplication
Compared with addition and subtraction, multiplication is a complex operation, whether
performed in hardware or software.

UNSIGNED INTEGERS: The example position to the left relative to the

illustrates the manual multiplication of preceding partial product.
unsigned binary integers. Several important 4. The multiplication of two n-bit binary
observations can be made: integers results in a product of up to 2n
1.Multiplication involves the generation of bits in length (e.g., 11 x 11 = 1001).
partial products, one for each digit in the
multiplier.
2.The partial products are easily defined.
When the multiplier bit is 0, the partial
product is 0.When the multiplier is 1, the
partial product is the multiplicand.
3.The total product is produced by adding
the partial products. For this, each
successive partial product is shifted one

To make computerized multiplication more efficient, we must do the following :

1. We can perform a running addition on the partial products rather than waiting until the end. This eliminates
the need for storage of all the partial products; fewer registers are needed.
2. We can save some time on the generation of partial products. For each 1 on the multiplier, an add and a
shift operation are required; but for each 0, only a shift is required.

Figue shows a implementation employing these measures. The multiplier and multiplicand are loaded into two
registers (Q and M). A third register

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