Ministry of Higher Education and Scientific Research

University of Boumerdes
Institute of Electrical and Electronic Engineering

Digital Systems I with VHDL

EE221 Lab - L03

Report of Lab Work # 09

Group 10

Slimani Yanis - Sayoud Day Eddine

EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

I- Introduction:
In this final lab for Digital Systems I with VHDL, we'll apply our accumulated knowledge to
test and enhance our understanding of recently covered adder types.
These adders, while basic, are crucial VHDL code extensions. Mastering their construction is
valuable for tackling more complex codes in the future.
By the end of lab 9, we'll adeptly write VHDL code for various adder types, employing
Dataflow, Behavioural, and Structural designs. We'll also work with a specific IC housing an
Adder type for the first time.

II- Objectives:
The objective of this lab assignment is to explore fundamental concepts related to binary
addition circuits.

- BCD (Binary-Coded Decimal) adders using fixed-function ICs and VHDL implementation.
- In addition to implementing schematic-designed circuits with buses.

III – Solutions:

Problem #1: In this problem, we are asked to take and to implement the new IC that we recently
learned about. Which is the 7483A IC, we will implement it directly into the Digi-designer tool
given by our lab-instructor.

- Using this pin map and jumper wires, we the inputs

A1 A2 A3 A4 and B1 B2 B3 B4 and Cin to a set of 9
switches, and connect the output sum and carry to,
either a set of LEDs (straightforward solution) or to
a seven segment displays.

- For more clarity, the circuit will be modelized using

the software provided. A 7483A 4-bit adder IC and
BCD convertor and their respective pin maps. Along
with switches and breadboards, seven segments
display. As show in the figure below:
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

Color code used:

- Red wires for VCC, Black wires for Ground.
- Green wires for the input A (A1 A2 A3 A4) Labelled from left to right in the same order. The
last switch of the first board is assigned to the input carry.
- Blue wires for B (B1 B2 B3 B4), Orange for the output sum S (S1 S2 S3 S4). Then the light
blue wires are for the seven segment displays inputs abcdfg, the ‘p’ pin is the output carry.
Example:

- 1100 + 1000 = 010100 => Taking 4-bits the result is ‘4’ with a carry.

Problem #2: For this problem n°2, we are asked to draw the truth-table of a function that must
be deduced using the given circuit, before reproducing it in our software. After doing this, and
the steps given by the instructor, we will try to use a functionality named “Bus”.

-This is the circuit that must be reproduced, the picture is

taken directly from the lab-work n°9 (Figure 2):

In the end, we will perform the functional simulation of

the circuit before comparing it to the results that we
obtained from our truth-table.
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

The Truth Table:

A [3] A [2] A [1] A [0] F [3] F [2] F [1] F [0]

0 0 0 0 0 1 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 0 0 0

0 1 0 0 1 1 0 0

0 1 0 1 1 0 1 0

0 1 1 0 1 1 0 1

0 1 1 1 1 0 1 0

1 0 0 0 0 0 0 0

1 0 0 1 0 0 0 0

1 0 1 0 0 0 0 1

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 1 0

1 1 1 0 0 0 0 1

1 1 1 1 0 0 1 0

- We can turn on the Quartus II software on our computers. We will then create a new file
to draw the schematic design of Fig-2.2:
We go to: New File -> Block Diagram / Schematic File.
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

For this step, we simply have to double click on the white space to select and to insert the
wanted gates. We took 2 not-gates with 4 and-gates as it is shown in the circuit.
After inserting all the necessary gates, we will extract from each of them the inputs and outputs
that we will be using Buses.
We will simply extract wires from the input of the gates and from their outputs, naming each
one of these wires individually as it follows:

- A [0] & F [0] for the top of the circuit.

- A [3] & F [3] for the bottom of the circuit.

We can then place our input A [3..0] and our output F[3..0] => We select a single Input entry
for the circuit that will be named A[3..0]. And we single a single Output entry that will be
named F [3..0]
- We can notice that this wire will be thicker than the others as represented in the figure
below, these thick wires are the wanted Buses.
- The figure below represents the final form of our Schematic Design.

- We can perform its functional simulation. So, by creating a new Vector Waveform file, we
can insert all our inputs and outputs directly in the simulation, setting all the possible
combinations for A[3]…A[0]. And setting the Grid-size to 50 ns, while the End-time will
be set to 800ns.
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

After performing the functional simulation, we will get the result illustrated in the following
figure:

After looking into this last figure, we can see that the result matches perfectly with the result of
our Truth Table.

Problem #3: In this problem, we are asked to write the VHDL code of a simple 4-bit adder
using one of the new packages that we learned: STD_LOGIC_UNSIGNED or
STD_LOGIC_SIGNED.
- The figure below represents the VHDL code that will provide us with the desired result (The
4-bit adder)
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

- The code can be written simply using the direct assignments (Arithmetic assignment)
method with a single signal.
- After finishing the code, we have to perform the functional simulation of our program, to
do this, we will as always create a new Vector Waveform file, and perform the following
assignments:

- As we can see here, the addition is running perfectly, as the Carry-in is taken in consideration
when Cin = ‘1’. And we can also notice that the carry out appears to be ‘1’ whenever the result
of Sum is Out of range (S > 15)
DE2 board and perform the pin-assignment:
The pin-assignment will be as follow, such that the value of the sum and the carry out will be
displayed using the LEDs. Whenever the carry out is ‘1’, the LED that is at the most left will
bright up. While the 4 other LEDs will turn On or Off in function of the resulted Sum.
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

Problem #4: For this problem, we are asked to write using the Behavioral style of VHDL code
a BCD adder program (4-bit BCD adder). This program must be done in a way such that if one
of the inputs is not a BCD, a high impedance ‘Z’ must be assigned to the output.

The figure below represents some combinations of the final functional simulation of our
problem:
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

- As we can notice from this functional simulation, whenever one of our inputs (Either A or
B) are not in BCD (A > 9 or B > 9), then a high impedance is assigned to the output of the
function (Both of the Sum and the Carry out).
- For this problem, the pin-assignment will be the exact same as the one of the previous
problem, then downloaded in the DE2 and tested.

Problem #4: In this problem, we are asked to write once again the VHDL code for a BCD-
adder. However, this adder is provided with an Invalid-BCD detector that will automatically
add 6 to the summation of our inputs A and B if it detects:
- The presence of a Carry.
- That the summation exceeds the number 9 (Or (1001)2).
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

-In our case, since it is easier to use and to explain, we decided to write create our program
using the Block Diagram File method.
To do so, we must perform some Pre-Drawing manipulation, since we are going to perform
multiple operations on this function, it is important to know exactly which gates must be used.
-As we saw in the first problem of this lab-work n°9, there is a special IC that performs directly
the addition operation of two 4-bits inputs, which is the 7483A IC, and due to this, we don’t
have to perform any further simplification of the function A + B, since a single gate can perform
the operation.
- This function is the result that we needed to create the correct and the simplest Block
Diagram file for our total function.
- Now, we can start our Block Diagram following the necessary steps:
First, we will design the block Diagram file of the 4-bit Adder itself, using the new gate that
we’ve just used in the problem I.

- After completing the first part, we will insert in the circuit the Invalid-BCD-Detector using
the function that we deduced earlier.
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

- However, the Invalid-BCD-Detector doesn’t have a specific IC for the performed

operation, this is why we will have to draw the corresponding logic circuit.
FDetector = Cout + F(S[3], S[2], S[1], S[0]) = Cout + S[3] (S[1] + S[2])
- We can then finally connect the outputs as we did for the inputs in the first part, to get the
final result as:

- We can now perform the functional simulation of our system (function), to do this, we do
as we did in the previous problems by setting the Grid-size to 50ns, and the End-Time to
800ns.
- By following all the steps, here is the corresponding functional simulation for the program:
EE 221 Lab – Digital Systems with VHDL Institute of Electrical and Electronic Eng.

- For the Pin-assignment of this problem, we will use one similar to the problems n°3 and
n°4, since it considers the same inputs and outputs.

Conclusion:

- In the end of this lab-work n°9, which is also the final lab-work of our Digital Systems with
VHDL I course. We can use and understand the system of adders, using the multiple
methods that we learned during this semester, we are now able to create some adders with
specific conditions (As we were asked to do in the last problem).

- These adders being essential for multiple programs, learning how they work, and the logic
behind them was a necessary step before moving to the program of the next semester.