ABSTRACT

VLSI (Very Large Scale Integration) is a technology that involves packing millions of electronic components onto a
single microchip to create complex and powerful integrated circuits. Adders are digital circuits used in computer
architecture to perform addition operations. They add binary numbers and often come in several categories,
including half adders (addition of two binary digits), full adders (addition of three binary digits with carry), and
ripple carry adders (used for multi-bit addition). They play a crucial role in arithmetic and data processing within
computers. Adders are used in computer processors for arithmetic calculations, memory addressing, data
encryption, digital signal processing, and error checking in data transmission. In the original study, XOR, NOR, and
mux gates were employed to compute sum and carry signals, leading to significant time delay concerns. In our
innovative approach, we've streamlined the design by exclusively utilizing mux gates, resulting in a remarkable
reduction in time delay. This advancement promises improved efficiency and performance, setting a new standard
in digital circuitry.

INTRODUCTION
In the realm of electronics, Very Large Scale Integration (VLSI) technology stands as a testament to human
ingenuity, allowing the consolidation of an extensive array of electronic components onto a single semiconductor
chip. This paper delves into the pivotal role played by adder circuits in VLSI design, emphasizing their significance in
digital systems, where they perform essential arithmetic and logical operations.

Within the VLSI domain, a diverse spectrum of adder types has been developed to cater to specific performance
requirements and design constraints. This paper undertakes an exploration of these adder types, offering a
comparative analysis of their attributes, strengths, and weaknesses. Prominent among these adder types are the
classic Ripple Carry Adders (RCA), which employ a sequential carry-propagation mechanism, and the more
advanced Carry Look-Ahead Adders (CLA), designed to reduce carry-propagation delays through parallel
computation of carry signals. Additionally, Conditional Sum Adders (CSA) optimize area and speed characteristics,
while Parallel Prefix Adders (PPA) leverage efficient parallel-prefix computation techniques. The paper also
discusses the Wallace Tree Adder, celebrated for its high-speed operation.

This paper underscores the profound significance of VLSI technology and the indispensable role of adders within
this domain. By examining the strengths and weaknesses of various adder types, it contributes to the ongoing
refinement of VLSI design and its broad spectrum of applications in the electronics industry. The insights offered
here serve as a valuable resource for engineers and researchers seeking to enhance the efficiency and
performance of adders in digital systems. In an era marked by relentless technological advancements, VLSI
technology and its constituent adders remain at the forefront of innovation, shaping the future of electronics.

In the realm of digital circuit design, the consideration of delay is of paramount importance. Ignoring delay factors
can lead to circuit failures and timing discrepancies, which can have critical consequences for the functioning of
digital systems. To address this, various methods have been proposed for analyzing digital circuit designs and
accurately calculating latency. One such method, known as the Logical Effort (LE) method, introduced by Fathi et
al, has gained prominence for its ability to provide both speed and accuracy in analyzing digital circuits.

The LE method replaces vague definitions such as fan-out and drive with precise mathematical patterns and
combines them with the resistor-capacitor (RC) linear delay model. This approach enhances the understanding of
delay within circuits and can be applied to determine transistor sizes and optimization levels in circuit designs. LE is
closely related to the number of gate inputs, meaning that larger and more complex logical gates tend to exhibit
longer delays. Consequently, the selection of the appropriate logical structure during the design process becomes
crucial.

The LE method finds application in accurately modeling and computing circuit delays through mathematical
equations. It distinguishes between two types of delays within circuits: effort delay (f) and parasitic delay (p), which
are combined to determine the overall delay (d), expressed as d = f + p.
Parasitic Delay (p): This represents the gate delay when the gate is not part of the circuit, essentially a no-load
condition. Parasitic delay is primarily determined by parasitic capacitors and has a constant value for each gate
type. Effort Delay (f): Effort delay encompasses two components: logical effort (g) and electrical effort (h). Logical
effort quantifies a gate's delay and resistance when it is actively operating within a circuit, depending on its driving
characteristics. Electrical effort, on the other hand, is the ratio of the output capacitor to the input capacitor, often
referred to as fan-out.

These delay components are essential for understanding the behavior of digital circuits, and the LE method
provides a systematic framework for their calculation. By considering different gate types and their respective
delays, designers can make informed decisions to optimize circuit performance.

The LE method's utility extends to the computation and modeling of circuit delays, allowing for precise and
efficient analysis. By leveraging mathematical equations, it offers a comprehensive understanding of delay
mechanisms within digital circuits, contributing to the refinement of circuit designs and their subsequent
performance enhancements.

RELATED WORKS
Introducing an energy-efficient floating-point adder, finely tuned for field programmable gate arrays (FPGAs). This
adder harnesses a two-path floating-point addition algorithm, seamlessly accommodating single-precision and
double-precision calculations. Its fully pipelined architecture achieves a double-precision addition or two parallel
single-precision additions in a mere six clock cycles, ensuring exceptional speed and throughout. The [1]
architecture's adaptability shines as it seamlessly integrates into various FPGA devices, including Altera Stratix-III,
Xilinx Virtex-5, Altera Arria-10, and Xilinx Virtex-7. Derived from a double-precision adder foundation, key
components are adeptly partitioned to support dual single-precision operations. Notably, it surpasses FPGA
vendors' double-precision IP core adder in clock frequency and exhibits superior energy efficiency compared to
single and double-precision IP core adders. Its adaptability extends across FPGA devices and diverse hardware
platforms, solidifying its versatility and significance.

Recent years have witnessed the growing importance of approximate circuit design, particularly for applications
that can tolerate errors. In this research, the authors introduce a novel metric for evaluating stand-alone
approximate adders. This [2] metric ranks these adders based on the power savings they yield, while maintaining
specific mean error distance or mean square error (MSE) criteria. The study extends the applicability of this metric
from single adders to more intricate structures like adder trees and registers. Additionally, it reveals that certain
approximations within these adders can enhance the power efficiency of multipliers when integrated into
applications alongside accurate multipliers. Furthermore, the research explores essential metrics beyond power
savings, including noise floor and mean error in filtering applications, as well as compression levels achieved in
image compression applications for given peak signal-to-noise ratio (PSNR) requirements. It also highlights the
trade-offs between noise and error for the same overall MSE, enabling adder classification based on their impact.
The study delves into the implications of employing approximate discrete cosine transform blocks to meet reduced
PSNR requirements, shedding light on the ensuing compression levels and associated trade-offs.

In pursuit of faster and more reliable adders, this [3] study presents an innovative approach to enhance carry-
select adders. The method involves encoding sum bits using two-rail codes and validating them using self-checking
checkers. Notably, all multiplexers within the adder are meticulously designed to be entirely self-checking. To
demonstrate the scheme's effectiveness, a 2-bit carry-select adder is implemented, showcasing real-time detection
capabilities for single stuck-at faults. While double fault detection is not guaranteed, this modular design permits
the construction of larger adders by cascading these 2-bit units.The approach is put into practice with adders
ranging from 4 to 128 bits, employing a 0.5-micrometer CMOS technology. The implementation incurs a transistor
overhead ranging from 19.51% to 20.94% and an area overhead ranging from 16.07% to 20.67% compared to
conventional adders without built-in self-checking mechanisms.Recent advancements in approximate adder design
have seen the emergence of Equal Segment Adders (ESAs), which segment N-bit adders into smaller, independent
sub-adders. In this [4] research, the authors introduce analytical models for estimating Pass Rate (PR), delay,
power, and area of ESAs, with a particular focus on PR, representing the probability of correct output.The analytical
models highlight the potential for improving the quality-effort curves of existing ESAs. To enhance these curves,
the authors propose modifications to ESAs, aiming to boost accuracy without introducing additional delays, power
consumption, or area overheads.Analytical and simulation results consistently demonstrate that these modified
ESAs offer superior accuracy, enhanced quality-effort curves, and more optimal trade-offs between Delay, Power,
Area, and Accuracy. Moreover, real-world applications, including image processing, underscore the practical
effectiveness of these modifications, producing more precise images when compared to original ESAs.

In the realm of Very-Large-Scale Integration systems and digital signal processing, addition is a cornerstone
mathematical operation profoundly influencing computational speed. Various digital adders employing different
methodologies exist. This [5] study introduces an innovative adder distinguished by its streamlined computational
path, resulting in heightened speed and reduced power consumption. The novel aspect of this research centers on
the creation of a structured, high-speed adder with scalable bit capacity. This design optimizes both calculation
speed and power efficiency. Each level of the adder employs multiplexers and OR gates, with well-defined
formulas.The performance of the proposed adder is meticulously examined and compared to established
counterparts, such as the ripple carry adder, carry skip adder, carry select adder, carry look ahead adder, and prefix
Kogge-Stone adder, across varying bit configurations. The outcomes underscore the proposed adder's superiority,
particularly in metrics encompassing power consumption, power-delay product, and delay-area product.

Within Very Large Scale Integration (VLSI) designs, achieving optimal delay performance is paramount. This [6]
paper investigates four distinct types of Parallel Prefix Adders (PPAs) - Kogge Stone Adder (KSA), Spanning Tree
Adder (STA), Brent Kung Adder (BKA), and Sparse Kogge Stone Adder (SKA). Additionally, it examines Ripple Carry
Adder (RCA), Carry Lookahead Adder (CLA), and Carry Skip Adder (CSA) for comparative analysis. These adders are
meticulously implemented in Verilog Hardware Description Language (HDL) using the Xilinx Integrated Software
Environment (ISE) 13.2 Design Suite. The designs are instantiated within Xilinx Virtex 5 Field Programmable Gate
Arrays (FPGAs), and their performance metrics, including delay, power consumption, and area characteristics, are
thoroughly investigated and compared. Measurement and analysis are conducted using an Agilent 1692A logic
analyzer, aiming to offer valuable insights into the relative efficiency and suitability of these adder architectures for
VLSI applications.

Our proposed architecture is designed for efficient computation of the double-precision floating-point multiply-
add-fused (MAP) operation, denoted as A + (B × C). It is centered on optimizing both the addition and rounding
processes through the use of a dual adder. A key feature is the prioritization of the normalization step before
addition, ensuring no overlap between the leading-zero-anticipator (LZA) and the adder. To prevent delays, we've
ingeniously modified the LZA design to promptly generate leading bits, facilitating early normalization initiation.
Furthermore, we've strategically anticipated certain aspects of the addition process. Through thorough evaluation,
factoring in the impact of lengthy connections, our estimates indicate a substantial reduction in delay—between
15 percent and 20 percent—compared to prior implementations. This [7] architecture promises enhanced
efficiency in double-precision floating-point MAP computations, with potential benefits spanning various
application domains.

The advent of the Internet of Things (IoT) has ushered in an era where virtually every device can seamlessly
connect via a stable internet connection. This [8] interconnectedness, while facilitating data exchange and
communication between devices, has also led to increased power consumption. Consequently, in the development
or enhancement of IoT systems, paramount consideration is given to low-power circuit design.Among the
challenges in low-power circuit design, minimizing leakage power is of utmost importance. Battery-operated IoT
devices, when in standby mode for extended periods, can rapidly deplete their energy reserves. Addressing this
issue, reducing delay in a ripple carry adder is a crucial objective, and Carry-Skip Adder (CSA) emerges as an
efficient solution compared to alternatives like carry-look ahead adders.CSA, a member of bypass adders,
prioritizes enhancing IoT device worst-case delay while considering area and power consumption. Integrating CSA
into the proposed IoT processor significantly bolsters system performance in terms of average power dissipation,
leakage power, power delay product, and propagation delay. This approach promises to enhance the efficiency and
longevity of IoT devices in a power-conscious landscape.

The realm of advanced computing explores innovative pathways with memristor-based digital logic circuits,
offering a compelling departure from traditional IC technology. Within this [9] landscape, memristor ratioed logic
(MRL) seamlessly integrates with conventional CMOS technology. This study introduces two distinct carry-
lookahead adders (CLA) leveraging a hybrid CMOS-memristor structure.One of these CLAs is rooted in MRL logic,
while the other represents an enhanced variant implementing MRL universal gates (MRLUG). Rigorous theoretical
analyses and simulation-based verification highlight the prowess of these CLAs. Notably, they demonstrate
superior resource efficiency, utilizing fewer memristors and CMOS components compared to IMP-based or CMOS-
based CLAs. This translates to more compact circuitry and reduced power consumption, promising advancements
in compact, energy-efficient design.

Achieving a delicate balance between high performance and low power consumption is a central challenge in VLSI
design. This [10] holds especially true for applications operating under low and ultra-low power constraints, where
managing power usage and minimizing logic delays is pivotal. In today's VLSI landscape, the cornerstone of
superior performance often lies in the design of crucial computational units like the Arithmetic Logic Unit (ALU),
where adders and multipliers play essential roles. To meet the stringent criteria of speed and power dissipation in
low-power, high-performance applications, meticulous engineering of these critical components is imperative. This
paper introduces a novel approach employing the Modified Gate Diffusion Technique to construct a Carry Look-
Ahead Adder (CLA). Notably, the CLA excels in curtailing propagation delays compared to alternative adder models.
The proposed CLA is carefully implemented on a 90 nm technology platform within the Cadence environment. The
primary objective of this research is to leverage Modified Gate Diffusion Input (MGDI) Technology to conceptualize,
develop, and implement an advanced CLA, poised to elevate the performance and power efficiency of VLSI
systems.

In the realm of portable electronics, rapid advancements necessitate designers to enhance existing designs for
optimal performance. Addition, a fundamental arithmetic operation, finds application in digital signal processors,
ALUs, math processors, and various scientific contexts. This [11] paper introduces a novel approach to 1-bit Carry
Select Adder (CSA) by employing gates with different NMOS and PMOS values. Extensive simulations are
conducted at 45nm, 90nm, and 180nm technologies using TANNER tools, evaluating key performance parameters
such as area, power consumption, and delay. The study investigates data dependency and identifies redundant
logic operations within CSAs, proposing an innovative logic formulation that eliminates such redundancies.
Notably, this CSA design exhibits significantly reduced area and delay compared to recent binary-to-excess-1
converter-based CSAs. These findings contribute to the ongoing enhancement of portable electronics.

Introducing a ground-breaking approach to digital addition, this study holds great promise for Very‐large‐scale
integration systems and digital signal processing. Its central objective revolves around enhancing computational
speed while simultaneously curbing power consumption through the development of a novel adder. This [12]
inventive adder functions with notable efficiency by employing fewer levels, resulting in remarkable computational
speed and reduced energy usage. A distinctive feature of this method is its structured design, which offers
scalability for accommodating higher-bit calculations while preserving top-tier performance. Each circuit level is
meticulously crafted using multiplexers and OR gates, complemented by comprehensive formulae for thorough
understanding.To gauge its performance, a rigorous evaluation is undertaken through mathematical analysis and
simulation. This assessment places the proposed adder in direct competition with established counterparts like the
ripple carry adder, carry skip adder, carry select adder, carry look ahead adder, and prefix kogge‐stone across
various bit configurations (8, 16, 32, and 64 bits).The results unmistakably showcase the superiority of the
proposed adder, with remarkable achievements in power consumption, power delay product, and delay area
product metrics compared to existing alternatives. This advancement holds significant promise for digital
computation in VLSI systems and DSP applications.
Introducing a novel approach to approximate carry select adders (CSLA) with reverse carry propagation (RCSLA)
through the implementation of a unique reverse carry propagate full adder (RCPFA) structure. Departing from
conventional designs, the RCPFA enables the reverse propagation of the carry signal, starting from the most
significant bit (MSB) and moving towards the least significant bit (LSB). This [13] prioritizes the carry input over the
output carry, resulting in a distinctive approach.The innovation encompasses three distinct RCPFA
implementations, each tailored to specific design parameters. Beyond CSLA, this approach extends to ripple carry
adders (RCA) and results in the creation of diverse approximate adder designs. All design and simulation activities
are executed using CADENCE Software, capitalizing on 45 nm CMOS technology. Furthermore, comprehensive
comparative analysis of design parameters is conducted among the three CSLA implementations with RCPFA,
providing valuable insights into their performance in relation to existing CSLA adders. This pioneering approach
holds the promise of enhancing the adaptability and efficiency of adder circuits across a wide spectrum of
applications.

Innovations in prefix adder carry tree design are at the core of this research. The first innovation centers around
the use of high-valency prefix cells, strategically employed to significantly reduce logical depth, thereby enhancing
the overall efficiency of carry tree designs. Complementing this, the paper introduces the concept of end-around
carry adders, meticulously engineered to alleviate the challenges posed by fan-out loading, effectively addressing
limitations inherent in conventional carry select and flagged prefix adders.In addition to these innovations, the
research provides an algorithm for the generation of parallel prefix carry trees. This [14] algorithm is flexible,
allowing for customization of parameters like carry tree width, prefix cell valency, and the spacing of repeated
carry trees. Such parameterization proves to be a valuable asset in the realm of VLSI synthesis.Furthermore, the
study meticulously explores the area-delay design space, utilizing a 0.25 μm CMOS technology and examining a
spectrum of adder widths. This comprehensive analysis offers valuable insights, highlighting the superior
performance and efficiency of these pioneering prefix adder carry tree designs.

In the realm of complex circuit design, efficient formal verification stands as a critical imperative. Existing
verification techniques, though abundant, often fall short in providing a clear framework for assessing the time
complexity of the verification process. To address this challenge, Polynomial Formal Verification (PFV) has emerged
as a promising solution. In this paper, we present our innovative approach to PFV, specifically tailored for
arithmetic circuits.Our method leverages a divide and conquer strategy, systematically decomposing the circuit
into manageable subgraphs. These subgraphs are subjected to verification using Answer Set Programming (ASP), a
model-based reasoning technique. Notably, for circuits characterized by limited cutwidth, our approach enables
efficient verification. To demonstrate its practical applicability, we employ adder circuits as exemplars.
Furthermore, we conduct a comprehensive analysis of the approach's time complexity, substantiating its efficiency
by proving that the verification of various adder architectures can be achieved in linear time. These [15] theoretical
insights are further validated through extensive experiments involving diverse adder designs, including those with
inputs of up to 10,000 bits.

This [16] paper introduces an innovative design of a high-speed, low-power carry-skip adder, making it highly
suitable for advanced signal processing core development when compared to traditional carry-skip adder (CKA)
designs. The research delves into the critical path analysis of a ripple carry adder (RCA)-based carry-skip adder,
aiming to identify opportunities for reducing delays. Building on these findings, the study proposes new logic
formulations and corresponding RCA modifications for the CKA.In a departure from the conventional AND-OR logic,
this novel design incorporates AND OR Invert (AOI) and OR AND Invert (OAI) composite gates for both the full
adder and skip logic. The proposed architectures are implemented in Verilog HDL, synthesized using Xilinx and
CMOS library tools.Synthesis outcomes demonstrate that the proposed 32-bit carry-skip adder reduces delay by
40.91% and area by 7.96%. In comparison, the modified RCA design exhibits superior efficiency in terms of area,
delay, and energy consumption, surpassing traditional RCAs.

In this [17] investigation, diverse 32-bit carry-skip adders are meticulously examined, including the Fixed Stage
Size-Conventional carry-skip adder (FSS-Conv CSKA), Variable Stage Size-Conventional carry-skip adder (VSS-Conv
CSKA), Fixed Stage Size-Concatenation and Incrementation carry-skip adder (FSS-CI CSKA), and Variable Stage Size-
Concatenation and Incrementation carry-skip adder (VSS-CI CSKA). Employing 45 nm static CMOS technology and
varying supply voltages (0.7v, 0.9v, 1.1v), a comprehensive assessment is conducted, encompassing power
efficiency, energy consumption, critical path delay, power-delay product, and energy-delay product
metrics.Through Tanner EDA simulations, noteworthy performance differentials emerge, particularly in the
Concatenation and Incrementation carry-skip adder designs. These variations, featuring fixed and variable stage
sizes, exhibit remarkable improvements, boasting a substantial 51% and 49% reduction in critical path delay and
energy utilization when compared with the Fixed Stage Size-Conventional carry-skip adder and Variable Stage Size-
Conventional carry-skip adder counterparts.

The widely-used logical effort method is effective for estimating and optimizing single paths in circuit design.
However, it requires gate library calibration and may not be optimal for tight timing constraints in real
combinatorial paths. This is because it doesn't account for I/O coupling and input ramp effects, which differentiate
transition time from propagation delay. This [18] paper presents an extended logical effort model that incorporates
these effects by analyzing the supply current in simple gates during switching. Validation is performed on 130-nm
STMicroelectronics technology. The model offers a compact representation of CMOS library timing performance
and discusses the choice of sampling points for look-up tables in design optimization.

A novel method for the calculation of poles in electrical systems is introduced, offering a streamlined and efficient
approach to derive characteristic functions without the need for intricate computations. The methodology involves
the systematic decomposition of circuits into three fundamental networks, as elucidated in the text, leading to the
rapid determination of the characteristic equation. This [19] novel pole calculation method stands out due to its
precision and broad applicability. Poles can be accurately and straightforwardly calculated without necessitating
additional assumptions, making it suitable for a wide range of electrical systems, including those comprising
resistors, capacitors, inductors, and even dependent sources.The paper provides practical examples that highlight
the method's efficiency and effectiveness in real-world scenarios. In summary, this approach simplifies pole
calculations in electrical systems, offering enhanced accuracy and generality, making it a valuable tool for
engineers and researchers engaged in electrical circuit analysis.

In pursuit of cost-effective and efficient Complementary Metal Oxide Semiconductor (CMOS) logic circuit design,
automation plays a pivotal role by reducing labor and manufacturing time. Traditional methodologies rely on
manual testing, often guided by the Logical Effort (LE) technique. Leveraging prior research that demonstrated the
viability of Particle Swarm Optimization (PSO) in tandem with LE for optimizing CMOS gate widths, this [20] paper
introduces an advanced PSO variant known as Mutative Particle Swarm Optimization (MPSO).The core objective of
MPSO is to streamline the sizing process within CMOS circuit design, with a specific focus on an 8-stage full adder
circuit. The optimization parameters revolve around gate widths within the circuit, aimed at achieving a predefined
target delay while adhering to LE-informed fitness criteria. Extensive experimentation involves the fine-tuning of
parameters, such as swarm size and iterations, alongside different initialization conditions, providing a
comprehensive assessment of MPSO's performance in optimizing the 8-stage full adder circuit.Results conclusively
demonstrate that the MPSO algorithm emerges as a potent and efficient solution for addressing circuit design
complexities. It exhibits high convergence rates and holds significant promise for broader applications in optimizing
CMOS logic circuit designs.

In the domain of application-specific integrated circuits (ASICs), the 1-bit full adder circuit stands as a critical
component. This [21] paper unveils an inventive and energy-efficient 1-bit full adder design, leveraging a
multiplexer-based architecture referred to as the 12-transistor MBA-12T adder. Notably, this circuit exhibits
several commendable attributes, including a reduction in transition activity, an intrinsic charge recycling capability,
and a distinctive feature of lacking direct connections to power-supply nodes. This unique characteristic translates
into a substantial reduction in short-current power consumption.Through exhaustive HSPICE simulations, the
effectiveness of this novel adder becomes evident. It achieves remarkable power savings, surpassing conventional
28-transistor CMOS adders by more than 26%. Furthermore, it consumes 23% less power than alternative 10-
transistor adders such as SERF and 10T while operating at an impressive 64% higher speed. This innovation not
only promises substantial enhancements in power efficiency but also delivers superior performance, positioning it
as a compelling choice for future ASIC designs.
In this [22] study, we explore the design of an innovative and high-speed 4-2 compressor. The objective is to
bolster its speed performance, achieved through strategic modifications to the conventional 4-2 compressor's
truth table. These alterations effectively reduce the gate-level delay to a minimal configuration of just 2 XOR logic
gates and 1 transistor, applicable across all parameters. Notably, the presence of similar paths eliminates the need
for additional buffers to equalize delays in low-latency routes. Consequently, this design approach not only reduces
power dissipation but also ensures the absence of glitches in the output waveforms. Extensive simulations using
HSPICE and TSMC 0.35µm CMOS technology confirm a delay of 340ps, highlighting the potential of this innovation
to enhance digital circuit efficiency.

This [23] paper delves into a comprehensive performance analysis of 64-bit Carry Lookahead Adders (CLA)
employing both conventional and hierarchical design approaches. The study evaluates the efficacy of Conventional
Carry Lookahead Adders (CLA) and Hierarchical Carry Lookahead Adders (HCLA) while considering various
parameters. Our investigation focuses on FPGA Virtex 7 family deployment, with a meticulous examination of area,
delay, and area-delay product for all design configurations.The experimental findings showcase notable
achievements, particularly in reducing CLA delay and area through the utilization of radix-2, which outperforms the
conventional radix-4 CLA. Interestingly, the results underscore that the CLA employing the conventional structure
exhibits superior performance compared to the hierarchical counterpart.

In the realm of digital circuit design, the XOR gate stands as a foundational element, particularly crucial for
detecting the sum output in binary adders. This [24] paper introduces a novel approach to enhancing a 2-input XOR
gate, optimizing its performance. Traditionally, a Half Adder (HA) circuit comprises one XOR and one AND gate.
However, by integrating this modified XOR gate into the HA design, we streamline it to necessitate only a single
XOR gate, with the AND gate's functionality ingeniously embedded within the XOR gate itself. Our research reveals
that this modified XOR gate significantly outperforms conventional designs, particularly when integrated into adder
circuits housing multiple XOR gates. We applied this innovation to various scenarios, including conventional square
root CSLA, Binary to Excess-1 Converter (BEC) based square root CSLA, and Optimized Logic Based (OLB) square
root CSLA designs. The outcomes demonstrate a noteworthy reduction in the Area-Delay-Product (ADP), with
reductions of 12.45% in conventional CSLA, 21.45% in BEC-based CSLA, and 17.81% in OLB CSLA. These advanced
adders hold significant promise for applications, especially within the Arithmetic Logic Unit (ALU) of
microprocessors, where they can substantially enhance binary addition efficiency. This innovation marks a
substantial leap forward in digital circuit design.

In the intricate landscape of digital computing systems, adders emerge as fundamental building blocks, wielding a
profound influence over system performance. These adders encompass a spectrum of types, each governed by
unique algorithms with distinct computational delays, thus underscoring the multifaceted nature of adder circuit
design. While optimizing computational speed remains paramount, the imperative to minimize power
consumption remains a core objective in this arena. This [25] paper presents a pioneering approach that dissects
the proposed adder architecture into discrete sub-blocks, each meticulously engineered using multiplexers and
NOR gates to compute output carries or input carries for subsequent sub-blocks. This innovative methodology
effectively slashes the critical path delay, ushering in a substantial enhancement in the adder's operational speed.
A comprehensive analysis unfolds, involving rigorous simulation and synthesis for adder configurations spanning 8,
16, 32, and 64 bits. The results are juxtaposed against a backdrop of contemporary high-speed adders,
unequivocally positioning the proposed 16- and 32-bit adders as standouts. They not only exhibit the lowest
computation delay but also boast the most favorable power delay product, setting new benchmarks for efficiency
and performance in digital computing systems.

EXISTING
2.1 Logical effort (LE) theory

The delay is a crucial factor in digital circuit design. Neglecting the delay results in the circuits' failures and timing
mismatches. Therewith, the LE method , proposed, presents a fast and accurate analysis of digital circuit design.
Fathi et al.’s method
is another method for analysing digital circuits for latency calculation. The previous vague definitions such as fan‐out
 and drive are replaced with specific mathematical patterns and
combined with the resistor–capacitor (RC) linear delay model. LE can be used to determine the transistor sizes and
the number of optimisation levels in circuits. LE, in most logical gates, directly relates to the number of gate
inputs, that is, larger and more complicated logical gates have larger delays Type equation here .. During the design
procedure, such characteristics make the selection of proper logical structure more important. LE is applied to
calculate the delay of the proposed adder and other adders through mathematical equations set according to logical
gates structures.
One application of the LE method is the computation and modelling of circuits delay. The LE method calculates
the delay of circuits accurately and precisely through mathematical equations.
There are two types of delay in circuits, effort delay ( f ) and parasitic delay (p), expressed by d = f + p.
p delay: the gate delay when the considered gate is not in the circuit, stated as a no‐load condition. This delay
is deter- mined by the parasitic capacitors, and it has a constant value
for each gate as reported in Table 1.
f delay: the Effort delay itself has two parts, logical effort
(g) and electrical effort (h), expressed by f = gh.
Logical effort: defined as the delay and resistance value
of a gate against the electrical current, when the gate is ON and working in a circuit. It depends on the characteristics
of the gate when driving the load. The value of g for NOT gate is considered 1, and for other gates is obtained by
comparing with NOT gate. Table 2 shows the different values of LE.

Electrical Effort: is the ratio of the output capacitor to the input capacitor, also known as fan‐out.

C out
h= (5)
C¿

TABLE 1 The parasitic delay values for some gates TABLE 2 The value of logical effort for some gates

GAT NUMBER OF INPUTS G NUMBER OF INPUTS

E TYPE ATE TYPE 1 2 3 4 n
1 2 3 4 n
Inverter 1 Inverter 1
NAND 2 3 4 n NAND 4/3 5/3 6/3 (n+2)/3
NOR 2 3 4 n NOR 5/3 7/3 9/3 (2n+1)/3
Tristate/MUX 2 4 6 8 2n Tristate/MUX 2 2 2 2 2
XOR,XNOR 4 6 8 XOR,XNOR 4,4 6,12,6 8,16,16,8

Electrical circuits are composed of different gates, which carry electrical currents from input to output in a path. A
path is made up of some gates with numerous branches. To compute the delay of a path, the characteristics of the
gates existing in that path are used and the effort delay equation is rewritten as follows:

F=GBH ( 6 )
The B factor is added due to the branches in the circuit, which is defined as follows:

C on path +C C total
b= off path
= ( 7)
C on path Cuseful
 b is the branch size in a level of the path. Con‐path and Coffpath are, respectively, the capacitors existing in the
considered path and the capacitors existing in branches out of the path. The value of B is related to all branches of
the circuit, which is obtained from multiplying each branch b.

B=πbi ( 8 )

B is calculated with the same method as Ref. [24], where instead of capacitors the value of g is used, as can be
observed the examples in this paper.
LE value: is related to a path (G) and obtained by multiplying g values of each gate in the path.

G=πgi ( 9 )

Electrical effort value: is related to a path (H ) and obtained as the ratio of output capacitor to the input
capacitor of the path.

C out ( path )
H= (10)
C ¿ ( path )

The output and input capacitors are considered as unit capacitance.

The parasitic delay of a path (P ) is the summation of the pvalues of each gate in that path.

P=∑ pi ( 11)

To calculate the minimum delay of a path, Equation (12) is applied.

1/ N
D=N (F) + P(12)

2.1 Adder theory

An adder circuit is proposed using a multiplexer ,capable of computing the carry bit with a smaller delay. The full
adder in Ref. [25] is shown in Figure 1,which computes the carry bit and summation result using XNOR gates and a
multiplexer.The XNOR gate used in this paper was derived from Ref. [26],which uses the pass ‐transistor level(PTL)
and is shown in Figure2. As can be observed in Figure1,the control input of the multiplexer is connected to A
XNOR B,and the data inputs of the multiplexer come from the circuit inputs.This circuit shows that the carry bit can
be computed by a MUX.By repeating this circuit,a 3‐bit RCA will be as follow.

THE PROPOSED FAST ADDER

According to Figure 3, three serial multiplexers are used to compute the carry bit. If the circuit is repeated, for
example,for 7‐bit adders, seven serial multiplexers are needed. The goal is to compute the carry bits by these
multiplexers with a smaller delay. To this end, MUXs should not be connected serially, and a scheme should be
found to connect them in parallel. First, it should be investigated how an adder circuit works. According to the
circuit in Figure 3, Equation (13) is assumed as follows:
 Xi = Ai XNOR Bi (13)

FIGURE 1 Transistor level of the XNOR, XOR gate used

1-bit RIPPLE CARRY ADDER USING MUX AND XNOR GATES:

In this adder, two XNOR gates and a multiplexer is required to generate sum and carry. Sum is
generated just like full adder except two XNOR gates are used instead of XOR gates. And multiplexer comes into
play for generating Carry where XNOR of A and B is used as select lines and the input line are A and Cin.

FIGURE 2 Gate level implementation of the full adder

In the 3‐bit adder of Figure 3, for computing the output carry bit, the following cases reported in Table 3 hold. In Figure 3, the
three multiplexers, connected serially, work with the cases of Table 3. Now, these multiplexers are connected in parallel so that the
cases of Table 3 still hold. The circuit in Figure 4 is designed to this end, which will be explained further. Figure 4 works with the
same cases as Table 3, but the logic length needed to compute the output carry bit, reduce*d from three multiplexers to two
multiplexers. Therefore, using the proposed method, one MUX is saved, leading to a smaller delay in computations. The
circuit in Figure 4 is extended to generate the carry bit of adders with more bits. Figure 5 demonstrates the circuit of the
proposed 8‐bit adder.
 FIGURE 3 3‐bit RCA adder FIGURE 4 The proposed scheme for computing the carry
bit

8-bit RIPPLE CARRY ADDER USING MUX AND XNOR GATES:

This 8-bit adder, meticulously crafted with multiplexers and XNOR gates, exemplifies a remarkable feat in digital
arithmetic circuitry. Its distinctive configuration empowers it to generate both odd and even carries with precision.
Within this circuit, the process of binary addition is intricately divided into multiple stages, with each stage
featuring a multiplexer that utilizes XNOR gates as select lines. The outcome of each bit's addition is achieved
through a pair of XNOR gates.

The brilliance of this design revolves around the innate capability of the XNOR gate to discern between two distinct
inputs. This output, which reflects the parity of the input bits, serves as the select line for the multiplexer that
generates odd carries. When the XNOR gate detects differing inputs, it designates that bit as contributing to an odd
carry, and this information is utilized to select the appropriate input for the multiplexer.

For generating even carries, 2x1 multiplexers are ingeniously employed. These multiplexers rely on the information
from the XNOR gates to discern which bits should be added together to produce even carries.

Simultaneously, XNOR gates are harnessed to concurrently generate the sum for each bit, making the entire
process efficient and parallel. The result is a highly specialized and finely-tuned 8-bit adder that optimizes the
computation of both odd and even carries.

This innovative approach not only significantly enhances computational speed but also serves as a testament to
the ingenuity of digital logic design when addressing specific arithmetic challenges. In summary, the 8-bit adder
constructed using mux and XNOR gates represents a breakthrough in digital circuitry, showcasing its capacity to
handle distinct carry types while exemplifying the artistry of tailored logic design.
FIGURE 5 The proposed 8‐bit adder.
According to Figure 5, the maximum logic length to generate C7 is three multiplexers and one XNOR gate, and
the maximum logic length for an 8‐bit adder is four multiplexers and two XNOR gates. While, for an 8‐bit RCA,
the maximum logic length is seven multiplexers and two XNOR gates.

Therefore, in the logic length of the proposed 8‐bit adder, three multiplexers have been saved, which
accelerates the computations.

According to Figure 5, firstly the odd carry bits (C1, C3, C5, C7) are calculated in a parallel way and the even
carry bits are calculated after passing from one multiplexer 2*1 like Figure 5.

The amount of Si is calculated with the XNOR. As a result, the proposed diagram adder can be designed like
Figure 6.In Figure 6, the first block calculates the amount of Xi which is used in the block of odd carry bits and
in the last block. The second block is the innovator of this design which produces odd carry bits and for it,
there is a circuit that includes a multiplexer and OR which calculate the number of the carry bits in a parallel
way. We can use Equation (14) for calculating odd carry bits.

FIGURE 6 The proposed adder diagrams

C i=X i A i + X i X i−1 A i−1+ …+ X i X i−1 … . X 2 X 1 A1 + X i X i −1 … X 2 X 1 C¿ (14)

In Equation (14),the amount of odd carry bits is calculated by using Ai, Xi, and Cin. The proposed
approach can be easily expanded to design adders with more bits having shorter logic lengths than
conventional adders.Figure7 shows the proposed16‐bitadder. The maximum logic length for the
circuit of Figure7 is two XNOR gates and five multiplexers. Additionally, for 16‐bitRCA, the logic
length is two XNOR gates and 15 multiplexers , so 10 multiplexers have been saved using the
proposed method. The proposed 32‐bitadder is designed as Figure8 , which includes the logic length
of two XNOR gates and six multiplexers.While the 32‐bit RCA has two XNOR gates and 31
multiplexers. This way, the computational delay of addition reduces considerably using the proposed
method. This is further supported through mathematical equations, simulations and comparisons
with other adders.
16-bit RIPPLE CARRY ADDER USING MUX AND XNOR GATES:

This designed 16-bit adder, engineered with a combination of 2x1 multiplexers and XNOR
gates, stands as an extraordinary achievement in the realm of digital arithmetic circuits. Its unique
architecture equips it with the precision to generate both odd and even carries. Within the structure
of this circuit, the binary addition process is intricately subdivided into several stages, and each stage
prominently features a 2x1 multiplexer that strategically employs XNOR gates as select lines. The
outcome of each bit's addition is orchestrated through the collaborative operation of paired XNOR
gates.

The brilliance of this design hinges upon the inherent ability of the XNOR gate to differentiate
between two distinct inputs. This output, reflecting the parity of the input bits, serves as the
decision-making input for the multiplexer responsible for generating odd carries. When the XNOR
gate detects dissimilar inputs, it designates the bit as contributing to an odd carry, thereby dictating
the appropriate input selection for the multiplexer.

In the pursuit of generating even carries, astutely designed 2x1 multiplexers come into play. These
multiplexers rely on information gleaned from the XNOR gates to discern which bits should be paired
with the previous odd carry as the input for the production of even carries.

Concurrently, XNOR gates are strategically harnessed to simultaneously compute the sum for each
bit, imparting an exceptional level of efficiency and parallelism to the entire process. The result is a
finely-tuned, highly specialized 16-bit adder, meticulously optimized to execute the computation of
both odd and even carries with utmost precision.

This groundbreaking approach not only significantly amplifies computational speed but also serves
as a testament to the artistry of digital logic design when confronted with the specific challenges of
arithmetic operations. In summation, the 16-bit adder ingeniously crafted using 2x1 multiplexers and
XNOR gates represents a significant advancement in digital circuitry. It not only showcases its
remarkable ability to handle distinct types of carries but also underscores the ingenuity inherent in
tailored logic design, especially when applied to a larger bit width.
FIGURE 7 The circuit for generating carry bit of the proposed 16‐bit adder

32-bit RIPPLE CARRY ADDER USING MUX AND XNOR GATES:

The 32-bit adder we've designed, employing a clever blend of 2x1 multiplexers and XNOR
gates, represents a remarkable milestone in the domain of digital arithmetic circuits. This distinct
architectural approach grants it the precision necessary to generate both odd and even carries with
exceptional accuracy. Within the framework of this circuit, the binary addition process is
meticulously subdivided into multiple stages, with each stage prominently featuring a 2x1
multiplexer thoughtfully utilizing XNOR gates as select lines. The result of the addition operation for
each individual bit is expertly coordinated through the combined action of paired XNOR gates.
The genius of this design lies in the innate capacity of the XNOR gate to distinguish between two
disparate input values. This output, which mirrors the parity of the input bits, serves as the decisive
input for the multiplexer tasked with generating odd carries. When the XNOR gate identifies
dissimilar inputs, it signifies that the bit in question contributes to an odd carry, thereby guiding the
multiplexer in making the appropriate input selection.

For the task of generating even carries, ingeniously crafted 2x1 multiplexers come into play. These
multiplexers draw upon insights provided by the XNOR gates to discern which bits should be paired
with the preceding odd carry as inputs for generating even carries.

Simultaneously, XNOR gates are strategically harnessed to simultaneously calculate the sum for each
bit, introducing an exceptional degree of efficiency and parallelism into the entire process. The result
is a finely-tuned, highly specialized 32-bit adder, painstakingly optimized to execute the computation
of both odd and even carries with unparalleled precision.

This ground-breaking approach not only significantly amplifies computational speed but also serves
as a testament to the artistry of digital logic design when confronted with the specific challenges
posed by complex arithmetic operations. In summary, the 32-bit adder ingeniously crafted using 2x1
multiplexers and XNOR gates represents a monumental leap forward in the realm of digital circuitry.
FIGURE 8 The circuit for generating the carry bit of the proposed 32‐bit adder

COMPUTING THE DELAY OF THE ADDER USING THE LE METHOD

The critical path is the path that has the longest propagation delay from input to output. The critical
path in different adders and proposed adders are listed in Table 4. This table shows the critical path
without considering the sub‐branches. The minimum delay for the proposed circuits and other adder circuits is
calculated from the critical path. Some ex- amples of delay calculation are provided in the following: Consider the
circuit of the 8‐bit adder in Figure 5.In Figure 9, the blue path is chosen, which has the maximum number of levels.
The minimum delay is calculated for this path.

g MUX g XNOR + g XNOR 2∗4 +4 12 3

b 2= = = =
g MUX g XNOR 2∗4 8 2
There are two secondary paths, one with C7 and the other with C3:

b 2∗3
gMUX b1 g ∗2∗4 +2∗4 +2∗4
2 40 5
MUX g
NOR+¿ g g
MUX XNOR+ g g
2=¿ MUX XNOR
= = = ¿¿
gMUX b1 g 2∗3 24 3
MUX
gXNOR
∗2∗4
2

g MUX g MUX b 2 g MUX b1 gMUX g XNOR + g XNOR

b 3=
g MUX g MUX b 2 g MUX b1 g MUX g XNOR
2∗2∗5
∗2∗3
3
∗2∗4+ 4
2 164 41
¿ = =
2∗2∗5 160 40
∗2∗3
3
∗2∗4
2
 License
1751861x, 2023, 3-4, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/cdt2.12063, Wiley Online Library on [13/09/2023]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons
3
∗4
4
∗41
3 41
¿ b1 b2 b3 = =
40 20
G=g XNOR g MUX g MUX g MUX gMUX g XNOR
2 4
¿ ( g XNOR ) (g ¿¿ MUX) ¿
2 4
¿ 4 ∗2 =256
P=2 P XOR +4 P MUX =6∗4=24

( )
1
N 256∗41 16
D=N ( F ) + P=6 +24=41.040
20

Consider the proposed 16‐bit adder in Figure 7. The C11 path is selected for this adder, and its
minimum delay is calculated according to the violet path in Figure 10.To calculate the delay of the
proposed 32‐bit adder, the longest path should be selected. According to Figure 8, the longest
path is the path composed of six multiplexers and two XNOR gates, including the C15 location,
which has the maximum number of secondary branches. Therefore, the path marked in red in Figure
11, which passes C23, is selected.The delay calculation for 8, 16 and 32 bits adders has been shown, the
delays of other adders are calculated similarly.The general equation for delay calculation in the LE
method is calculated by using Equation (15) for the proposed adder in n bit.

T =T MUX 2 ( log n2 +1 ) +2 T XNOR 2

The Equation (15), shows the number of adder bits in n, the delay of a two‐inputs multiplexer in TMUX2, the
delay of a two‐inputs XNOR in TXNOR2 and the circuit delay in T. Table 5 shows the minimum delay for
the proposed adder and other adders. As it is obvious from Table 5, the delays of the pro- posed adder with all
numbers of bits are smaller than those of other adders, indicating the efficient performance of the proposed
approach. In LE calculations, the critical path includes the main path and the branches connected to the
main path. In case of CSA, there are many sub‐branches connected to the main path, which makes its
delay a little longer than the proposed adder. But in Table 4, it only shows the critical path gates and
does not include sub‐ branches.
PROPOSED
8 BIT ADDER USING EXNOR AND MUX
16 BIT ADDER USING EXNOR AND MUX
32 BIT ADDER USING EXNOR AND MUX
8 BIT ADDER USING MUX
16 BIT ADDER USING MUX
32 BIT ADDER USING MUX
RIPPLE CARRY ADDER:

A Ripple Carry Adder (RCA) consists of a sequence of full adders, with the number of full
adders being equal to the number of bits involved [3]. The initial full adder takes as inputs the least
significant bits of two numbers, denoted as A(0) and B(0), along with an input carry signal, typically
labeled Cin. The output of this first full adder yields the least significant bit of the sum and a carry-
out signal, which then propagates to the subsequent full adder, and so forth. This cascade of carry
signals is why it's termed a "Ripple Carry Adder." While the RCA design is space-efficient, it does
suffer from significant circuit delay.

RCA presents a trade-off between its compact area footprint, which is relatively small, and its
prolonged delay in processing. When compared to other types of adders, the RCA exhibits higher
power consumption. In summary, the Ripple Carry Adder combines advantages such as a small area
footprint with disadvantages like increased delay time and greater power usage. A Circuit is shown in
Fig. 1.

Equations:

S = A xor B xor Cin

Cout = AB + BCin + ACin.

Upon examining the block diagram, we can identify the operands utilized as A and B, the operation
to be executed as addition, and the outcomes sought after as the sum (S) and carry (C). Commencing
with the least significant bits of the operands, namely A(0) and B(0), they are directed to the initial
full adder, while assuming an input carry (Cin) of 0. The ensuing outputs consist of the first bit of the
sum, denoted as S(0), and the carryout, referred to as Cout, which is then transferred to the
preceding full adder. Analogously, the second bits of the operands are conveyed to the second full
adder, the third bits are routed to the third full adder, and the fourth bits are supplied to the fourth
adder in sequence. The sum produced by each individual full adder corresponds to the respective bit
of the sum, while the carry generated by each full adder is propagated as the input carry to the
subsequent full adder. Ultimately, the last full adder furnishes us with the output carry resulting
from the executed operation.

1-bit RIPPLE CARRY ADDER USING 4*1 MUX:

An 1-bit adder constructed exclusively with 4x1 multiplexers is an intriguing example of minimalist
yet effective digital circuit design. In this unique configuration, a series of 4x1 multiplexers is skillfully
arranged to execute the addition of two 1-bit binary numbers. This approach simplifies the circuitry,
as each 4x1 multiplexer replaces the complex arrangement of logic gates typically found in
conventional adders.

To comprehend this design, it's essential to first understand how a 4x1 multiplexer functions. A 4x1
multiplexer has four data inputs (D0, D1, D2, and D3), one select input (S – Two bit), and one output
(Y). The select input determines which of the four data inputs is passed to the output. When S is set
to 00 in binary, D0 is selected; when S is 01, D1 is chosen, and so forth. This fundamental operation
forms the basis of the entire 8-bit adder.

In this 1-bit adder design, two different multiplexers are used to generate sum and carry seperately
for each bit so therefore 2 multiplexers. The inputs A and B are used as select lines in both
multiplexers generating sum and carry. For the multiplexer generating sum, the two inputs are C and
other two inputs are negation of C (D0 = C, D1 = ~C, D2 = ~C, D3 = C). Thus, the output for the bit of
A and B is stored sum. For the multiplexer generating sum, the two inputs are C and other two
inputs are ground and VDD (D0 = 0, D1 = C, D2 = C, D3 = 1). Thus, the output for the bit of A and B is
stored carry.
8-bit RIPPLE CARRY ADDER USING 4*1 MUX:

An 8-bit adder constructed exclusively with 4x1 multiplexers is an intriguing example of

minimalist yet effective digital circuit design. In this unique configuration, a series of 4x1
multiplexers is skillfully arranged to execute the addition of two 8-bit binary numbers. This approach
simplifies the circuitry, as each 4x1 multiplexer replaces the complex arrangement of logic gates
typically found in conventional adders.

To comprehend this design, it's essential to first understand how a 4x1 multiplexer functions. A 4x1
multiplexer has four data inputs (D0, D1, D2, and D3), one select input (S – Two bit), and one output
(Y). The select input determines which of the four data inputs is passed to the output. When S is set
to 00 in binary, D0 is selected; when S is 01, D1 is chosen, and so forth. This fundamental operation
forms the basis of the entire 8-bit adder.

In this 8-bit adder design, two different multiplexers are used to generate sum and carry sperately
for each bit so therefore 16 multiplexers. The inputs A and B are used as select lines in both
multiplexers generating sum and carry. For the multiplexer generating sum, the two inputs are C and
other two inputs are negation of C (D0 = C, D1 = ~C, D2 = ~C, D3 = C). Thus, the output for each bit of
A and B is stored sum. For the multiplexer generating sum, the two inputs are C and other two
inputs are ground and VDD (D0 = 0, D1 = C, D2 = C, D3 = 1). Thus, the output for each bit of A and B is
stored carry. The carry generated by previous bit is fed as input for the next bit.

In summary, the 8-bit adder utilizing only 4x1 multiplexers is a minimalist yet highly efficient digital
circuit. It leverages the select lines of the multiplexers to manage the addition of each bit position in
parallel, resulting in a streamlined and speed-optimized addition process. This innovative approach
highlights the power of creative circuit design in achieving effective and efficient digital arithmetic
operations.

16-bit RIPPLE CARRY ADDER USING 4*1 MUX:

A 16-bit adder, designed exclusively with 4x1 multiplexers, represents a fascinating

example of a streamlined yet robust digital circuit architecture. This unique setup orchestrates an
array of 32 multiplexers to perform the addition of two 16-bit binary numbers with remarkable
efficiency. By adopting this approach, the complexity inherent in conventional adders, typically
reliant on intricate arrays of logic gates, is elegantly circumvented.

To grasp the essence of this design, it's imperative to gain a comprehensive understanding of how a
4x1 multiplexer operates. Each 4x1 multiplexer features four data inputs (D0, D1, D2, and D3), two
select inputs (S0 and S1), and a solitary output (Y). The role of the select inputs is pivotal, as they
dictate which of the four data inputs is propagated to the output. For instance, when S0 and S1 are
both set to binary 00, the multiplexer routes data from input D0; when configured as 01, it selects
D1, and so forth. This foundational operation forms the cornerstone of the entire 16-bit adder's
functionality.
In this meticulously crafted 16-bit adder design, a pair of multiplexers is ingeniously employed for
each bit position to independently generate the sum and carry. This translates to a total of 32
multiplexers in use, as every bit in the 16-bit binary numbers is subjected to this process. The inputs
A and B, derived from the binary numbers, are judiciously employed as select lines in both sets of
multiplexers that handle sum and carry computations.

For the multiplexers responsible for generating the sum, the inputs are configured such that two are
connected to the carry-out (C) of the previous bit, and the other two are connected to the negation
of the carry-out (~C). This arrangement ensures that the output of each bit's sum is accurately
stored.

Conversely, for the multiplexers dedicated to carrying generation, the inputs are structured
differently. Two inputs are linked to the carry-out (C) of the previous bit, while the remaining inputs
are fixed at ground and VDD (D0 = 0, D1 = C, D2 = C, D3 = 1). Consequently, the output of each bit's
carry is efficiently computed and retained. The carry generated by each bit is seamlessly fed as input
to the subsequent bit in the sequence.

In summary, this 16-bit adder, exclusively employing 4x1 multiplexers, embodies a philosophy of
minimalism and efficiency in digital circuitry. It harnesses the inherent parallelism facilitated by the
multiplexers' select lines, resulting in a remarkably streamlined and rapid addition process. This
innovative design exemplifies the transformative potential of creative circuit architecture when
addressing the challenges of high-bit-width arithmetic operations.
32-bit RIPPLE CARRY ADDER USING 4*1 MUX:

A 32-bit adder implemented with 4x1 multiplexers represents an intriguing

advancement in digital circuitry. This distinctive design efficiently performs the addition of two 16-bit
binary numbers by utilizing a network of 32 multiplexers. In contrast to traditional adders that rely
on intricate arrays of logic gates, this approach simplifies the circuitry while maintaining robust
functionality.

Understanding the fundamental operation of a 4x1 multiplexer is crucial to grasp this design. Each
4x1 multiplexer includes four data inputs (D0, D1, D2, and D3), two select inputs (S0 and S1), and a
single output (Y). The select inputs dictate which of the four data inputs is transmitted to the output.
For example, setting S0 and S1 to binary 00 directs data from input D0, while configurations like 01
select D1, and so forth. This foundational operation serves as the basis for the 32-bit adder's
operation.

In this meticulously engineered 32-bit adder, a pair of multiplexers is ingeniously employed for each
bit position to independently compute both the sum and carry. This results in the utilization of a
total of 64 multiplexers, as every bit in the 32-bit binary numbers undergoes this process. The inputs
A and B, derived from the binary numbers, cleverly serve as the select lines for both sets of
multiplexers, facilitating the sum and carry calculations.

For the multiplexers responsible for sum generation, the inputs are configured such that two
connect to the carry-out (C) from the preceding bit, while the other two are linked to the
complement of the carry-out (~C). This arrangement ensures precise computation and storage of
each bit's sum.

Conversely, the multiplexers designated for carry generation utilize a different input structure. Two
inputs are linked to the carry-out (C) from the previous bit, while the remaining inputs are fixed at
ground and VDD (D0 = 0, D1 = C, D2 = C, D3 = 1). This enables efficient calculation and retention of
each bit's carry. The carry generated by each bit seamlessly serves as the input for the subsequent
bit in the sequence.

In summary, this 32-bit adder, exclusively utilizing 4x1 multiplexers, embodies the principles of
simplicity and efficiency in digital circuit design. By harnessing the inherent parallelism offered by
the multiplexers' select lines, it achieves a streamlined and rapid addition process. This innovative
design exemplifies the transformative potential of creative circuit architecture when tackling the
complexities of high-bit-width arithmetic operations.