Multiplexer(MUX)

Itis a selects
combinational ckt that
binary information
from me of
many inputs
lines and

directs itto
single outputline.
The selection
of particular inputline is controlled selection (in. Generally, there 2" inputlines
a
by a seto f are

and n selection lines whose bitcombinations ditumine which inputis selected.

Multiplexer can also be named as

1) Data selector

2) Many to me circuit

3) Universal logic converter

parallel series converter

4)
to

5) Waveform generator

If be the total number

inputand lines, then
m ofdata i be the number
of selection

FigD:Functional diagram a

aI
of

- MUX output digital multiplexes.

:
Im >
"....
N M

So Si Sn-1
-
n selection lines

Baric 2-line 1-line to Mux

Fig shows logic cirmitand the table

function of 2:1 Mux. Ithas two
inputlines as

To and I, and one selectlines. The

data outputline is
designated
as Y-

S Y
Io O

2:1 MUX Y Io
y 5I + 51,
0 =

=>

I, I I Il

(a) Block
Diagram (b) Table
Function

If

Io ⑧
· X ⑳
· Y
&

⑧
I,

I...s
(C) Circuit
Switching (d) Logic Circuit

Fig&:2:1 Multiplexes
The 4-line to 1-Line MUX

A4:1 line multiplexes is shown in

fig. Each the four
of
inputs, Io, I,, Iz and Is are applied
to the inputof
Mux and
logic levels applied tothe selection
lines so and s.. The logic base
ciemit on
function table is
shown in
fig.
·

Is 0
Si So Y
-

I, I ⑧ 0 Io
4:1 MUX Y
Iz 2 0 I I
I3 3 I O Iz
I I
I3
Si So

(a) Block
Diagram (b) function
Table

fig: 4:1 Multiplexes

from function
table we have, y 5,500+
=

5,501, +5,50I2+S,S.Is

E
7.
8

C-
I,
⑳

·
Y

7-
12

⑧
-

Iz8
⑳

⑳
C
Sio I i
I
·

Soo ④

Fig: Logic Circuit

of 4:1 Mux.

The 8-line to 1-line Mux

S2 Si S E
Y

00 0 Io
I >

8 0 I Is
1, o
X
0 1 0 12
Iz 3

8:I MUX D I I 13
Izo 7
10 8
147 -Y I4
I ⑧ I
-

150 7 I5
I I ⑧
I, 7 76

I I I 17
118 3

(b) function Table

a N R

E A

S2, So

197 Block
Digram fig:8: 1
multiplexer
y 525,57+ 25,5,]
=

+ 525,5.Ez + 525,SoIs

S5, 5. Int S25,S. I;+S2S, 5.Is+ S2S,So Iz

Q:Dlaw
logic ckt. for 8: Mux.

Mux as an Universal logic hate

(Using 2:1
Mux)
NOT Gate.

Aswe known
1.
J.Ip
. D
y =
+

S, I, 2:I
87
·

MV*
y A10 A I,
+

78 ⑧
=

If 70
=

191, 0
=

then A
y= as For NOThate -

Gate
AND

For AND operation

3
-
B
Y
y
-

AB
=

As we also know for a 2:1 Mux

conrot(x) 1.
. ⑧
2:I
87
·

MVN
y 5.Io+ S, I
=

B
78
if
A is the slection
line

y A =

I AI,
+

-
if
Io 0
=

4 B
1=

Y AB=

OR Gate

yA =

B
+

Bo
oX

coted(A)
1.
. B
2:I
87
·

MVN
*y 3010+ SoII I
78
=

A Io +AIl
=

AB+
=

A. I A

=
AB A +

(x A)(A B)
= +
+

=
A B +

So, Io B and
=

I, = 1
 NOR Gate

FORNOR operation y ABi.e =

complementof OR
gate ↳.
B2: 1
Hence, to
required Max is 2, one
perform or
operation and other one
MVX
d
87
·

0
perform complement.
to 78

:. T =
B
and I, 0
=

NAND Gate

For NAND operatos y IB =

i.e. complementofANDgate
1.
Hence, required
I
and other .
Mix is 2, one
perform
to AND
operates one
perform
to
2:I
87
·

MV*
complement. 7. E

.. Io= 1 and I, B =

Ex-OR Gate

For Ex-OR operation

1. B
y AOB=

AB + AB
=
.
2:I
87
·

MVN
and we also know thattor 2:1 Mux B
78
Y 501. +S,2,
=

I
=> B
= and 1, B =

... No of
mux required 2
=

Ex-NOR
gate
For Ex-NOR
operation, Y A&B AB
=
= +

AB
1. . B
2:I
and we also know thattor 2:1 Mux
87
·

MVN

Y 501. +S,2,
=

78 B

I B and I, B
=

=> =

A
... No
mux required
of 2
=

In order implementlogic gates

with4.1 Mox, thath table
to
required.
is

For example,
For AND Gate

Truth table

A B y
De Io

0 4:1

ooo Do I
MUX
Y

!O
00- I2

10 Is
0
Si So

I I I
⑮ B

Gate
AND

Similarly
0. Io
1. Io I ⑤ Io Os Io 1. Io

4 1 4:1 4:1 4:1 4:1

I I 1 Do I,
MUX o
I
MUX
Do I
MUX 1 I
MUX MUX
Y Y Y Y Y
I ⑥
I2 70- I2
10- I2 0 I2 I2 0
-
o-
o-

I o Is
0 o Is ⑧ ⑧ Is O Is I o Is

Si So
Si So
Si So Si So Si so

⑮ B
⑮ B ⑮ B ⑮ B ⑮ B

OR-Crate NAND NOR Ex-OR -X-NOR

L
:
 Application of MUx

1) Data Selection

2) routing
Data

3)
Operation
sequencing
4)
Waveform generation
parallel serial conversion
5) to

6) Logic function
generator.

Note! two variable

-

By using 4:1 Mux

any function and some
ofthree variable
functions
can be
implemented.
However, 4:1 and two variables all three
functions be implemented.
wing MUX a
gateall
NOT as well as variable can
 Boolean function
Implementation Mux
using

1. Expeen the in its

function sop
form.
In connect the selectline
sequence n-variables, (n-1)
2. the ordered of variables to and the

single highestorder position variable the

to
inputline with complemented or
uncomplementfrom
including 0 and I.

Listthe ills in two

3.
Mux
of rows.

for Istlw -> selectvariable is

complemented
for and saw - i 4
uncomplemented
Circle all
4. the mintesis
of the
function
and inspecteach column
separately
5. If
two mintams in a column are not circled, apply '0' to the
cosponding mux
input.
6. Iftwo minitesms are circled, apply 1 the
to
colsesponding mux
input.
1. minterm is ciecled, front value is the
Ifone then its
correspondingMux input.

Example!Implementf(A, B, 2) 2m =

(0, 1, 4,6,7) by uning 4:1

the Mux.

Solot":- Case
-
I

Let A
and B are the selectlines and be input
the

For tenth table is

3 variable
function, the In Is In Is

A B C Y I 0 2 4 6 Imystementat
D 0 O 0 I C
I 3 5 7
=
table
I

·
10 -

I 0 C I

4 I
I
the
Thus, for implementation
of
given logical function,
5

6 I I 0 I required is one 4x1 mux and an invester.

7 I I I I 1 a Io

0-14x1
-
Mox-oX
Co- Iz

10Is-

Si So

I I
B
C

LaI:B9C are selectlines

the and A as
input

I3

,
Iz
F 2 3 I 0
-
Io
13
4x1
A ⑥ 0
7 A -

MUX
ox
00

I
-

A -
*
-
Iz 0 I
10
*-I3
B+A5c ABI ABC +
S so
I I
y
=
+
I

NBI+ABI
=
* ABL+ABI+ DBC .
I I
⑧

1107
B 2

000
001
=100 40
W
G:A, are selectlines
the and Bas
input

I3
5
In
-

B B 0
-
Io

B 2 30 B 14x1
MUX
=

ox
15 15 11 1
-

Iz
B 1 -
-

Is
B =

Si So

I
0
I
O

0 0
ol

Y ABI + ABc Al ABC +

+
A L 10
I
=

ABI
=
xB AB AB
+
+
+

ABC
+

=000 00l 11010011

0 I 6 4 7
Use
.
a multiplexes having the selectlines implementthe function
to
given
F Em(0, 1,2,3,4,10,11,14,15)
=

For function, the truth table is

* a 3 variable

LetA line and

and Bare the select I be the
input
A B C D Y Io II Iz Is I415Is It
D 8 000 I -

B 0 2 46 8 10 12 14
I D I I

%888
D I 3 5 7 9 1113 15
I 0

0
I
! Thus, the
I

implementation
of
1 2

the given function

is as
0 0 10 1

5 I I 0
0
follows.
6
0 I I 0 0

7
0 11 l 0
10 - lo
⑧
100 0 O
1 - -
1
9 I ⑧ 0 I 0
Io-Iz
10 I 0 I 0 I 8:
8--I, -Y
11
I 0 I
d
MUX
0.-I4
12
I , I
1 15 -

13
I I 0 I I
0-Is
I b
↳
I I
I 0
1-
Iz
15 I I S2 S, So
I I I

isi s
 DEMULTIPLEXER
-

demultiplexes
A combinational 2
is a cut that
receives
information
on a
single line and transmits this
on one
of
possible outputlines. However the selection
of
a specific outputlines is controlled by the
bitvalue a of selection
lines.

Demultiplexes also
is known as:

1) distributor
Data

2) Serial parallel
to converter

One circuit
many
3) to

Itused
perform
to severe
the
operation Mox. of

"
For's' number selection
lines, the total
of number ofoutput =2

Ein
zonet
Input -> DEMUX

444-...4
-
n-selection lines

FigD!Functional diagram of
a digital DEMUX.

I a line
to
demultiplexes
Fig& shows the
logic cilantand
function
table
for 1:2 line DEmux. It has an
which outputto
inputI for and 4, are obtained.

·Yo

Do-3-T
-
Yo S'Y, Yo
-

I
- >

2:1 ·Yo 5I

--
= 10
x

-
⑦
-
I --DEMUX
Y, SI
=

·Y
-Y
I -

-4
-

Is ⑥ Function
Table ② Switching Diagram ·S

⑨
⑨ Block
diagram Logic [kt.
Fig: 2:1 line demodulator

I to 4 line demodulator

A 1:4line is shown
DEMUX
infig.
Si So Yy Yz YI Yo
-

·Yo Yo 5, J I
10
⑧ 00 O ↑
-
E
=

line
1:4 -
Y O ⑧ I 0 Y1 5
=

SoI
Ia Demux
oYz
0 0 IO
Yz
0
I
-

S,50 I
=

- > Yo I 10
1 0 Y =S, SoF

Si
!
(a) Block
Diagram ⑥ Function Table
 Si S 0 I
O
O

-
-

).
④*8.

>
8.

so
·% 5,
⑳ =
I

)-oY, Fig :
⑧

5,
=
so I line
114
demultiplexes
·

7-oY
.

·
5,5
=

. 3 ots S. So I
=
 Decoders.
-

Adecoder have
many inputs many outputs.
- and

-> a combinational
It is
logic altthatconvente firm
binary information
a bit
inputlines to

2* line such thatone outputline isactivated

a maximum
unique output for each one
of
possible combinations
ofinput.
Typical
- >

applications !

1. Code Converters
2. BCD seven to
segmentdecodes

Ifthe decoded has don'tcare combinations,

-> n-bit
information unused or decoder
the

have her 2"

outputwill than
outputs

E E I
Ao >

n inputs 2
!
DECODER
puts (. Yigimpucodal
An -Y -
1

General
Fig D: block
diagram a decodes
of

line decoder
2x 4

2x4decoders decoders
-> an minimum possible
LetA & B
inputs 40, 4,, Y2&Ys for outputs
->

are and are

I
Yo
[Enable
-

E outputs
A
ne 2x4 line is used to
Y
input
-

Line 2 decode
-

control the operations

Be re decoder
-
Y3

dEnable
=>

Fig &: 2 to 4 line decode with

enable input

For the 2,
figure we have

The Boolean Expressions

for the outputs
four are,

A B Yo X, x2 X3 Yo xB=

y=A B

0 0 I 000 Yz AB=

O I ⑧ 100 Y3 AB
=

D 00 I 0
I

I 0 00 I
I

Figs: Truthtable for

2x4 line decodes
 The internal
circuitry decodes exactly
->
of and DEMux
a re same.

2:4line
->

decoder act like 1:4 DEmux and vice versa.

may
a

ifference between Decodes and Demultiplexer

*

Parameter Demux Decoder

Number
data inputs
of one more than t

Select
inputs Present Absent

pplications
A Distribution switch, to
BCD seven
segmentdecoder,
to Decimalto BCD
implementBoolean etc.

Experines

3 to
8 Line Decodes

Truth Table
Logic diagram.
-

A BC

Inputs
* :
Outputs
A B
C Yo YI Y2Y3Yx45Y6Y7 -

I 0 00 000 0
·
60oI
O

B
0000 0
↓
0 0 0
⑧ ABI
I

00088
0

810
⑧

↓
98
00 O

! 0 O
⑧

10000 0000 8 I I O O
⑧

↓ ↑
I I D 0 00 00 0

I I oooooo I
8

⑳
· D-Y=ABI

D*
⑳

D Y5 BC
⑳

⑧ =

P3
Y ABI
⑧
-
=

Yz ABC
=
 Implementthe following
Boolean function
F(A, B, C, D) E m(0,1,3,4,7,8,9,11,14,15)
=

i) Kil Mux

ii) 2: 1 MUX

1. Using 4:1 Mux

implementation
table
A BCD y
0 0 00 ⑧ I

1000 I I Io I, Iz In
2
0 0 I 0 0

30 0 1 I I 25048 12

0
0 1 0 0 I ID 5 9 3
13

6 10

⑮
50 I 0 I O 2

60 1 1 8 0

10 11 I I

·1000 8

10 I

↳
9 0 O
10 I 0 1 0 0

11 I 01 I = I (D +

12
I I 00 0 =
[ x)([ D) I
+
+
=
+

D
↳
13 I I 0 I O

I 10 I, IB cD c0D
=

14 I =
+

15 I I 11 I
Iz I =
D
+

I3 (5
=
cD
+

c(B D)
=
+
C
=

28
-

=
0

⑳
-

Io
D

I C
=>
I
4: I

MUX
oX
I2
·

I3
->

↓ B
I
 ii) using 2:1 mux

mplementation
#
table

Io Fi Io
5 B +
=
+
+

① 000
0 ⑪
- - -

ABC ⑧
B

-
1001 ABC 2 A 00 01 11 18

O
2010 #B I 5 0 -I C
↑

>011
100
Ih --
6

⑧ E
⑪
W
4
ABC 10 W
EI
-101 ABI 13
6 110 12 I BI ABC A +

⑭0
+
=

ABL 1
7 III
⑳
I ABI ABI ABI ABC
= +
+
+

A[(B B)
=
+
+
ABI +

ABC
I, FB ABC ABC+ABC
+ +

FI ABT
=

=
+
+
ABC
ABCA ABC +

B
I(F xB) ABC
=>
+
+

[(A A)(E B) ABC

A 00 ol 11 10 =

+ +
+

0 I I I

I I I I I(F B) ABC
= + +

↑ ↑ Al
=>

BI
+ +

ABC
B L

B+
I, =

Logic t

it i
⑳

B
D
·

Io
-

2. I
oY
⑧
D MUX

I,
-

So