Subject: Digital Electronics and Microprocessors

JNTUA
Unit Wise Important Questions
By
M.Sivakrishna, Asst.Professor
*-Important **-Very Important ***Very Very Important

Unit-1

NUMBER CONVERSIONS

1 (a) Convert the octal number 367412 to binary, decimal and hexadecimal. (R15-
REG-MAR-2021)

(b) Convert the following to Decimal and then to octal: (R15-REG-MAR-2021)

(i) (125F)16. (ii) (10111111)2. (iii) (4234)10.

2 List the octal and hexadecimal numbers from 16 to 32. (R15-SUP-OCT-2020)

3 (a) Explain any two binary codes with example. (R15-REG-NOV-2019)

(b) Each of the following arithmetic operations is correct in at least one number
system. Determine the possible bases of the numbers in each operation:
(i) 1234 + 5432 = 6666.
(ii) 41/3 = 13.
(iii) 33/3 = 11. (R15-REG-NOV-2019)

4 Explain the binary codes with examples. (R15-SUP-JUNE-2019)

5 Convert (3456)8 to base 3 and base 7. (R15-SUP-JUNE-2019)

6 The solution to the quadratic equation x2 – 11x + 22 = 0 is x = 3 and x = 6. What is

the base of numbers? (R15-SUP-JUNE-2018)

7 Convert the following: (R15-SUP-JUNE-2018)

(i) (163.789)10 = ( )8.
(ii) (101101110001.00101)2 = ( )8.
(iii) (292)16 = ( )2.

8 Convert the following to decimal and then to binary: (i) 110116. (ii) ABCDE16.
(R15-REG-NOV-2017)

9 Convert the following to Decimal and then to Octal. (i) 420416. (ii) 10100112. (R15-
SUP-JUNE-2017)
BOOLEAN EXPRESSIONS & LOGIC GATES

1 (a) What are the various logic gates, give the representation along with the truth
table.(R15-SUP-AUG-2021)
(b) Find the complement of the following Boolean function and reduce into minimum
number of literals: Y= (BC’+A’D)(DB’+CD’)(R15-SUP-AUG-2021)

2 Find the complement of the following and show that F.F’ = 0 and F + F’ = 1.
(i) F = xy’ + x’y.
(ii) F = (x + y’ + z)(x’ + z’)(x + y). (R15-SUP-JUNE-2018)

3 Find the complement of the following and show that A. A′ = 0 and A + A′ = 1.

(i) A = xy′ + x′y.

(ii) A = (x + y′ + z)(x′ + z′)(x + y). (R15-REG-MAR-2021)

4 Reduce the following Boolean Expressions to the indicated number of literals:

(i) A′C′ + ABC + AC′ + AB′ to two literals.

(ii) (X′Y′ + Z’) + Z + XY + WZ to three literals.

(iii) A′B (D′ + CD) + B(A + A′CD) to one literal. (R15-REG-MAR-2021)

5 (a) Simplify the following algebraic expression: (R15-REG-NOV-2019)

(x’ + xyz’) + (x’ + xyz’)(x+x’y’z)
(b) Prove that if w’x+yz’ = 0 , then
wx+ y’(w’+z’) = wx + xz + x’z’+w’y’z

6 Obtain the dual of the following Boolean expressions:

(i) AB + A(B+C) + B’(B+D). (ii) A + B + A’ B’C. (R15-REG-NOV-2017)

7 Reduce the expression f = A[B+C’(AB+AC’)’]. (R15-REG-NOV-2016)

SOP & POS

1.Determine the canonical sum-of- products representation of the following function:
f(x,y,z) = z + (x’+y)(x+y’) (R15-REG-NOV-2019)

2 Simplify the Boolean expressions to minimum number of literals:

(i) X′ + XY + XZ′ + XYZ′ . (ii) (X + Y)(X + Y′) (R15-SUP-JUNE-2019)

3 Find the complement of the following Boolean function and reduce into minimum
number of literals. Y= (BC’+A’D)(DB’+CD’) (R15-SUP-JUNE-2017)
4 Express the Boolean function F = A+B’C a sum of min terms and product of max
terms. (R15-SUP-AUG-2021)

5 Simplify the following Boolean expressions to a minimum number of literals:

(i) (A’+C)(A’+C’)(A’+B+C’D)
(ii) x’y’ + xy + x’y (R15-REG-NOV-2016)

6 Convert the given expression in standard POS form. Y = A. (A + B + C). (R15-SUP-

JUNE-2019)

7 Express the Boolean function f = A(A’+B)(A’+B+C’) to maxterms. (R15-REG-NOV-

2016)

COMPLEMENTS

1 What is the use of complements? Perform subtraction using 7’s complement for the
given Base-7 numbers (565) - (666). (R15-SUP-AUG-2021)

2 Perform subtraction on the following unsigned numbers using the 2’s complement
of the subtrahend.
Where the result should be negative, 2’s complement it and affix a minus sign:
(i) 10011 – 11001.
(ii) 1011 – 110000.
(iii) 101010 – 101011. (R15-SUP-OCT-2020)

3 Perform N1 + N2, N1 + (-N2) for the following numbers expressed in 2’s

complement representation. Verify answers by using decimal addition and
subtraction.
N1 = 10001110 N2 = 00001101 (R15-REG-NOV-2016)

K-MAP, NAND & NOR GATES

1 Simplify the following using K- map and implement the same using NAND gates:
Y (A, B, C) = Σ (0, 2, 4, 5, 6, 7) (R15-SUP-AUG-2021)
(b) Simplify the following expressions: (R15-SUP-AUG-2021)
(i) T(x, y, z) = (x + y) {[x’ (y’ + z’)]’} +x’ y’ +x’ z’.
(ii) X(A, B, C, D) = A’ B’ C’ +(A+B+C’) ’ +A’ B’ C’ D.

2 (a) Simplify the following expression into sum of products using Karnaugh map:
F(A, B, C, D) = Σ(1, 3, 4, 5, 6, 7, 9, 12, 13) (R15-SUP-AUG-2021)
(b) Simplify the following to the minimum number of literals. (R15-SUP-AUG-2021)
(i) A’B (D’ + C’D) + B (A + A’CD).
(ii) x’y’ +xy + x’y.

3 Reduce the following expression to the simplest possible POS and SOP forms: F =
Σm(6, 8, 13, 18, 19, 25, 27, 29, 31) + d(2, 3, 11, 15, 17, 24, 28)R15-REG-MAR-2021)
4 Simplify the following expression into sum of products using Karnaugh map: F(A,
B, C, D) = Σ(1, 3, 4, 5, 6, 7, 9, 12, 13) (R15-REG-MAR-2021)

5 Simplify: (i) A′B + A′BC′ + A′BCD + A′BC′D′E. (R15-REG-MAR-2021)

(ii) (P + Q + R) (P′ + Q′ + R′) P.

6(a) Simplify the following Boolean function in: (i) Sum of products. (ii) Product of
sums.
F(A, B, C, D) = ∑ (0, 1, 2, 5, 8, 9) (R15-SUP-OCT-2020)
(b) Implement the following Boolean function with NAND gates:
F(x, y, z) = ∑(1, 2, 3, 4, 5, 7) (R15-SUP-OCT-2020)

7 (a) Find the minterms of the following Boolean expressions by first plotting each
function in a map:
(i) xy +yz+ xy’z.
(ii) wxy +x’z’ + w’xz. (R15-REG-NOV-2019)
(b) Draw a NAND logic diagram that implements the complement of the following
function: F(A,B,C,D) = ∑ ( 0,1,2,3,4,8,9,12) (R15-REG-NOV-2019)

8 Simplify the Boolean expression using K-map and implement using the NOR gates:
F(A, B, C,D) = Σm(0, 2, 3, 8, 10, 11, 12, 14) + Σd(4, 9) (R15-SUP-JUNE-2019)

9 Simplify the following Boolean functions, using four variable maps:

(i) F(W, X, Y, Z) = ∑(1,4,5,6,12,14,15).
(ii) F(A, B, C, D) = ∑(1,5,9,10,11,14,15). (R15-SUP-JUNE-2018)

10 Simplify the following function using K- map and implement the same using NAND
gates: F(A,B,C)=∑ (0,2,4,5,6,7) (R15-SUP-JUNE-2018)

11 Simplify the following Boolean expressions using K-map and implement them
using NAND gates. F(W, X, Y, Z) = XZ + W’XY’ + WXY + W’YZ + WY’Z (R15-REG-
NOV-2017)

12 (a) Reduce the following expressing using k-map: f = ∑m(1,3,4,5,8,9,13,15). (R15-

REG-NOV-2016)
(b) Obtain minimal POS expression for ΠM(1,2,3,8,9,10,11,14) d(7,15). (R15-REG-
NOV-2016)
(c) Implement the following function using only NOR gates: F = a(b + cd) + bc’.
(R15-REG-NOV-2016)

Unit-2
COMBINATIONAL CIRCUITS

1 Explain design procedure for combinational circuit. Differentiate between

Combinational circuit & Sequential circuit. (R15-REG-MAR-2021)

2 Design a combinational circuit that generates the 9’s complement of a BCD digit.
(R15-SUP-OCT-2020)

3 Design a combinational circuit which reads 3 bit input data and outputs square of
the input. (R15-REG-NOV-2019)

4 Design a combinational circuit with three inputs A, B and C and three outputs x, y
and z. When the binary inputs are 0, 1, 2 and 3, the binary output is one greater than
the input. When the binary inputs are 4, 5, 6 and 7 the binary outputs are one less
than the input. (R15-REG-NOV-2016)

ADDERS & SUBTRACTORS

1 Design a full adder by using two half adders. (R15-SUP-AUG-2021)

2 Design of full adder by using two half adders. (R15-REG-MAR-2021)

3 Explain the binary adder – subtractor with neat block diagram. (R15-REG-NOV-
2019)

4 (a)Design and draw the full-adder. (R15-SUP-JUNE-2019)

(b) Design and draw a logic circuit diagram for full adder / subtractor. Let us consider
a control variable w and the designed circuit that functions as a full adder when w =
0, as a full subtractor when w = 1. (R15-SUP-JUNE-2018)

5(a) Design a full subtractor and implement it using NAND gates. Explain its
operation with the help of truth table. (R15-SUP-JUNE-2018)
(b) Draw the schematic diagram and truth table for full adder. Explain the design
approach for full adder using universal gates. Draw the relevant logic diagrams with
necessary expressions. (R15-SUP-JUNE-2018)

MULTIPLEXERS & DEMULTIPLEXERS

1 Discuss a few applications of multiplexers and distinguish between a multiplexer

and a decoder. (R15-SUP-AUG-2021)

2 Define a multiplexer. Draw a 4:1 multiplexer for the function f(a,b,c,d) =

Σ(0,4,5,10,11,12,15). (R15-SUP-AUG-2021)
3 (a)What is a multiplexer? Draw and explain the 4-to-1 Line Multiplexer operation.
(R15-SUP-OCT-2020)
(b) Implement the following Boolean function with a multiplexer:
F(A, B, C, D) = ∑(0, 1, 3, 4, 8, 9, 15) (R15-SUP-OCT-2020)

4 Define a multiplexer? Draw a 4:1 multiplexer for the function:

f(a, b, c, d) = Σ(0, 4,5,10,11,12,15) (R15-REG-MAR-2021)

5 Implement a full adder using 4 x 1 multiplexer. (R15-REG-NOV-2019)

6 Implement the following Boolean function using 4 × 1 MUX.

F(a, b, c) = Σm(1, 3, 5, 6) (R15-SUP-JUNE-2019)

7 Design 32:1 Multiplexer using two 16:1 Multiplexers and one 2:1 Multiplexer. (R15-
SUP-JUNE-2017)

8 Realize the function using f (A,B,C,D) - ∑m(0,1,2,5,9,11,13,15) using 8:1 MUX. (R15-
REG-NOV-2016)

ENCODERS & DECODERS

1 Explain about decoder circuit and implement the 4 × 16 decoder by using two 3 × 8
decoders. (R15-SUP-AUG-2021)

2 Construct 4*16 Decoder with help of 2*4 Decoder (R15-REG-MAR-2021)

3 Implement and odd parity generator for 3-bit using a decoder. (R15-REG-MAR-
2021)

4 Draw and explain the operation of 3 to 8 decoder. (R15-SUP-JUNE-2018)

5 With the help of a logic diagram and a truth table, explain a 3-line to 8-line decoder.
(R15-REG-NOV-2017)

6 Distinguish between an encoder and a priority encoder? Design an octal to binary

priority encoder. (R15-REG-NOV-2016)

PLA & PAL

1 (a) Write short notes on PLA. (R15-SUP-AUG-2021)

(b) Implement the following Boolean function using PLA: (R15-SUP-AUG-2021)
F1(A,B,C) = Σm(3,5,6,7)
F2(A,B,C) = Σm(0,2,4,7)

2 Compare PLA with PROM. (R15-REG-MAR-2021)

3 Explain the operation of PAL and implement the following two Boolean functions
with a PAL:
W(A, B, C, D) = ∑(2, 12, 13)

x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15)

y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z((A, B, C, D) = ∑(1, 2, 8, 12, 13) (R15-SUP-OCT-2020)

4 Explain the operation of PLA and implement the following two Boolean functions
with a PLA:
F1(A,B,C) = ∑(0,1,2,4).
F2(A,B,C) = ∑(0,5,6,7). (R15-REG-NOV-2019)

5 Implement the following function using PAL:

w(A, B, C,D) = Σm(0, 2, 7, 8, 9, 12, 13)
x(A, B, C,D) = Σm(0, 2, 6, 7, 8, 9, 12, 13, 14)
y(A, B, C,D) = Σm(2, 3, 8, 9, 12, 14) (R15-SUP-JUNE-2019)

6 Design the logic diagram using PLA with following functions: (R15-SUP-JUNE-
2018)
(i) Y1 = AB+A’C+ABCD.
(ii) Y2 = AB’C +ABC’ +AC’.
(iii) Y3 = AB.
(iv) Y4 = 0.

7 Design a PAL for the following logical functions: (R15-SUP-JUNE-2018)

(i) Y1 = AB+A’CB’.
(ii) Y2 = AB’C+AB+AC’.
(iii) Y3 = AB+BC+CA.

8 Explain detail about PAL and PLA. (R15-REG-NOV-2017)

9 Write short notes on PLA. (R15-SUP-JUNE-2017)

10 Implement the following Boolean function using PLA: (R15-SUP-JUNE-2017)

F1(A,B,C) = ∑m(3,5,6,7)
F2(A,B,C) = ∑m(0,2,4,7)

11 Implement the following Boolean function using PLA:

F1(A,B,C) = ∑m(3,5,6,7)
F2(A,B,C) = ∑m(0,2,4,7) (R15-REG-NOV-2016)
12 Implement a BCD to Gray code converter using ROM. (R15-REG-NOV-2016)

Unit-3
COUNTERS

1 Explain the operation of the 4-bit asynchronous counter. (R15-SUP-AUG-2021)

2 Design and draw the logic diagram for MOD-6 ripple counter. (R15-REG-MAR-
2021)

3 Design a 3-Bit binary counter using T-flips. (R15-SUP-OCT-2020)

4 Design and draw the 3 bit up-down synchronous counter using D flip-flop. (R15-
SUP-JUNE-2019)

5 Design a 3-bit counter using T flip flops. (R15-REG-MAR-2021)

6(a) Explain the operation of a BCD Ripple counter. (R15-REG-NOV-2019)

(b) Design a counter with the following repeated binary sequence: 0,1,2,3,4,5,6. Use
JK flip-flops. (R15-REG-NOV-2019)

7 Design modulo -12 up synchronous counter using T- flip flops and draw circuit
diagram. (R15-SUP-JUNE-2018)

8 Design a synchronous 3-bit up-down counter using JK flip flops. (R15-REG-NOV-

2017)

9 Design and draw the logic diagram for MOD-6 ripple counter. (R15-SUP-JUNE-
2017)

10 Distinguish between asynchronous and synchronous counters. Write the design

steps of synchronous counters.

11 Design a divide by 6 counter using T- flip flop. Write the state table and reduce the
expressions using K – Map. (R15-REG-NOV-2016)

FLIP-FLOPS

1 Explain the operation of S-R, J-K, T and D Flip-Flops with neat diagrams. (R15-
SUP-OCT-2020)

2 Define the following terms with relation to flip flop:(R15-REG-MAR-2021)

(i) Set-up time. (ii) Hold time. (iii) Propagation delay time. (iv) Preset. (v) Clear.

3 Draw and explain the logic diagram of Master-Slave J-K flip-flop.

(R15-SUP-AUG-2021)
4 Explain the working of a master-slave JK flip flop. State its advantages. (R15-SUP-
JUNE-2018)

5 Explain the working of the following: (R15-SUP-AUG-2021)

(i) J-K flip-flop.
(ii) S-R flip-flop.

6 Draw the schematic circuit of an edge-triggered JK flip flop with active low preset
and active low clear using NAND gates and explain its operation. (R15-REG-MAR-
2021)

7 (a)What is Race around condition? In which flip-flop operation it exists? Explain

how it can be eliminated with neat diagram. (R15-REG-NOV-2019)
(b) List the characteristic equations and excitation table of all flip-flops. (R15-REG-
NOV-2019)

8 Convert T-Flip Flop to D-Flip Flop and D-Flip Flop to T-Flip Flop, with relevant truth
tables and expressions. Also draw the logic diagrams. (R15-SUP-JUNE-2018)

9 How is the race around condition eliminated in JK Flip Flop? (R15-SUP-JUNE-

2017)

10 Convert S-R flip flop into JK-flip flop. Draw and explain the logic diagram. (R15-
SUP-JUNE-2017)

11 Draw the schematic circuit of an positive edge triggered JK Flip flop and explain
its operation with the help of the truth table. How is the race around condition
eliminated? (R15-REG-NOV-2016)

REGISTERS

1 With suitable logic diagram, explain a 4-bit bidirectional shift register. (R15-SUP-
AUG-2021)

2 Explain the operation of shift register with neat diagram. (R15-SUP-OCT-2020)

3 What are different types of shift registers? Explain any one type of shift register.
(R15-SUP-JUNE-2019)

4 Draw the logic diagram of a 4 bit shift resister. Explain how shift-left and shift-right
operations are performed. (R15-SUP-JUNE-2018)
 Unit-4

***1. Explain the internal hardware architecture of 8086 microprocessor with a neat
diagram. (R15-REG-JUNE-2018)

Explain the function and components of the execution unit of 8086 microprocessor.
(R13-SUP-JUNE-2017)
OR
Draw the internal architecture of 8086 microprocessor and explain its bus interface unit
(BIU). (R15-SUP-DEC-2018)

**2. Draw and explain the register organization of the 8086 and explain typical
applications of each register. (R15-REG-JUNE-2017)

*3. Differentiate between architecture of 8085 and 8086. (R15-REG-JUNE-2019)

***4. Explain with neat diagram how 8086 access a byte or word from even & odd
memory banks. (R13-REG-DEC-2015)
OR
Explain the concept of segmented memory. What are its advantages? (R13-SUP-JUNE-
2016)
OR
Explain the need for memory segmentation and segment registers of 8086
microprocessor. (R13-SUP-JUNE-2017)
OR
Discuss the different memory segments used in 8086 and their functions. (R15-SUP-
DEC-2017)

**5. Describe functions of following signals of 8086 microprocessor:

(a) RESET. (b) BHE. (c) DT/R. (d) TEST.(R13-REG-DEC-2016)

**6. (a) Compare the features of 8086 and 8085 processor.

(b) Explain how pipelining is achieved in 8086.
(c) Explain the function of following pins in 8086:
(i) ALE. (ii) INTR. (iii) HOLD. (iv)TEST (v) DT/R . (R13-SUP-JUNE-2016)

*7. Compare the instruction CALL and PUSH. (R15-REG-JUNE-2017)

***8. Describe addressing modes of 8086 with suitable examples. (R13-REG-DEC-

2015)
OR
Describe addressing modes of 8086 with suitable examples. (R13-REG-DEC-2016)
OR
Explain the addressing modes of 8086 with examples:
Register addressing mode. (ii) Indirect addressing mode. (iii) Relative index addressing
mode. (R13-SUP-JUNE-2016)
OR
Describe the register, indexed and base relative addressing modes of 8086 with example
instructions. (R13-SUP-JUNE-2017)
 OR
Explain any 8 addressing modes of 8086 processor with an example. (R15-REG-JUNE-
2018)
OR
What is addressing mode and discuss different types of addressing modes of 8086?
(R15-REG-JUNE-2019)
OR
Explain any three memory addressing modes supported by 8086 microprocessor with
examples. (R15-SUP-DEC-2017)
OR
Explain the addressing modes of 8086 with examples. (R15-SUP-DEC-2018)
OR
Describe the different program memory addressing modes in the 8086 giving an
example for each. (R15-REG-JUNE-2017)

**9. Draw and explain interrupt vector table of 8086.(R13-REG-DEC-2015)

OR
**10. Describe interrupts and interrupt response of an 8086 family process with neat
sketch.(R15-SUP-DEC-2018)

**11. (a) Explain the steps involved in execution of software interrupts in 8086.
(b) Explain the types of software interrupts of 8086.(R13-SUP-JUNE-2017)

**12. Draw a circuit showing the generation of I/O read and write control signals in the
minimum mode operations of the 8086. (R15-REG-JUNE-2017)

**13. Briefly explain the differences between minimum and maximum mode of
operation of 8086.(R13-SUP-JUNE-2016)

*14. How the multiplexed address bus in the 8086 separated into address bus and data
bus? Draw the diagram for the same. (R15-SUP-DEC-2017)

***15. Explain pin details of 8086.(R15-REG-JUNE-2017)

Unit-5

**1. Describe following instructions of 8086 with example:

(i) STOS. (ii) TEST. (iii) ROL. (iv) CMC.(R13-REG-DEC-2015)

***2. Describe following instructions of 8086 with examples:

(a) DEC. (b) CBW. (c) DAA. (d) LOOP. (R13-REG-DEC-2016)

***3. Explain the following instructions:

(i) AAM. (ii) DAA. (iii) CBW. (iv) LAHF/SAHF. (v) LDS. (R13-SUP-JUNE-2016)

**4. With an example describe the difference between jump and call instruction.
Explain the processor internal operation in executing them. (R13-SUP-JUNE-2016)
**5. Explain the instructions used to perform program execution transfer in 8086.

**6. What are the functions of the REP and REPE prefixes used with string instructions
in the 8086? Explain. (R15-SUP-DEC-2017)

*7. List the different steps performed by the 8086 when it executes the XLAT
instruction. What is the use of XLAT? (R15-SUP-DEC-2017)

*8. Discuss the function of the LOCK prefix used with an 8086 instruction.

***9. Explain about the following assembler directives: END P, EQU, EVEN, EXTRN
with examples. (R15-SUP-DEC-2018)

***10. Explain the purpose of following directives:

(i) ORG. (ii) EQU. (iii) ASSUME. (iv) MODEL. (v) DW.

***11. Explain the functions of the assembler directives PTR, TYPE, SHORT,
GLOBAL and LOCAL with examples for each. (R15-REG-JUNE-2017)

***12. What is an assembler directive? Write assembly language program for finding
largest number in an array. (R15-REG-JUNE-2019)

*13. 8 data bytes are stored in memory locations E000H to E007H. Write an assembly
language program for 8086 microprocessor to transfer the block of data to a new
location B001H to B008H. (R13-SUP-JUNE-2017)

*14. Write an assembly language program to convert an array of ASCII code to

corresponding binary (hex) value. The ASCII array is stored starting from 4200H.The
first element contains a number of elements in the array. (R15-REG-JUNE-2018)

*15. Write the differences between procedure and macro with an example. (R13-SUP-
JUNE-2016)

***16. With a neat sketch, explain the architecture of 8051. (R15-REG-JUNE-2019)

OR
With a neat sketch, explain the architecture of 8051. (R15-SUP-DEC-2018)

*17. Why microcontrollers are often called single chip computers? Explain. (R15-REG-
JUNE-2017)

***18. Describe about parallel ports and memory interfacing in 8051. (R15-REG-
JUNE-2019)
OR
Discuss in detail about parallel I/O ports in 8051 microcontroller and explain how these
ports are accessible for specific applications. (R15-SUP-DEC-2018)
**19. Explain memory organization of 8051 microcontroller in detail. (R13-REG-
DEC-2016)

*20. For the given ALP below determine the baud along with serial & timer modes set.
MOV SCON, #52H
MOV TMOD, #20H
MOV THI, F3H
SETB TRI ; start timer_(R13-SUP-JUNE-2016)

**21. Explain bit level instructions of 8051 microcontroller with appropriate examples
(R13-REG-DEC-2015)

*22. Write a program to arrange a block of binary numbers in ascending order. (R15-
REG-JUNE-2017)