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Lecture 8

This document discusses synchronous sequential logic circuits and state machines. It contains the following key points: 1) Clocked synchronous state machines use flip-flops with a common clock and have a number of states equal to 2 to the power of the number of flip-flops. Their next state and output depend on the current state and input. 2) Moore machines have their output depend only on the current state, while Mealy machines have their output depend on both the current state and input. 3) The state machine design procedure involves organizing specifications, minimizing states, assigning states to variables, choosing flip-flop types, and drawing the logic diagram.

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Osama Tahan
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19 views11 pages

Lecture 8

This document discusses synchronous sequential logic circuits and state machines. It contains the following key points: 1) Clocked synchronous state machines use flip-flops with a common clock and have a number of states equal to 2 to the power of the number of flip-flops. Their next state and output depend on the current state and input. 2) Moore machines have their output depend only on the current state, while Mealy machines have their output depend on both the current state and input. 3) The state machine design procedure involves organizing specifications, minimizing states, assigning states to variables, choosing flip-flop types, and drawing the logic diagram.

Uploaded by

Osama Tahan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DSDE 152

Digital System Design

Lecture 8: Synchronous
Sequential Logic Circuits
Spring 2021
Dr. Shawkat S. Khairullah
Department of Computer Engineering 1
University of Mosul
Clocked Synchronous State-Machines
• Such machines have the characteristics:
• Sequential circuits designed using flip-flops.
• All flip-flops use a common clock (clocked synchronous).
• A machine using n flip-flops (state memory) has n state variables (the
outputs of the flip-flops) and 2n states.
• In general, the next state and output of the machine both depend on
the current state of the machine and on the current input:
Next state = F(current state, input)
output = G(current state, input)
This type of state machine is called Mealy Machine
• In some cases the next output depends only on the current state and
not directly on the current input
•

Next state = F(current state, input)


output = G(current state) 2
Such machines are called Moore machines.
Clocked Synchronous State-Machine Model

External Input Bistable Output


excitation current state Combinational outputs
inputs Combinational
Memory
Logic Logic
devices
F G
clock

State memory:
Usually edge-triggered
clock
D or JK flip-flops

Moore Machine
3
Clocked Synchronous State-Machine Model

External Input Bistable Output


excitation current state Combinational outputs
inputs Combinational
Memory
Logic Logic
devices
F G
clock

State memory:
Usually edge-triggered
clock
D or JK flip-flops

Mealy machine 4
Clocked Synchronous State-Machine
Model

Moore outputs
External Input Bistable Output
excitation current state Combinational
inputs Combinational
Memory
Logic Logic
devices Mealy outputs
F G
clock

State memory:
Usually edge-triggered
clock
D or JK flip-flops

Moore & Mealy Machine (Mixed) 5


State Machine Design Procedure
Step1: Organize design specifications into a PS/NS table , state
diagram, ASM chart, flow map or timing diagram from word
description.
Step2: Minimize number of states (optional, can result fewer flip-
flops).
Step3: State Assignment: Choose state variables (one variable for
each flip-flop) and assign a unique code to each state.
Step 4:Choose flip-flop type (D, J-K, etc.)
• Build excitation table for flip-flop inputs from transition table.
• Derive excitation equations from excitation table.
• Derive output equations from PS/NS table.
Step 5: Draw logic diagram with excitation logic, output logic, and 6
state memory elements.
Excitation table
State transition Excitation inputs
PS (q) NS (Q) D T J K S R J K’
0 0 0 0 0 X 0 X 0 X
0 1 1 1 1 X 1 0 1 X
1 0 0 1 X 1 0 1 X 0
1 1 1 0 X 0 X 0 X 1

present state (PS) External next state (NS)


output Signal input signals output signal
q S R Q
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
7
1 0 1 0
1 1 0 1
1 1 1 0
Example 9-1/p511
• Design a Moore type synchronous state machine with three
external inputs X1,X2 and X3 and one output signal Z. The
output Z goes to 1 when X1.X2.X3=1 at the next system
timing event. The output Z stays at 1 as long as X3=0;
otherwise, the output goes to 0.
(a-) Obtain and ASM chart to represent the design.
(b-) Use a positive edge-triggered D flip-flop in the design.
Solution:-
First state: Z goes to 1 (0→1) if X1.X2.X3=1
Second state: Z stays at 1 (1→1) if X3=0 else Z goes to 0

8
Example 9-1/p511
0
a

y= state variable 0
X1.X2.X3
0 1

State a y=0 X1
1
1
State b y=1 0
X2
1
b
Z=Y
0
X3
Z
1

Q=Y=D
01
X3

Y  y.X1.X2.X3 Y=1 when y=0 AND X1.X2.X3=1 01

 (Set a→b)
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y.X3 Y=1 when y=1 AND X3=0
(Hold b→b)
Example 9-1/p511
X1
X2
X3
y
D Q Z

y
Q

clock

Circuit diagram

 (Set or Hold) method Used with D flip-flop only


 (clear or Hold) method
10
Thank you

11

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