ELECTRONIC DEVICES

LABORATORY MANUAL

B.E. (ECE) III - Semester, Academic Year : 2023-24

Course Code: U21PC311EC CIE Marks: 30 SEE Marks: 50 Credits: 1

DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING

VASAVI COLLEGE OF ENGINEERING (AUTONOMOUS)

ACCREDITED BY NAAC WITH 'A++' GRADE
IBRAHIMBAGH, HYDERABAD - 500 031
 VASAVI COLLEGE OF ENGINEERING (AUTONOMOUS)
ACCREDITED BY NAAC WITH 'A++' GRADE
Ibrahimbagh, Hyderabad – 500 031
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Institute Vision

Striving for a symbiosis of technological excellence and human values

Institute Mission

To arm young brains with competitive technology and nurture holistic

development of the individuals for a better tomorrow

Department Vision

Striving for excellence in teaching, training and research in the areas of

Electronics and Communication Engineering and fostering ethical values

Department Mission

To inculcate a spirit of scientific temper and analytical thinking and train

the students in contemporary technologies in Electronics and
Communication Engineering to meet the needs of the industry and society
with ethical values
 VASAVI COLLEGE OF ENGINEERING (AUTONOMOUS)
ACCREDITED BY NAAC WITH 'A++' GRADE
Ibrahimbagh, Hyderabad – 500 031
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

UG Program : B.E (ECE)

Program Educational Objectives (PEO’s)

PEO1: Graduates will be able to identify, analyze and solve engineering problems.

PEO2: Graduates will be able to succeed in their careers, higher education and
research.

PEO3: Graduates will be able to excel individually and in multidisciplinary teams

to solve industry and societal problems.

PEO4: Graduates will be able to exhibit leadership qualities and lifelong learning
skills with ethical values.

Program Specific Outcomes (PSO’s)

PSO1: ECE students will be able to analyze and offer circuit and system level
solutions for complex electronics engineering problems, keeping in mind
the latest technological trends.

PSO2: ECE students will be able to apply the acquired knowledge and skills in
modeling and simulation of wireless communication systems.

PSO3: ECE students will be able to implement signal and image processing techniques
for real time applications.
 VASAVI COLLEGE OF ENGINEERING (AUTONOMOUS)
ACCREDITED BY NAAC WITH 'A++' GRADE
Ibrahimbagh, Hyderabad – 500 031
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
B.E. (ECE) PROGRAM OUTCOMES (PO’s)
PO1 Engineering Knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals and an engineering specialization to the solution of complex engineering
problems.
PO2 Problem Analysis: Identify, formulate, review research literature and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences and engineering sciences.
PO3 Design / development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety and the cultural, societal and environmental
considerations.
PO4 Conduct investigations of complex problems: Use research based knowledge and research
methods including design of experiments, analysis and interpretation of data and synthesis of
the information to provide valid conclusions.
PO5 Modern tool usage: Create, select and apply appropriate techniques, resources and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
PO6 The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant
to the professional engineering practice.
PO7 Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts and demonstrate the knowledge of and
need for sustainable development.
PO8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO9 Individual and team work: Function effectively as an individual and as a member or leader
in diverse teams and in multidisciplinary settings.
PO10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, give and
receive clear instructions.
PO11 Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
PO12 Lifelong learning: Recognize the need, and for have the preparation and ability to engage
in independent and lifelong learning in the broadest context of technological change.
 VASAVI COLLEGE OF ENGINEERING (AUTONOMOUS)
Ibrahimbagh, Hyderabad – 500 031.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Electronic Devices Lab

L:T:P (Hrs./week) : 0:0:2 SEE Marks : 50 Course Code: U21PC311EC
Credits : 1 CIE Marks : 30 Duration of SEE : 3 Hours

Cycle - I Experiments
1. Zener Diode Characteristics and Zener as Voltage Regulator.
2. Common Base characteristics of BJT and measurement of h - parameters.
3. Common Emitter characteristics of BJT and measurement of h – parameters.
4. MOSFET Characteristics and measurement of its small signal parameters.
5. CMOS invertor Transfer characteristics with different capacitive loads.
6. Diode Clipper circuits.
7. Clamper circuits.
8. Design of Half wave and Full wave Rectifiers with and without Filters

Cycle - II Experiments
(Using Cadence Tools)

9. Plotting MOSFET I V Characteristics

10. DC & transient analysis of CMOS Inverter
11. DC & transient analysis of FinFET Inverter

Learning Resources
1. “LAB MANUAL”, Department of ECE, Vasavi College Of Engineering.
2. Paul B Zbar and Alber P Malvino, Michael A Miller, “Basic Electronics: A Text Lab Manual”, 7th edition,
Tata McGraw Hill, 2009.
3. David A Bell, “Laboratory Manual for Electronic Devices and Circuits”, 4th edition, PHI, 2001.
4. https://community.cadence.com/cadence_technology_forums/ Cadence Community

Tools:
1. Multisim/Cadence may be used to facilitate analysis of characteristics of devices.
2. Cadence tool can be used to do analysis on CMOS & FinFET
 VASAVI COLLEGE OF ENGINEERING (AUTONOMOUS)
ACCREDITED BY NAAC WITH 'A++' GRADE
Ibrahimbagh, Hyderabad – 500 031
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ELECTRONIC DEVICES LABORATORY

L:T:P (Hrs./week) : 0:0:2 SEE Marks : 50 Course Code: U21PC311EC
Credits : 1 CIE Marks : 30 Duration of SEE : 2 Hours

S.No Page
Name of The Experiment
No
1 Zener Diode Characteristics and Zener as Voltage Regulator
2 Common Base characteristics of BJT and measurement of h - parameters.
3 Common Emitter characteristics of BJT and measurement of h – parameters.
4 MOSFET Characteristics and measurement of its small signal parameters.
5 CMOS invertor Transfer characteristics with different capacitive loads.

6 Diode Clipper circuits.

7 Clamper circuits.
8 Design of Half wave and Full wave Rectifiers with and without Filters
9 Plotting MOSFET I V Characteristics
10 DC & transient analysis of CMOS Inverter
11 DC & transient analysis of FinFET Inverter
 VASAVI COLLEGE OF ENGINEERING (AUTONOMOUS)
ACCREDITED BY NAAC WITH 'A++' GRADE
Ibrahimbagh, Hyderabad – 500 031
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Name of the Course : Electronic Devices Laboratory SEE Marks : 50 Course Code: U21PC311EC

Academic Year: 2022-23 Semester : III CIE Marks : 30 Credits : 1

Course Outcomes
On completion of the course, students will be able to
CO1 Plot the characteristics of electronic devices to understand their
behaviour
CO2 Employ Diode as a circuit element to get a given output response.
CO3 Operate electronic test equipment and hardware/software tools to
characterize the behaviour of electronic devices.
CO4 Analyze the various device parameters effect on device
characteristics
CO5 Comparative analysis of MOSFET and FinFET using cadence tool.

CO-PO Mapping CO-PSO Mapping

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
3 1 1 1 2 2 2
CO1

3 1 1 1 2 2 2
CO2

3 1 1 1 2 2 2
CO3

3 1 1 1 2 2 2
CO4

3 1 1 1 3 2 2
CO5
 1. ZENER DIODE CHARACTERISTICS AND ZENER AS VOLTAGE
REGULATOR

(a) CHARACTERISTICS OF ZENER DIODE

Brief account of zener diode: Diodes designed with adequate power dissipation capabilities to
operate in the breakdown region are known as zener diodes. Zener diode is heavily doped than
the ordinary diode. The operation of zener diode is same as that of ordinary PN diode under
forward biased condition. The minimum voltage at which the device would conduct in the
forward bias mode is known as ‘cut in voltage’, where as in a reverse biased condition
breakdown of the junction occurs.

When P&N regions are heavily doped, direct rupture of covalent bonds takes place
because of the strong electric field and electron hole pairs so created increases the reverse
current in a reverse biased diode. The increase in current takes place at a constant value of
voltage called breakdown voltage. This depends upon the amount of doping. Zener diode
can be used as voltage regulator under reverse biased condition.

AIM:

1. To determine the forward & reverse characteristics of Zener diode.

2. From the graph to determine the break down voltage, static and
dynamic resistances. (Forward and reverse)

APPARATUS:

D.C. source (0-30) V 1No

Ammeter (0-20) mA 1No
Voltmeter (0-1) V, (0-20) V 1No
Variable resistance box 1No
Zener diode (1N4735, 1N4739) 1No
Resistor (1KΩ) 1No

1
CIRCUIT DIAGRAM:

Figure 1: FORWARD BIAS

Figure 2: REVERSE BIAS

PROCEDURE:

FORWARD BIAS

1. Connect the circuit as shown in figure 1.

2. Change the supply voltage from 0 to 30V in steps of 0.2v and note down the
Voltage and current.
3. Change the forward biased voltage (Vi) and note down the corresponding
Voltage (VD) and current (ID).

4. Plot the graph VD verses ID.

2
REVERSE BIAS

1. Connect the circuit as shown in figure 2.

2. Change the supply voltage from 0 to 30V in steps of 2v and note down the
Voltage and current.
3. Plot the reverse characteristics VD verses ID.
From the graph determine the breakdown voltage of the diode.

EXPECTED GRAPH:

Figure: V-I CHARACTERISTICS OF ZENER DIODE IN FORWARD AND

REVERSE BIAS

OBSERVATIONS:

FORWARD CHARACTERISTICS:

Table (I):

Supply Voltage VD (V) Current ID (mA)

Voltage(V)

3
REVERSE CHARACTERISTICS:

Table (II):

Supply Voltage VD (V) Current ID (mA)

Voltage(V)

RESULT:

1. The Forward and reverse characteristics of the Zener diode have been plotted.
2. The breakdown voltage VZ =
Static resistance
3. Forward resistance =

4. Reverse Resistance =
Dynamic resistance
5. Forward =
6. Reverse =

4
(b) ZENER DIODE AS VOLTAGE REGULATOR
Brief account of voltage regulator:
Line regulation is the capability to maintain a constant output voltage level and the output
channel of the power supply dissipate changes to the input voltage level. To obtain this zener
diode is connected in parallel to the load and operated in reverse biased condition. This is
because in the breakdown region, large changes in diode current produce only small changes
in diode voltage.
Load regulation is the capability to maintain a constant voltage level on the output channel
of a power supply dissipate changes if the supplies load (such as change in resistance) value
connected across the supply voltage.

AIM:

To determine the line and load regulation for a given Zener diode.

APPARATUS:

D.C. Source (0-30) V 1No.

Ammeter (0-30) mA 1No.
Volt meter (0-20) V 1No.
Decade Resistance Box 1No.
Zener diode (1N4735, 1N4739) 1No.
Resistor (1KΩ) 1No.

Connecting wires as per required

5
CIRCUIT DIAGRAM:

Figure 3: LINE AND LOAD REGULATION

PROCEDURE:

LINE REGULATION:

1. Connect the circuit as shown in figure 3.

2. The zener diode is used under reverse biased condition.

3. The reverse bias voltage VI should be greater than the breakdown voltage. To
maintain this keep the load resistance RL constant at 5K.

4. Vary VI in steps of 2V from the breakdown voltage and note down the corresponding
total current (IT) and the load current (IL).

5. Determine IZ, zener current (IT - IL).

6. Plot Vi Vs V0 to get the line regulation characteristics.

6
LOAD REGULATION:

1. Connect the circuit as shown in figure 3.

2. Adjust VI to slightly greater than the breakdown voltage and keep it constant.

3. Vary the load resistance R L such that current varies in steps of 1mA up to 10mA.

4. Note down the corresponding total current (IT) and load current (IL)

5. Determine IZ, zener current (IT - IL).

6. Plot IL Vs VO to obtain the load regulation characteristics.

EXPECTED GRAPHS:

Figure: Line regulation Figure: Load regulation

7
OBSERVATIONS:

LINE REGULATION:

Table (I):

Supply Voltage IT (mA) IL (mA) Iz(mA)=IT - IL Output

(Vin) Voltage(Vo)

LOAD REGULATION:

Table (II):

Supply Voltage IT (mA) IL (mA) Iz (mA)=IT--IL Output

(Vin) Voltage(Vo)

RESULT:

1. The breakdown voltage Vz =----------------------

2. Static resistance:

i. Forward resistance: Rf = Vf/If=

ii. Reverse resistance: R r = Vr/Ir=

8
PRE LAB QUESTIONS:
1. Explain the phenomenon of Zener breakdown & avalanche breakdown?
2. Compare the characteristics of zener diode with ordinary PN diodes both forward and
reverse biased conditions?
3. Explain how a zener diode acts as a voltage regulator for line and load regulations?
4. Why do you use an ammeter in micro-amps range when a diode is used in reverse
bias?
5. In what region of the characteristics you prefer to use a zener diode? Find out
Iz (min) and Iz( max) for the given configuration?
6. Explain the voltage stabilization with load in zener voltage regulator?
7. Mention applications and specifications of a zener diode?

8. List the drawbacks of zener regulators.

9
 2. COMMON BASE CHARACTERISTICS OF BJT AND
MEASUREMENT OF h-PARAMETERS

Brief account of CB configuration: A transistor is a three terminal device. A transistor

consist of a layer of p-type material sandwiched between two layers of n-type materials. The
three portions of a transistor are emitter, base and collector. The arrow on the emitter lead
specifies the direction of current flow.

In common base(CB) configuration, the base is common to both input(emitter) and

output(collector).For normal operation emitter base junction is forward biased and collector
base junction is reverse biased. In PNP CB configuration, IE is +ve, IC is –ve and IB is –ve.
So,

VEB = F1 (VCB, IE) and

IC = F2 (VEB,IB)
With an increasing the reverse collector voltage, the space-charge width at the output
junction increases and the effective base width decreases. This phenomenon is

known as “Early effect”. Then, there will be less chance for recombination within the
base region. With increase of charge gradient with in the base region, the current of
minority carriers injected across the emitter junction increases. The current amplification
factor of CB configuration is given by,

α = ∆IC/ ∆IE
Input Resistance, Ri = ∆VEB /∆IE at Constant VCB
Output Resistance, Ro = ∆VCB /∆IC at Constant IE

AIM:

To determine input and output characteristics and h-parameters of BJT in Common

Base configuration.

APPARATUS:

10
 PNP transistor (BC 557/558) 1No
Dual regulated power supply (0-30) V 1No

Voltmeter (0-1) V 1No

Ammeter (0-20) mA 2No’s
Resistors (4.7KΩ, 1KΩ) each one
Connecting wires as per required.

CIRCUIT DIAGRAM:

Figure 1: COMMON BASE CONFIGURATION

PROCEDURE FOR COMMON BASE:

INPUT CHARACTERISTICS:

1. Connect the circuit as shown in the figure 1.

2. Keep VCB (output voltage) constant. (2 volt)
3. Vary VEE in steps and note down the corresponding VEB & IE.
4. Change the value of VCB and repeat the step 3 to get a set of characteristics.
5. Plot IE Vs VEB for different VCB values.

OUTPUT CHARACTERISTICS:

11
 1. Connect the circuit as shown in the figure 1

2. The input current IE is kept constant (say 2mA) by adjusting VEE.

3. Vary VCB in steps and note down the corresponding IC.
4. Change the value of IE and for different values repeat step2.
5. Plot VCB Vs IC for different IE values.

EXPECTED GRAPHS:

Figure: INPUT CHARACTERISTICS

Figure: OUTPUT CHARACTERISTICS:

OBSERVATIONS:

12
Table(I):

INPUT CHARACTERISTICS:

S.NO. VCB = 2V VCB = 4V VCB = 6V

VEB (V) IE (mA) VEB (V) IE (mA) VEB (V) IE (mA)

Table(II)

OUTPUT CHARACTERISTICS:

S.NO. IE = 2mA IE = 4mA IE = 6mA

VCB (V) IC (mA) VCB (V) IC (mA) VCB (V) IC (mA)

CB CONFIGURATION:

13
 IE = Input current (Emitter current)

IC = Output current (collector current)

VEB = Input voltage (emitter to base voltage)

VCB = Output voltage (collector to base voltage)

PRECAUTIONS:

1. The supply voltages should not exceed the rating of the transistor.

2. Meters should be connected properly according to their polarities.

RESULT:

PRE LAB QUESTIONS:

1. Compare the input resistance, output resistance, voltage gain, current gain of different
transistor configurations
2. What is Early –effect / base width modulation in transistors?
3. Why the input characteristics of transistor in CB-configurations originate from the
origin?
4. Explain the three different regions, Active, saturation and cut off, in the output
characteristics.
5. A CB – stage is generally used as the first stage in a cascade. Why?
6. What is meant by common base configuration?
7. Define current gain in CB configuration.
8. Give the Ebers Moll representation of a NPN Transistor?

14
 3. CHARACTERISTICS OF COMMON EMITTER BJT AND
MEASUREMENT OF h-PARAMETERS

Brief account of common emitter (CE) configuration: A transistor is a three terminal device.
A transistor consists of a layer of n-type material sandwiched between two layers of n-type
material. The three portions of a transistor are emitter, base and collector. The arrow on the
emitter lead specifies the direction of current flow.

In this configuration emitter is common to both input (base) and output(collector) is known as
‘common emitter configuration’. Emitter base junction is forward biased and base collector
junction is reverse biased. The input characteristics are essentially that of forward
characteristics of PN diode. In general increase in VCE, with constant VBE causes a decrease
in base current. The plot of IC against VCE gives the information about output characteristics
of BJT. For a constant IB, the current increase as the voltage increase till it reaches saturation.
The characteristics made up of three regions: cutoff, active and saturation regions. At saturation
the VCE is almost zero & very high current flows. At cutoff the output current will be zero &
at the active region IC increases linearly with VCE .

(a)CHARACTERISTICS OF COMMON EMITTER

AIM:

To determine input and output characteristics of BJT in CE configuration and to

measure h-parameters.

APPARATUS:

NPN transistor (BC 547) 1No

Dual regulated power supply (0-30) V 1No

Voltmeter (0-1) V 1No

Ammeter (0-2000) µA (0-20) mA each one

Resistors (47KΩ, 1KΩ) each one

Connecting wires as per required.

15
CIRCUIT DIAGRAM:

Figure 1: COMMON EMITTER

PROCEDURE:

INPUT CHARACTERISTICS:

1. Connect the circuit diagram as shown in figure 1.

2. Keep VCE, the output voltage constant (say 2V).
3. Vary VBB in steps and note down the corresponding VBE & IB.
4. For different constant values connect the circuit.
5. Now to observe the input characteristics the output voltage VCE kept to be zero and
the value of input source VBB in varied. Such that the current IB increases in steps of
50A. The respective values for VBE are noted. The same procedure is repeated
keeping VCE at 10V, graph IB Vs VBE is drawn and the h parameters calculated.

16
OUTPUT CHARACTERISTICS:

1. The voltage source VCE is varied keeping VBB and IB constant, keep IB at around
20A and vary the output voltage VCE in steps of 0.1V to 1V and after that increase
VCE in steps of 1V to 12V note down the current Ic.
2. Repeat the experiment for 30A and 40A values of IB. The h parameters can be
calculated from the graph.

EXPECTED GRAPHS:

Figure: INPUT CHARACTERISTICS

Figure: OUTPUT CHARACTERISTICS

17
OBSERVATIONS:

Table(I):

INPUT CHARACTERISTICS

VBB(V) VCE = 1 V VCE = 2 V VCE = 3 V

VBE(V) IB (A) VBE (V) IB(A) VBE (V) IB(A)

Table(II):

OUTPUT CHARACTERISTICS

IB = 10 A IB = 20 A IB = 30 A
VCC(V)
VCE(V) IC (mA) VCE(V) IC (mA) VCE(V) IC (mA)

18
h-parameters calculation:
Input Impedance hie = ΔVBE / ΔIB at VCE constant
Output admittance hoe = ΔIC /ΔVCE at IB constant

Reverse Transfer Voltage Gain hre = ΔVBE / ΔVCE at IB constant

Forward Transfer Current Gain hfe = ΔIC / ΔIB at constant VCE

RESULT:

PARAMETERS VALUE DETERMINED

hie

hre

h fe

ho e

PRE LAB QUESTIONS:

1. CE stages are used as middle stages in a cascade why?

2. What is the phase relation between the input and output in a CE amplifier?
3. Mention advantages and disadvantages of CE configuration over CB & CC?
4. Explain why CE configuration is most popular in Amplifier circuits.
5. Show the Transistor current components for a forward biased emitter junction and
reverse biased collector junction?
6. Explain the terms ICBO, ICEO and VEBO ?
7. Can we interchange the collector and emitter terminals in a transistor?
8. What are typical h-parameter values for a transistor in CE configuration?
9. Why Hybrid parameters are called so?
10. Define the h-parameters?
11. What are the salient features of hybrid parameters?

19
 4. CHARACTERISTICS OF MOSFET IN CS CONFIGURATION AND
MEASUREMENT OF ITS SMALL SIGNAL PARAMETERS
AIM:

To obtain the drain characteristics and transfer characteristics of the given N-channel MOSFET
in CS configuration & to Determine Drain resistance (rd), Trans Conductance
(gm),&Amplification factor ()
APPARATUS:

Resistor (1k) 1 No

MOSJFET Transistor (2N7000) 1 No.

DC Power Supply (0-30) V 2 No’s

DC Ammeter (0-30) mA 1 No

DC Voltmeter (0-15) V 1 No

Resistor (100Kohms) 1 No

Brief account of MOSFET: MOSFET I-V Characteristics A metal-oxide-semiconductor field-

effect transistor (MOSFET) is a three-terminal device that can be used as a switch (e.g. in
digital circuits) or as an amplifier (e.g. in analog circuits). The three terminals are referred to as
the Source, Gate, and Drain terminals. The MOSFET also has a Body terminal, which is usually
tied to the source terminal (so that VBS = 0 volts) in discrete transistors. Current flow between
the source and drain terminals is controlled by the voltage VGS applied between the gate and
source terminals. If the gate-to-source voltage VGS is less than the threshold voltage value VT
(e.g. ~2 Volts, for the transistors which you will be using in this lab), no current can flow
between the source and the drain – i.e. the transistor is OFF; if VGS > VT, then current can
flow between the source and the drain – i.e. the transistor is ON. The circuit symbol for an n-
channel enhancement-mode (VT > 0 Volts) MOSFET is shown in Figure 1, along with the
terminal current reference directions. IG G D S ID IS B Figure 1 Circuit symbol for n- channel
enhancement MOSFET

20
CIRCUIT DIAGRAM:

Figure 1: COMMON SOURCE CONFIGURATION

PROCEDURE:

DRAIN CHARACTERISTICS:

5. Note the type no. of MOSFET connected to the experimental board and trace the
circuit and connect as shown in figure 1.
6. Make the circuit connections as shown in fig. Use milli-ammeter and electronic voltmeter
of suitable ranges.
7. For drain characteristics fix Vgs at some value, say 0 V. Increase the Vdd slowly in
steps and note down the Vds and Id for each value of Vdd. Now change Vgs to another
value (say –1V, –2V, –3V) and repeat the above.
8. Plot the drain characteristics on the graph (between Id and Vds for fixed values of Vgs).

21
TRANSFER CHARACTERISTICS:

5. Connect the circuit as shown in figure 1.

6. Fix Vds at 4V. Increase the Vgg slowly in steps and note down Vgs and Id for each set
of Vds. Now change the Vds to another value, say 3V and repeat the above.
7. Plot the transfer characteristic on the graph (between Id and Vgs for fixed values of Vds).
8. Determine the drain resistance, Trans conductance and amplification factor from the
above curves.

EXPECTED GRAPHS:

Figure: TRANSFER CHARACTERISTICS & DRAIN CHARACTERISTICS

OBSERVATIONS:

22
Table(I):

DRAIN CHARACTERISTICS:

Vgs = 1.7V Vgs = 1.8 V Vgs = 1.9 V

Vds (V) Id (mA) Vds (V) Id (mA) Vds (V) Id (mA)

Table(II):

TRANSFER CHARACTERISTICS:

Vds = 5V Vds = 7V Vds = 9V

Vgs (V) Id (mA) Vgs (V) Id (mA) Vgs (V) Id (mA)

CALCULATIONS:

4. Drain resistance rd = ∆Vds / ∆Id = K Ohms, where Vgs is constant

5. Trans conductance, gm = ∆Id / ∆Vgs = Ohms, where Vds is constant.
6. Amplification factor, μ = rdXgm = ∆Vds / ∆Vgs where Id is constant.

RESULT:

PRELAB QUESTIONS:

1. Name the different regions in case of transfer-mutual characteristics of MOSFET.

2. What is threshold voltage in MOSFET?

23
 5.CMOS Invertor Transfer Characteristics

5.CMOS Invertor Transfer Characteristics

Making inverters with the CD4007 transistor array

Below in figure 1 is the schematic and pinout for the CD4007:

Figure 1 CD4007 CMOS transistor array pinout

As many as three individual inverters can be built from one CD4007 package. The simplest first
one to configure as shown below is by connecting pins 8 and 13 together as the inverter output.
Pin 6 will be the input. Be sure to connect pin 14 VDD to power and pin 7 VSS to ground.

Figure 2 Three Inverters

The second Inverter is made by connecting pin 2 to VDD, pin 4 to VSS, pins 1 and 5 are
connected together as the output and with pin 3 as the input. The third inverter is made by
connecting pin 11 to VDD, pin 9 to VSS, pin 12 is the output and pin 10 is the input.

24
Characterizing The CMOS Inverter
There are a number of both static (DC) and dynamic (AC) performance characteristics of the
CMOS inverter that are often specified and should be measured. In this section we will measure
a number of them for the inverter but these same measurements can be made on other the types
gates we will see in later sections of this activity. We will start with the static characteristics,
threshold voltage, transition region width, output source and sink current.

Threshold voltage :
Generally the CMOS fabrication process is designed such that the threshold voltage, VTH, of the
NMOS and PMOS devices are roughly equal i.e. complementary. The designer of the inverter
then adjusts the width to length ratio, W/L, of the NMOS and PMOS devices such that their
respective transconductance is also equal.

Directions:

On your solder-less breadboard build the first inverter shown in figure 2 to test the input to
output switching characteristics of the CMOS inverter. The green boxes in figure 3 indicate the
required connections to the connector on ADALM2000. Connect Vp (+5V) power to VDD (pin
14) through a 100Ω resistor to measure the supply current and ground to VSS (pin 7). Connect
the output of the waveform generator to the inverter input (pin 6) along with scope input 1+ and
connect the inverter output (pins 8,13) to scope input 2+. It is also generally good to ground the
unused negative scope inputs (1- , 2-).

Figure 3 Setup to measure input threshold and transition region

Hardware Setup :
Configure the waveform generator for a 100 Hz triangle wave with 5V amplitude peak-to-peak
and 2.5V offset. Both scope channels should be set to 1V/Div. Configure the scope in XY mode

25
with channel 1 on the horizontal axis and channel 2 on the vertical axis.

Figure 4 Breadboard connections Setup to measure input threshold and transition region

Procedure :
First using scope channel 2 to measure the inverter output voltage vs. the input as the input is
swept from 0 to 5V obtain a plot like the top curve in figure 5. Export the data to a .csv file and
extract the width of the transition region and the threshold voltage at the input at the point
where the output voltage is exactly 1/2 VDD.

Next move the channel 2 scope inputs 2+ and 2- to measure the voltage across the 100Ω
resistor, R1, in figure 3. You may need to adjust the vertical scale of channel 2 for an optimal
view of the current waveform. Now obtain a plot of I D vs. the input as the input is swept from 0
to 5V. This should give you a plot much like the bottom curve in figure 5. Export the data to a
.csv file and extract the peak current ( measured voltage divided by the 100Ω resistor value) and
the input and output voltages where the peak occurred.

26
 Figure 5 Inverter output voltage and supply current curves vs. input voltage

Figure 6 Scopy screenshots: Inverter output voltage and supply current curves vs. input voltage

The input to output transfer characteristic plots the output voltage VOUT versus the input
voltage VIN. Notice that when the input voltage increase from 0V to 5V the output voltage
decreases from 5V to 0V. The supply current characteristic plots the current flowing through
the transistors between VDD and ground also versus the input voltage VIN. The fact that there are
two parts of the characteristic curves when the input voltage is near ground and VDD, no current
flows between VDD and ground, is very attractive because there is no power dissipation at this

27
stages. This very fact is the reason that today nearly all digital circuitry is now build using
CMOS technology.

The width of the transition region as a fraction of the power supply leads to a performance
measure that is often referred to as the noise margin, the part of the input range where the
output remains at a constant high or low level. Given that there is likely to be noise
superimposed on the input signal it is desirable to have the output not respond to small changes
in the input. A narrow transition region also potentially reduces the amount of time the output
spends transitioning between states and thus the so called “shoot through” current when both
the NMOS and PMOS transistors are partially turned on.

Dynamic performance

In this section we will investigate the dynamic properties of the CMOS inverter, that is, its
behavior during the time when switching the input signal from low-to-high or high-to-low
voltages and the associated power dissipation.

We now consider a CMOS inverter driven by a voltage pulse. Typical input/output waveforms
are shown in figure 5. Delay characterization of the dynamic behavior of an inverter is given by
two propagation delay times, THL and TLH as illustrated in figure 7. Note that these propagation
times are specified with respect to the mid supply voltage VDD/2.

Figure 7 CMOS Inverter propagation delay

28
 Figure 8 CMOS Inverter rise / fall time

Hardware Setup :
Now configure the waveform generator for a 500 KHz square wave with 5V amplitude peak-to-
peak and 2.5V offset. Be sure to reconnect scope channel 2 to measure the output voltage
waveform. Both scope channels should be set to 1V/Div. Adjust the horizontal scale so that you
can view both the rising and falling edges of the input and output waveforms similar to what is
shown in figures 7 and 8.

Figure 9 CMOS inverter Breadboard connections

29
 Figure 10 Scopy screenshot: CMOS Inverter propagation delay

Measurements:

Propagation delay, THL and TLH = time between input transition (when VIN = VDD/2) and output
transition (when VOUT = VDD/2). Rise time, TR = time for a waveform to rise from 10% to 90%
of its steady state value. Fall time, TF = time for a waveform to fall from 90% to 10% of its
steady state value.

30
 6. DESIGN OF HALF-WAVE AND FULL WAVE RECTIFIERS WITH
AND WITHOUT FILTERS
Brief account of half wave rectifiers:

In Half Wave Rectification, When AC supply is applied at the input, only Positive Half Cycle
appears across the load whereas, the negative Half Cycle is suppressed. This can be explained
is as follows:

During positive half-cycle of the input voltage, the diode D1 is in forward bias and conducts
through the load resistor RL. Hence the current produces an output voltage across the load
resistor RL, which has the same shape as the +ve half cycle of the input voltage.
During the negative half-cycle of the input voltage, the diode is reverse biased and there is no
current through the circuit. i.e., the voltage across R L is zero. The net result is that only the
+ve half cycle of the input voltage appears across the load. The average value of the half
wave rectified o/p voltage is the value measured on dc voltmeter.
For practical circuits, transformer coupling is usually provided for two reasons.

1. The voltage can be stepped-up or stepped-down, as needed.

2. The ac source is electrically isolated from the rectifier. Thus preventing shock hazards in
the secondary circuit.

The maximum efficiency of the Half Wave Rectifier is 40.6%

To remove the AC components or filter them out in a rectifier circuit, a filter circuit is used.
A filter circuit is a device to remove the AC components of the rectified output, but allows
the DC components to reach the load. A filter circuit is in general a combination of inductor (L)
and Capacitor (C) called LC filter circuit. A capacitor allows A.C only and inductor allows
D.C only to pass. So a suitable L and C network can effectively filter out the A.C component
from rectified wave.

A filter circuit consists of passive circuit elements i.e, inductors, capacitors, resistors and
their combination. The filter action depends upon the electrical properties of passive circuit
elements. For example, an inductor allows the D.C to pass through it. But it blocks A.C. On
the other hand, a capacitor allows the A.C to pass through it. But it blocks the D.C. Some of
the important filters are given below
. Inductor Filter
31
 2. Capacitor Filter
3. LC Filter
4. π Filter

AIM:

To measure the ripple factor of half wave rectifier without filter and with filters.

APPARTUS REQUIRED:

AC Voltmeter (0-20) V 1 No. DC

Voltmeter (0-20)V 1 No. DC
Ammeter (0-100) mA 1 No. Diodes
(1N4007) 2 Nos Transformer
(Step down) 1 No. Capacitors 100

F 2 Nos DRB (Decade

Resistance box) 1 No. Inductors

2Nos

CIRCUIT DIAGRAM:

Figure 1: HALFWAVE RECTIFIER (WITHOUT FILTER)

PROCEDURE:

32
HALF WAVE RECTIFIER (WITHOUT FILTER)

1. Connect the circuit as shown in figure 1, with S1 open keep RL in maximum position.
2. Tabulate Vdc , Vac by varying the IL in steps of 5mA (The change of RL causes the
change of IL)
3. Observe the rectified output on CRO. Calculate ripple factor & compare with
theoretical value.

OBSERVATIONS:

Table(I)

S.NO. RL IL Vac Vdc Ripple Theoretical

(Volts) (Volts) Factor Ripple
(Ohms) (mA)
= Vac/Vdc Factor

EXPECTED GRAPHS:

Figure: HALF WAVE RECTIFIER (WITHOUT FILTER)

33
CIRCUIT DIAGRAM:

Figure 2: HALFWAVE RECTIFIER WITH (C) FILTER

PROCEDURE:

1. Connect the circuit as shown in figure 2, keep RL in maximum position.

2. Tabulate Vdc , Vac by varying the IL in steps of 5mA (The change of RL causes the
change of IL)
3. Observe the rectified output on CRO. Calculate ripple factor & compare with
theoretical value.

OBSERVATIONS:

Table (II)

S.NO. RL IL Vac Vdc Ripple Theoretical

(Volts) (Volts) Factor Ripple
(Ohms) (mA)
= Vac/Vdc Factor

34
CIRCUIT DIAGRAM:

Figure 2: HALFWAVE RECTIFIER WITH (LC) FILTER

PROCEDURE:

4. Connect the circuit as shown in figure 2, keep RL in maximum position.

5. Tabulate Vdc , Vac by varying the IL in steps of 5mA (The change of RL causes the
change of IL)
6. Observe the rectified output on CRO. Calculate ripple factor & compare with
theoretical value.

CIRCUIT DIAGRAM:

Figure 3: HALF WAVE RECTIFIER WITH (π) SECTION FILTER

35
PROCEDURE (WITH FILTER):
1. Connect the circuit as shown in figure.
2. Tabulate Vdc , Vac by varying the IL in steps of 5mA (The change of RL causes the
change of IL)
3. Observe the rectified output on CRO. Calculate ripple factor & compare with
theoretical value.

PRECAUTIONS:

1. The primary and secondary side of the transformer should be carefully identified
2. The polarities of all the diodes should be carefully identified.

RESULT:

Brief account of full-wave rectifiers: The AC input is applied through the transformer, the
anode of the two diodes D1 & D2 (having similar characteristics) are connected to the opposite
ends of the centre tapped secondary winding and two cathodes are connected to each other and
are connected also through the load resistance RL and back to the centre of the transformer.

When the top of the transformer secondary winding is positive(+ve),say during the first half-
cycle of the supply, the anode of diode D1 is positive(+ve) w.r.t cathode, and and anode of
diode D2 is negative(-ve)w.r.t cathode. Thus only diode D1 conducts ,being forward biased and
current flows from cathode to anode of diode D1,through load resistance RL and top half the
transformer secondary making cathode end of load resistance RL positive. During the second
half-cycleof the input voltage the polarity is reversed, making the bottom thus diode D2 is
forward biased and and D1 is reverse biased. Consequently during this half-cycle of the

Input only the diode D2 conducts and current flows through the load resistance RL and
bottom of the transformer secondary making the cathode end of the load resistance RL positive.
Thus the direction of flow of current through the load resistance RL remains the same
during both halves of the input supply voltage.

To remove the AC components or filter them out in a rectifier circuit, a filter circuit is used.
A filter circuit is a device to remove the A.C components of the rectified output, but allows
the D.C components to reach the load. A filter circuit is in general a combination of inductor
(L) and Capacitor (C) called LC filter circuit. A capacitor allows A.C only and inductor

36
allows D.C only to pass. So a suitable L and C network can effectively filter out the A.C
component from rectified wave.

A filter circuit consists of passive circuit elements i.e, inductors, capacitors, resistors and
their combination. The filter action depends upon the electrical properties of passive circuit
elements. For example, an inductor allows the D.C to pass through it. But it blocks A.C. On the
other hand, a capacitor allows the A.C to pass through it. But it blocks the D.C. Some of the
important filters are given below.

1. Inductor Filter
2. Capacitor Filter
3. LC Filter
4. π Filter

AIM:

To verify the ripple factor of full wave rectifier without filter and with filters .

APPARTUS REQUIRED:

AC Voltmeter (0-20) V 1 No.

DC Voltmeter (0-20) V 1 No.
DC Ammeter (0-100) 1 No.
Diodes (1N4007) 2 Nos
Transformer (Step down) 1 No.

Capacitors 100 F 2 Nos

Inductors 2Nos
DRB (Decade Resistance box) 1 No.

CIRCUIT DIAGRAM:
37
 Figure 1: FULLWAVE RECTIFIER (WITHOUT FILTER)

PROCEDURE:

FULL WAVE RECTIFIER (WITHOUT FILTER)

1. Connect the circuit as shown in figure 1, with S1 closed keep RL in maximum

position.
2. Tabulate Vdc, Vac by varying the IL in steps of 5mA (The change of R L causes the
change of IL)
3. Observe the rectified output on CRO. Calculate ripple factor & compare with
theoretical value

OBSERVATIONS:

Table(III)

S.NO. RL IL Vac Vdc Ripple Theoretical

(Volts) (Volts) Factor Ripple
(Ohms) (mA)
= Vac/Vdc Factor

38
CIRCUIT DIAGRAM:

Figure 2: FULLWAVE RECTIFIER WITH (C) FILTER

PROCEDURE:

FULL WAVE RECTIFIER (WITH FILTER)

1. Connect the circuit as shown in figures 2 & 3..

2. Tabulate Vdc, Vac by varying the IL in steps of 5mA (The change of R L causes
the change of IL)
3. Observe the rectified output on CRO. Calculate ripple factor & compare
with theoretical value

OBSERVATIONS:

Table (IV)

S.NO. RL IL Vac Vdc Ripple Theoretical

(Volts) (Volts) Factor Ripple
(Ohms) (mA)
= Vac/Vdc Factor

CIRCUIT DIAGRAM:
39
 Figure 2: FULLWAVE RECTIFIER WITH (LC) FILTER

Figure 3: FULLWAVE RECTIFIER WITH (π) FILTER

PROCEDURE:

FULL WAVE RECTIFIER (WITH FILTER)

1. Connect the circuit as shown in figures 2 & 3..

2. Tabulate Vdc, Vac by varying the IL in steps of 5mA (The change of R L causes the
change of IL)
3. Observe the rectified output on CRO. Calculate ripple factor & compare with
theoretical value

OBSERVATIONS:

Table (IV)

S.NO. RL IL Vac Vdc Ripple Theoretical

(Volts) (Volts) Factor Ripple
(Ohms) (mA)
= Vac/Vdc Factor

40
41
FORMULAE USED
RL
For inductor filter ripple factor  =
3 2L

1
For capacitor filter ripple factor  =
4 3 fCRL

2 1
For LC filter ripple factor = . 2
3 4 CL

X C1 X C 2
For -section filter ripple factor = .

RL XL

PRECAUTIONS:

42
 1. The primary and secondary side of the transformer should be carefully identified
2. The polarities of all the diodes should be carefully identified.

RESULT:

PRELAB QUESTIONS:
1. Define regulation of full wave rectifier and half wave rectifier?
2. Define peak inverse voltage (PIV)?
3. Does the process of rectification alter the frequency of the waveform?
4. What are the applications of a rectifier?
5. What is the necessity of the transformer in the rectifier circuit?
6. What is mean by ripple and define ripple factor?
7. Explain how capacitor helps to improve the ripple factor?
Can a rectifier made in INDIA (V=230v, f=50Hz) be used in USA (V=110v, f=60Hz)?

43
 7. Diode Clipper circuits

AIM:

1. To design and test the performance of clippers (peak clippers/base clippers)

2. To obtain the transfer characteristics of clippers.
3. To design and test the performance of clampers (positive and negative
Clampers) using diodes.

APPARATUS:

Signal generator 1No.

Power supply 1No.

CRO 1No.

Resistors:

10K, 100K 1No.

Capacitors:

1µF, 1No.

Diode:

1N4007 2No.

CIRCUIT DIAGRAM:

One way diode clippers

1. Positive Diode Clipper (Shunt Clipper)

44
2. Positive Diode Clipper (Series Clipper)

3. Negative Base Diode Clipper (Shunt Clipper)

45
4. Negative Base Diode Clipper (Series Clipper)

Two Way Diode Clippers

PROCEDURE:

1. Connect the circuits as shown in fig.

46
 2. Take one circuit at a time (say 1).Apply a sine wave of frequency 1 KHz 8Vp-p in case
of diode. Note down the input and output waveforms on both the channels of the
CRO. To obtain the transfer characteristics apply the input signal to channel A(X
input) and output signal to Channel B (Y input).After selecting XY mode at the input
connected)

3. Repeat the above steps taking the circuit (3) then (4) and so on.

RESULT:

47
 8. Clamper circuits

Clamping circuits:

CIRCUIT DIAGRAM:

1) To Clamp the Positive Peaks of the Input Signal at Zero Level.

2) To Clamp the Negative Peaks of the Input Signal at Zero Level.

3) To Clamp the Positive Peaks of the input Signal at VR = +2 Volts

Level

4) To Clamp the Positive Peaks of the Input Signal at VR = -2 Volts Level

48
PROCEDURE:

1. Connect the circuit as shown in fig. Note down the input and output waveforms
using a CRO on both the channels, under DC conditions (Keeping the input
switches to DC position).
3. Verify the clamping circuit theorem

(Where Af = Area under the o/p waveform for the diode in the forward bias
condition; Ar = Area under the o/p waveform for the diode in the Reverse bias
condition).

4. Repeat the above steps using the circuits in the above remaining figures

OBSERVATIONS:
Circuit Af Ar Ratio

Theoretical Experimental

(Rf/Rr) (Af / Ar )

(1)
(2)
(3)
(4)

RESULT:

49
PRE LAB QUESTIONS:

1. Indicate the advantages and the disadvantages of series and shunt diode clippers.
2. For good transmission in the diode clippers what is the basis to select R vis-à-vis the
diode parameter.
3. What are the consequences of a pulse type of input to a diode clipper?
4. What will be consequences of varying input periodic pulse train to a diode clamping
circuit?
5. What will be the consequences of peak clamping of narrow pulses or clamping the
sharp edges?

50
Cycle - II Experiments
(Using Cadence Tools)
9. Plotting MOSFET I V Characteristics

Aim: To simulate the I V characteristics of NMOS, PMOS transistors and observing the
effect of various parameters on their characteristics

Software Tools: Cadence Virtuoso, ADE L, Spectre, Assura, Quantus

Theory:

NMOS/PMOS devices are formed in a p/n-type substrate of moderate doping level. Source and
drain are isolated from one another by two diodes. For, enhancement mode device, a minimum
voltage level of threshold voltage Vth must be established between gate and source to obtain a
channel inversion. Now the current flows in the channel by applying a voltage Vds between
drain and source. There must, of course, be a corresponding IR drop = Vds along the channel.
This results in the voltage between gate and channel varying with distance along the channel
with the voltage being a maximum of Vgs at the source end. For all voltages Vds < Vgs - Vth, the
device is in the non-saturated region of operation and in other case saturation region.

Circuit diagram of NMOS:

51
Circuit diagram of PMOS:

Procedure:

1. Select the project library and create new schematic and cell.
2. Select the instance and click gpdk045…symbols…Choose PMOS1v/NMOS1v.
3. Include pins to the circuits and create a symbol and save the symbol.
4. Create a new cell in same schematic.
5. Select the instance (click i) and select the schematic from the user library.
6. Make interconnections by selecting wire and construct the schematic diagram.
7. Include supply voltages and input signal source.
8. We can alter the properties of PMOS1v/NMOS1v by selecting component and press
the button Q. Click on check and save button.
9. To perform transfer characteristics, give a constant voltage to V DS and vary the VGS
voltage plot the Drain current.
10. To perform Drain characteristics give a constant voltage to VGS and Vary the VDS
voltage plot the drain current.
11. Check the variation of drain and transfer characteristics with different width and
length of the MOSFET
12. Check the variation of drain and transfer characteristics with different temperatures.
13. From characteristics calculate the threshold voltage, Trans-conductance, output
resistance for the above cases.

52
Simulation outputs:
PMOS Characteristics:

53
NMOS Characteristics:

Results: Calculated MOSFET parameters from its characteristics and observed the effect on
the parameters/characteristics of MOSFET by its second order effects.

54
 10. DC & Transient analysis of CMOS Inverter.

Aim: To Design and simulate the Symmetrical CMOS inverter and performing DC and
Transient analysis on it.

Software Tools: Cadence Virtuoso, ADE L, Spectre, Assura, Quantus.

Theory:

The CMOS inverter consists of a combination of an pMOS transistor at the top and a nMOS
transistor at the bottom. CMOS is also sometimes referred to as complementary-symmetry
metal–oxide–semiconductor. The words "complementary-symmetry" refer to the fact that the
typical digital design style with CMOS uses complementary and symmetrical pairs of p-type
and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
Two important characteristics of CMOS devices are high noise immunity and low static power
consumption. Significant power is only drawn while the transistors in the CMOS device are
switching between ON and OFF states. Consequently, CMOS devices do not produce as much
waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic,
which uses all n-channel devices without p-channel devices.

Circuit Diagram:

Procedure:
1. Select the project library and create new schematic and cell.
2. Select the instance and click gpdk045…symbols…Choose PMOS1v/NMOS1v.
3. Include pins to the circuits and create a symbol and save the symbol.
4. Create a new cell in same schematic.
5. Select the instance (click i) and select the schematic from the user library.
6. Make interconnections by selecting wire and construct the schematic diagram.
7. Include supply voltages and input signal source.
8. We can alter the properties of PMOS1v/NMOS1v by selecting component and press
the button Q. Click on check and save button.
Edit the required changes in the symbol it look like below

55
9. After creating symbol connect supply voltages and input sources and run simulation.

10. FUNCTIONAL SIMULATION

To simulate the design launch ADEL window.

56
Simulation Results:

Results: Obtained the symmetrical CMOS inverter and perform the DC and Transient
analysis

11. DC & Transient analysis of FinFET Inverter.

57
Aim: To Design and simulate the Symmetrical FinFET inverter and performing DC and
Transient analysis on it.

Software Tools: Cadence Virtuoso, ADE L, Spectre, Assura, Quantus.

Theory:
A FinFET is classified as a type of multi-gate Metal Oxide Semiconductor Field Effect
Transistor (MOSFET. A multi-gate transistor incorporates more than one gate in to one single
device. In FinFET, a thin silicon film wrapped over the conducting channel forms the body.
The name has been derived from the fact that the structure, when viewed, looks like a set of
fins. The thickness of the device determines the channel length of the device.

Circuit Diagram:

Procedure:
11. Select the project library and create new schematic and cell.
12. Select the instance and click gpdk045…symbols…Choose PMOS1v/NMOS1v.
13. Include pins to the circuits and create a symbol and save the symbol.
14. Create a new cell in same schematic.
15. Select the instance (click i) and select the schematic from the user library.

58
16. Make interconnections by selecting wire and construct the schematic diagram.
17. Include supply voltages and input signal source.
18. We can alter the properties of PMOS1v/NMOS1v by selecting component and press
the button Q. Click on check and save button.
Edit the required changes in the symbol it look like below

19. After creating symbol connect supply voltages and input sources and run simulation.

20. FUNCTIONAL SIMULATION

To simulate the design launch ADEL window.

59
Simulation Results:

Results: Obtained the symmetrical FinFET inverter and perform the DC and Transient
analysis

60
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