----SHARP----

SERVICE MANUAL

CE-158
WWW.
PC· l500
.INFO

SHARP CORPORATION
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SERVICE MANUAL
MODEL CE-158
RS-232C Interface
(PC-1500 Option)

CONTENTS

I. Int roduction . . . . _ . .. . . . . _ . .. • ... . . . . .. .. .. . . ..-. . .-... .

2. Specificat ion .... _ .. ... . .. .. . ... . ... .•. -.. .. . . . .... . . . . - . . J
3. System configuration . . . . . . . . . . . . . . . . . . • . •... . . .. •.. .. ... . .. 2
4. lllock diagram .. . _ . . . . . . . . . . . . . . . . . . . . . . .. .. . .. .. .. . .. .. .. 3
S. Circuit discription . - .. • . . .. . . ... . . .. . ... . ... . .. . . . . . . . . . . - 4- 8
6. l.si discription . .. - . . . .... . . . . . . . .. . . . . . .... . . . .. . . • ... . . 9- 17
7. IC pin connection . - . . . . . . • . . . . . . . • . . .• .. ... ... . . . ....... 18- 20
8. Circuit diagram . . . . . . . . . . . . . . . . . . . . . • . . . . .. .. . . . . . . . . . . . . 2J
9. Color chart .... . .... .. . ...... . . . . . •.. . . . ... . . . · · · • · · · · 22- 23
l O. Parts Guide/ Parts list . . . . . . . . . . . . . • • . . • . . . . . . ... .• · · · · · · · · 24 - 2 8

File this manual into the service manual "PC-1500 & Option"

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1. INTRODUCTION
There arc cwo cypcs of interfaces built-in. One is a general-purpose interface for the communication
between PC- 15011) and a device equipped wi1h RS-232C 1ype i111erface, such as personal computor,
peripheral device, etc. The 01her is a centronic$ type parallel interface for full-scale data processing
printers.

2 . RS-2 32C INTERFACE SPECIFICATIONS

·rransrnission ll)Cthod Asynchronous
Applicable standards EIA RS-232C compliance
Baud ra te 50, 100, 110, 200, 300, 600, 1200, 2400 baud, programmable•
Data bit 5, 6, 7, S bits, progra mmable
Parity bit Even, odd, non-parity) progranunabJe
Stop bi1 1, 1.5 for 1he character size of 5. }
programmable
2.0 for the character sizes of 6 to 8.
Connectors used 60-pin male connector for connection with 1he PC-1500 or CE-150.
25-pin connector, DB-2S(W), for connection wi1h an ex ternal device.
Adaplor jack.
Power supply source 4.8 V ~ (DC): Ni-Cd rechargeable b:lllcry
AC: 120 V, 60 Hz wilh EA-21 A
Po\vcr consun1ption 4.8 V m (DC), 0.80 W
AC adaptor/charger EA-21 A (120 V. 60 Hz)
Ba11ery capacity For approx. 3 hours of operation (charging: 15 hours)
Output sig11al level High level: +5 V to +IO V (3 to 7 Kohms load)
Low level: - 5 V to - 10 V (3 l<l 7 Kohms lo:id)
Interfacing signals Inputs: RD, DSR, Cl), CTS
Outputs: TD, RTS, DTR
01hcrs: SC (FG)
Switch XI (POWER switch)
Dilncnsions 86 (W) X 115 (D) X SO (H) mm
3-3/8" (W) X 4· 17/32" (D) X 1-3 1/32" (H)
Weigh t 435 g (0.96 lbs.)
Accessories Keyboard 1cmpla1cs, join! plales (1wo kinds) and instruction manual.

• : In terminal program mode, the speciftca1ions of baud rate (600, 1200 :rnd 2400) is restricted.

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3. SYSTEM CONFIGURATION
CON,NECTION OF PC-1500 WITH CE-158

CE · 158

Power sw i tch

Jo in t p late (A)

CONNECTION OF PC-1500 WITH CE-150 AND CE-158

PC·1 500 CE· 150

CE· 158
""'
Con nee tor for ~
parallel interface---+1-..:;;;~~
AC adaptor
connection jack
Connector
for RS·232C
""
Joint p late (8 )

2
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4. BLOCK DIAGRAM
• V'(+
OC IOC Ve:>
CONverueA ;;,. GNI>
• Ve-

r-- - - - -- -- - - -- - - - i't l'N. ltJ T

.------1.~tf=::i:::::=:--·::::::::::::::--i-----~ ···
C.MOS

n===I-
UAAT
~ COP1A54ACI<
'"'
It•:,,.,,"
..)~)
t: • (-c)l;!I

K.S·2J2C llf $ i.:1:; 188

OS·:?S(A) SNl'Sl l}!)A
Hr----+•--+--~+----------l}A lE cus
r--+l--'----1--1-----~----- AOHES SUS

Ej'.- - - - - PU 1, OMEo
PAR.=t. lL EL llF
D A.2$tBJ
RCM !--"------""·
S C>Gll XXX
• vcc
s ;NQ
tiOPIN
C::OllNl!C l O R

CO 0 l!o:l t; K H~

3
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5. CIRCUIT DISCRIPTION
• Power >upply
The CE·1 58 is driven by the PC·ISOO power (Vee) and Ni-Cd battery, o r through an AC adapter.
The input is fed through the DC-DC converter to reach VDO (+5.0 V), VC+ ( +9.0 V), and VC-
(- 9.0 V).

Notel . Oat"' rl nc 1i11cr(ESD-H-14B}

,__,-<> VC-(- 9.0V)

1W 100Cl
,__,-<> VC+ (+ 9.0V)
EA21Ay + r--~--. DC-DC
l ow battery
0.1 100 1 ConYOtOI' 1---0 VD oC+ 5.0 V }
de tection
)If X2 Circuit. Circuit
P.GNO -+--~'----;,_;....~

,__,..-<) GNO

'---· 16V
220µF
S. GND

• Low battery detection circuit

Battery condition is monitored by the circuit sketched below. Signals detected are checked by the
CPU for each receiving and transmilting step through LH58 J I's PA5 1/0 port. Besides, SW6
reaches the GND level with power on, thereby turning on 2SA937R to keep the low battery
detection circuir in function .

2SA937R
(SW6}
3 .:lKO

150
560 KO
Vee
+ H438LL01
SOV 11rF 100KO

RV22KO 2SC2021RS

4
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•1
.....

'"
·~

''
c
·•• ·~ ..

Note: While the power switch is on , SW4 and SWS arc kept open to each otl1cr. Vee is impressed
to the base of 2SC202 I, and 2SC202 I and 258822 arc turned on.

• 1)Note I : Data line filtcr(ESO.H·l4B)

•2) Converter H1750
•3) 3-terminal rcgul•tor

s
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POWIER SOURCE (PC-1500, CE-150, CE-158)

, ,~
PC" 500
.... CE·1 50

~A INT(:R
,,
o-e=}--o
(A.t50
1SS9E AEGULATOA OAIV€R
1001)( "1
•
Al; MOTE
= suM CI P (:UIT "'
,:. 3 ... • ••• vcc
V« lOW 941i t.t-c:d -
C-':Q#fl ""~ ..c s=

REY
''
..
oFF -+-- ori-t--oi=r:
~·

Ve.a
'' '
--·~·--·~· -
'
''
''
Vu
L'
V¢. 'J¢
Voo L CE-1 5 8

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(SW 2)

0 D D 0
p p p I) V ss 150K
B D B B
4 3 2 1
_T
_l_R_C_L_O_C_K_ _. PEOUT 110 145696 cl--~~~~-<.,:-7=~~'-..>-~
CF
Vee. 'loo 154KHt
CTLA
Vss CTLe

• CLOCK circuit
According to commands from the CPU, the frequency dividing ratio is changed to make a clock
pulse corresponding to respective baud rates. In init ial setting, after turning the power switch on,
the baud rat e of 300 is automatically provided. Thus a specified baud rate can be obtained with
ch•nge command from the CPU. The commands 3rC delivered to LH581 l ports PCO thru PC4,
PA6 or PA7. (T/ R clock = baud r3tc X 16)

• CDP1854ACE CH IP S ELECT
The conditions to select this chip are that CSI and CS3 arc at HIGH posi1 ion and that CS2 is at
LOW position.
The circuit is as shown below.

A015(1 ) j d ) 0200 ................ WRITE)

A0 14(1)- ---l
- - ·>--- - CS2

A012(1)
----- 0 201 ................ READ

.--•CS3
A09 (1 ) CS 1
1108
AD I RO/WR

40H 138P

A015(t ~ Y1 h Of-
A014 (1) o,. 0
er;;
·:~
110 13 (0 _J of-
11 0 12(1 r- G1
A011 (0I c
11010(0) B
1109 (1) A
YI • G1 •
ME l (1 \ .

7
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• TPB Cl RCUIT

Y,- - ----.

0-----~

TPB
The lefr.hand circuir is 10
M£ , produce one pulse at ME,
( Y1 ) . At Y 1 and <Pos.
Y, 0 PRO X>-- TPB however, two pulses are
generated up to TPB. There.
fore, a stage of OFF i.s
~«; CK added to produce signal Q .
CL Thus TPB consisls of Y 1, Q,
and ¢OS·
V<x:

• INT CIRCUIT

A15 (1 /
INTERRUl'T PORT ADDRESS

A 13\G) -l-~==::::_____,J G>b

DEOO)
ME, ( I
A 12{1 ) DFFF
r -- --iG 1
A11 (11) - -- -+ - - -- C
A 10(1 ) 8
A9 (1) - - - - +-- ---l
AS
ME l (1 ) ---~

INTERRUPT will be effective Ollly condilion of MEI , A9, AlO, All, A12, AB Al4, A15 ,
(In tcrrupl will proceed adress of between D£00 to DFFF)

• LH5811 CHIP SELE CT

~O H 1 38P
(Address 0000 o r DOOF to be used)
AD1S (1/ - --<
AD14 (1) - - -I 10---<)!G>a
Vss
A 0 ·13(0) -
-4-!:::===:::::_-_J--<jG >,•
A01 2 (1)
A0·11 (0) - -- - - - -- f --IC

AD tO(O) 8
A09 (0) A
'--- - - '
ME1 (1) - - -- -- - --'

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6. LSI Discription
CDP1854A, COP1854AC Types
1. Initialization and Controls
In this mode . the CDPJ854A is configured to receive commands and send stal\Js via the micro-
processor dat.a bus. The register connected to the transmitter bus or the receiver bus is determined
by the RD/WR and RSEL inputs as follows:

TAB LE 1-Register Se•,ction :;um•nary

RSEL RD{WR Function

Low LO\V Load Transmitter Holding Register from Transmitter Bus

LO\\' High Read Receiver Hod Ung Register from Receiver Bus
High Low Load Control Register from Tranm1iltcr Hus
High Low Read Status Register from Receiver Bus

In this mode the CDPJ854A is compatible with a bidirectional bus system. The receiver and trans·
rnitter buses are connected to the bus. The CLEAR input is pulsed, resetting the Control, Status,
and Receiver Holding Registers and setting S.ERIAL DATA OUT(SDO) high. The Control Register
is loaded fronn the Trans111itter Bus in order to deter1nine the o per3ting configuration for tlu? UART.
Data is transferred from the Transmitter Bus inputs to the Control Register during TPB when the
UART is selected (CS I · CS2 · CS3·1 ) and the Control Register is designated (RSEL = H. RD/WR
= L). Titc CDPI 854A also has a Status Register wltich can be read onto the Receiver Bus (R BUS O-
R BUS 7) in order to determine the status of the UART. Some of these status bits are also available
at separate te rminals as indicated in Fig. 7.

2. Transmitter Operation
Before beginning to traMmit. the TBANSMIT REQUEST (TR) bit in the Control Register (see bit
assignment, Fig. 3) is set. Loading the Control Register with TR = I (bit 7 = ihig)1) inhibits changing
the other con trol bits. Therefore two loads arc required : one to format the UART, the second to
set TR. 1~1ien TR has been set, a TRANSMITTER HOLDING REGISTER EMPTY (THRE) inter-
rupt will occur. signalling the micropr<icessor that the Transmitter Holding Register is empty and
may be loaded. Setting TR also causes asscrhon of a low-level on the REQUEST TO SENT (RTS)
output to the peripheral. It is not necessary to set TR for proper operation for the UART. If de-
sired, it can be used to enable THRE intcrr~1pts and to generate the RTS s]gnaL The Transmitter
Holding Register is loaded from the bus by TPB during execution of an output instruction. The
CDPI 854A is selected by CS! • CS2 • CS3 - I, and the Holding Register is selected by RSEL =
L and RD/WR = L. When the CLEAR TO SEND (CTS) input, which can be connected to a
peripheral device output, goes low, the Transmitter Shift Register will be loaded from the Transmit·
ter Holding Register and data transmission will begin. If CTS is always low, the Transmitter Shift
Register will be loaded on t.he first high-to.low edge of the clock which occurs at least 1/2 clock
period after 'the trailing edge of TPll and transmis.•ion of a start bit will occur 1/2 clock period
later (see Fig_ I ). Parity (if programmed) and stop bit(s) will be transmitted following the last data
bit. If the word lengUt selected is Jess than 8 bits, the most significant unused bits in the transmitter
shift register will not be transmitted.
One transmitter clock period after the Trnnsmitter Shilt Register is loaded from the Transmitter
Holding Register, the THRE signal will go low and an interrupt will occur (INT goes low). The next
character to be transmitted can t.hen be loaded into the Transmilter Hold ing Register for trans-
mission with its start bi! immedialely following the lasl stop bit of the previous character. This cycle
can be repea ted until the las! character is transmitted, at which time a final THRE · TSRE intern1pt
will occur. T11is interrupt signals the microprocessor that TR can be turned off. This is done by

9
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reloading the original control byte in the Control Register with I.he TR bit= 0, thus terminating the
REQUEST TO SEND (RTS) signal.
SERIAL DATA OUT (SDO) can be held low by setting the BRcAK bit in the Control Rcgister($ee
Fig. 6). SDO is held low until the BREAK bit is reset

DYNAMIC ELECTRICAL CHARACTERISTICS at TA . - 40 tC> +85°C, Voo ±5%, t,, tf-20ns,

VIH . 0.7 Yoo· VIL= 0.3 Voo· CL • 100 pF. See Figs. 1and2.

LIMITS
CHARACTERISTIC Voo COPl8S4A CDP· l854AC UNITS
(V)
Typ." Max. • Typ.• Max. •
T rransmitter Timing - MOOE I
5 2so 310 2SO 310
ns
Minimum Clock Period ICC 10 125 ISS - -
Minimum P11lse Width: s I 00 125 100 125
ns
Clock Low Level lCL 10 75 100 - -
s I 00 125 JOO 125
Clock High Level l(;H 10 75 100 - - ns

5 100 150 100 ISO

TPB ns
ITT 10 so 75 - -
Minimum Setup Time: s 175 225 175 22S
ns
TPB to Clock ITC 10 90 I SO - -
Propagation Delay Time:
tco
s 300 450 300 450
ns
Clock to Data Start Bit JO I SO 225 - -
'rPB to THRJO 5 200 300 200 300
t·1TH 10 100 150 - - ns

Clock to THRE
5 200 300 200 300 ns
tent 10 100 150 - -
CPU lnicrface - W~TE Timing - MODE I
Minimum Pulse Wid01: 5 100 ISO 100 ISO
ITT ns
TPB 10 so 75 - -
Minimum Setup Time: 5 50 74 50 7S
RSEL to Write tRSW 10 25 40 - - ns

Data to Write 5 - 100 - 75 100 -75 ns

tow 10 -SO - 35 - -
Minimum Hold Time:
IWRS
s so 75 so 75
ns
RSEL after Write 10 25 40 - -
5 15 12S 15 125 ns
Data after Write two 10 40 60 - -
• Typical values are for T 11 = 2S°C and nominal voltages.
• Maximum limi ts of minimum characteristics are the values above which all devices function.

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TRA NSMITTER HOt. OING.. TRAN$M1r r £H $tUFT .,.:

REGISTER LOAOEO REGISTER LDADED

T CLO(;K
-: ~ tc o
WNI T EI
tTPB!
I l T,

-· , •
.........,.: trru :.....; :-1c1t-1
T...,E _ _ _~
__, .

soo I' ' DAT A. SIT

• THE BOLDING REGISTER IS LOADED ON THE TRAillNG EDGE OFTPB

•• THE TRANSMl1TER SHIFT REGISTER IS LOADED ON Till\ FIRST HIGH-TO.LOW lRt\!'ISITION
OF Tf! E CLOCK WHICH OCCURS AT LEAST I /2 CLOCK PERIOD + lTC AFTER THE TRAIUNG
EOGE OFTPB, ANO TRANSMISSION OF A START BIT OCCURS 1/2 CLOCK PERIOD +tep LATER.
WRITE IS TllE OVEl!LAP OF TPB, CSI , AND CS3 =I AND CS3. Rll/ WR • 0.

Fig. I - Transmiller liming diagram - MODE I.

• 1501'1' •
;-.-err·~

TP~---------------:;:,.,~
:---•Rsw 75ni : ;...1was...t1\
-----------~~----t•>-+----~·--~·~--
11SEL •
_-;!i '~. : X~--
125n111
:-•Dv1~ :-- wo::t,,____
1
T S US: 0-
f SUS 7 ------------"-----II,___ _ ___.___./\..___

11

• WRIT!> IS THE OVERLAP OF TPB. C:SJ, CS3 =I AND CS2. RO/WR • O.

Fig. 2 - MODE I cpu inte.rface (WRITE) timing diagram .

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CONTROL REGISTER BIT ASSIGNMENT TABLE

Bit 7 6 5 4 3 2 I 0
Signal TR BREAK IE WLS2 WI.SI SBS EPE Pl

Bil Signal: Func1ion

0 PARl1Y INHIBIT (Pl):
When sea high parity gcneralion :llld vcrificalion are lnhibiled and the PE Status bit is held low.
If parity is inhibited the stop bits(s) will immediately follow 1he last da1a bil on 1ransmission.
and EPE is ignored.

EVEN PARITY ENABLE (EPE):

When set high. even parity is generated by the transmillcr and checked by the receiver. Wilen
low, odd parity is selected.

2 STOP BIT SELECT (SllS):

Sec table below.

3 WORD LENGTH SELECT I (WLSI):

See table below.

4 WORD LENGTH SEUiCT 2 {WLS2):

See 1able below.

Bit 4 Bil 3 Bit 2

WLS2 WLSI Function
SBS
0 0 0 5 data bits, I stop bit
0 0 1 S data bias, J.S stop bits
0 I 0 6 da 1a bias, I stop bit
0 I 1 6 data bits, 2 stop bits
0 0 7 data bits, I stop bit
0 1 7 data bias, 2 stop bits
0 8 dala bits, 1 stop bit
8 da1a bits, 2 stop bits

Fig. 3 - Control Rcgistar bit assignment.

5 INTERRUPT ENABLE (IE):

When set high THRE. DA. THRE · TSRE, CTS. :llld PSI interrupts are enabled (see ln1errupt
Conditions. Table II).

6 TRANSMIT BREAK ( BREAK):

Holds SDO low when set. Once the break bit in the control regis1er has been set high. SDO will
s1ay low until the break bil is reset low and one of the following occurs: CLEAR goes low; CTS
&oes high ; or a word is transmilled. (The 1ransmit1ed word wil.I nol be valid since there can be no
starl bit if SDO is already low. SDO r;.1n be sci high without intermediate transitions by trans·
milling a word consisting of all zeros).

7 TRANSMIT REQUEST (TR):

When set high, RTS is set low and data transfer through the 1ransmit1cr is initiated by the ini tial
THRE interrupt. (When loading the Control Register from 1he bus, this (TR) bit inhibi1s chang-
ing of other control Oip.nops.)

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3. Receiver Operation
The receive operation begins when a start bit is detected at the SERIAL DA TA IN (SDI) input.
After detection of the first high·to-low transition on the SDI line, a valid start bit is verified by
checking for a low-lave! input 7-1/2 receiver clock peri<>ds later. When a vaUd start bit has been
verified, the following data bits, parity bit (if programmed) and stop bit(s) are shifted into the
Receiver Shift Register by clock pulse 7-1/2 in each bit time. The parity bit (if programmed) is
checked and receipt of a valid stop bit is verified. On count 7-1 /2 of the first stop bit, the received
data is loaded into the Receiver Holding Regis1er. If the word length is less than 8 bits, zeros (low
output level) arc loaded into the unused most significant bits. If DATA AVAILABLE (DA) has not
been reset by tbe time the Receiver Holding Register is loaded, the OVERRUN ERROR (OE) status
bit is set. One half clock period later, the PARITY ERROR (PE.) and FRAMING ERROR (FE)
status bits become valid for the character in the Receiver Holding Register. At this time, the Data
Available status bit is also set and the Data Avai]able status bit is also set and the DATA
AVAILABLE (DA) and INTERRUPT (INT) outputs go low, signalling the microprocessor that a
received charac.ter is ready. The microprocessor respond.< by executing an input instruction. The
UART's 3-state bus drivers are enabled when the UART is selected (CS! · CS2 · CS3 = I) and
RD/WR = high. Status can be read when RSEL =high . Data is read when RSEL = Low. When read-
ing data, TPB latches data in the microprocessor and resets DAT A AV Al LABLE (DA) in the UART.
The preceding sequence is repeated for each serial character which is received from the peripheral.

STATUS REGISTER BIT ASSIGNMENT TABLE

Bit 7 6 5 4 3 2 I 0
Signal THRE TSRE PSI ES FE PE OE DA
Also Available 22• 14 15 15 19•
at Terminal
•Polarity reversed at output terminal,
Fig. 4 - Status Register bit assignment

BIT SIGNAL: FUNCTION

0 DATAAVAlLABLE(DA):
When set high, this bit indicates that an entire character has been received and transferred to the
Receiver Holding Register. 11\is signal is also available at Tem1. 19 but with its polarity reversed.

OVERRUN ERROR (OE):

When set high, this bit indicates that the Data Available bit was not reset before the next
character w"' transferred to the Receiver Holding Register. This signal OR'ed with PE is output
at Term. 15.

2 PARITY ERROR (PE):

When set high , this bit indicates that the received parity bit docs not compare to that pro-
grammed by the EVEN PARITY ENABLE (EPE) control. This bit is updated each time a
character is transferred to the Receiver Holding Register. This signal OR'ed with OE is output at
Tenn. 15.

3 FRAMING ERROR (FE):

When set hi·gh, this bit indicates that the received character has no valid stop bit, i.e., the bit
following the parity bit (if programmed) is not a high-level voltage. This bit is updated each time
a character is transferred to the Receiver Holding Register. This signal is also available at Term.
14.

4 EXTERNALSTATUS(ES):
This bit is set high by a low.level input at Tenn. 38 (ES).

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5 PERIPHERAL STATUS INTERRUPT (PSI) :
This bit is se t high by a high·t<>-low voltage transition of Term. 37 (PSI). The INTERRUPT out.
put (Term. 13) is also asserted ( INT = low) when this bit is set.

6 T RANSMITTER SHIFT REGISTER EMPTY (TSRE):

When set high , this bit indicates that the Transmitter Shift Register has completed serial trans·
mission of a full character including stop bit(s). It remains sci until the start or transmission o f
rhe next character.

7 TRANSMITTER HOLDING REGISTER EMPTY (THRE):

When set high, this bi t indicates that the Transmi tter Hol ding Register has transferred its
contents to the Transmitter Sh ift Register and may be reloaded with a new character. Setting this
bit also sets the THRE output (Term. 22) low and causes an INTERRUPT (INT= low), if T R is
high.

4. Peripheral Int erface

In addition to serial data in and o ut, four signals arc provided for communication with a peripheral.
n ie REQUEST TO SET NT ( RTS) output signal alerts the peripheral to gel ready 10 receive data.
The CLEAR TO SEND (CTS) input signal is the response, signalling that the peripheral is ready. The
EXTERNAL STATUS (ES) input latches a peripheral Slatus level, and the PERIPH ERAL STATUS
IN TERRUPT (PSI) input senSC$ a status edge (high·lo·low) and also generates an interrupt . Fo r
example, the modern DATA CA RRIER DETECT line could be connected to the l'sfinpul on the
UART in order to signal the microprocessor that transmission failed because of loss of the carrier
on the communications line. The PSI and ES bits arc stored in the Sta tus Register (See F ig. 4 ).

~ : -1oc •
so1-----i : S fAAT Bil PAHnY I srOP err t

A(AO•• ~~---t------~-------------T-'---
--t I TT~
TPS _ _ ___,
' - - - - - -- - - -- - - -- - - - _.) ; !--• COL
OE•
: ICP~
:----:
··· ~-----------------------.;,....;_
1'CPt
,.....-.
Ft;I
- - ---------------- ---=--'--
Fig. 5 - MODE I receiver timing diagram.

' I I' A START BIT OCCURS AT A TIME LESS THAN Toe DE FO RE A fllGH·'f().LOW T RANSITION
O F 'Jll E CLOCK. T HE START BIT MAY NOT RE R ECOG NIZED UNTIL T HE NEXT JllGll·TO· l. O W
TRANSITION OF T HE CLOCK, T HE START arr
MAY IHO CO MPLETELY ASYNCHRO NOUS WIT.H
TllECLOCK.
" RE AD JS THE OVERLAP OF CSI , CS3. R D/WR • 1 AND CS2 • O.
II' A PE NDING DA HAS N OT BEEN CLEA RE D BY A REA D O F THE RECEI VER HOLDING
REGIST E R BY THE T IME A NEW WOR D I S LOADED t NTO TllE RECEIVER llOLDINC REGISTER ,
Til £ 0F. SIGNAL WI LL COME T RUE.
t 0£ AND P£ SHARE TERMINAL JS AND ARE ALSO AVAILABLE AS 1'1'0 SEPARATE BITS JN TIIE
STATUS REGISTER.

14
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DYNAMIC ELECTRICAL CHARACTERISTICS at TA= -40 to +85° C, Voo :it5%, tr. If= 20 ns,
V1H = 0.7 Voo . VIL = 0.3 Voo . DL = 100 pF. See Figs. 5 and 6.

LIMITS
Yoo
CHARACTERISTIC CDPJ854A CDP 1854AC UNITS
(V)
Min. Typ.• Max.• Min. Typ .• Max.•
Receiver Timing - MODE 1

Minimum Clock Period

5 - 250 310 - 250 31 0
ns
tee 10 - 125 155 - - -
Minimum Pulse Width : 5 - 100 125 - 100 125
Clock Low Level tel JO - 7S JOO - - - ns

5 - 100 125 - 100 12S

Clock High Level ten JO - 75 100 - - -
ns

5 - 100 150 - 100 150

ns
TPB t rr 10 - so 75 - - -
Minimum Setup l ime : 5 - JOO ISO - 100 150
Data Start Bit to Clock
1 Dc
JO - 50 75 - - - ns

Propagation Dela):'. Time:

1
TPB to DA'l'A AVAl[Al![E. TDA
5
10
-
-
220
110
325
17S
-- 220
-
325
- ns

5 - 220 325 - 220 32S

ns
Clock to DATA AVAI LABLE tcoA 10 - 110 175 - - -
5 - 210 300 - 210 300
Clock to Overrun Error 1c o E
10 - 105 ISO - - - ns

Clock to Parity Error tc PE

5
10
-- 240
120
375
175
-- 240
-
375
- ns

s - 200 300 - 200 300 ns

Clock to Framing Erro r 1crE 10 - I 00 150 - - -
CPU Interface - READ Timing - MODE l
Minimum Pulse Width : s - 100 ISO - JOO 150
ns
TPll Irr 10 - 50 75 - - -
Minimum Setup Time : 5 - 50 7S - 50 75
ns
RSEL to TPB tRST 10 - 25 40 - - -
Minimum Hold T ime : 5 - 50 75 - 50 75
ns
RSEL after TPB t ·rns JO - 25 40 - - -
Read to Data Access Time 1RDDA
5
10
·-
-
200
JOO
300
150
-- 200
-
300
- ns

Read to Data Valid Time

5 - 200 300 - 200 300
ns
tROV JO - JOO 150 - - -
RSEL to Data Valid Time 1RSDV
s
10
-
-
ISO
75
225
12S
-- 150
-
225
- ns

Hold Time: 5 50 150 - 50 150 -

Data after Read
1RDM
10 25 75 - - - - ns

• Typical values are fo r TA = 25°C and nominal voltages.

•Maximum limits of miniJnum characteristics are the values above which all devices fu nction.

15
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~•rr -;

TP9 ~~~~~~~~~~~~~~

~tnsr_; ;._tTAS- :
ASEL ~~~~~~~~~v-~~~~-1 •~~~...,._~--..,;,...-~~~~

II
* READ IS THE OVER LAP OF CS !. CS3. RD/WR • I AND CS2 • 0

Fig. 6 - MODE I cpu inte1facc (READ) timing diagram

TABLE 2·1nterrupt Set and Reset Conditions

SET* (INT = LOW) RESET (INT = HIGll)
CAUSE CONDITION TIM E
DA
(Receipt of data} Read of datn TPB leading edge
THRE* Read or Stntus or
TPB leading edge
(Ability to reload) write of character
THRE • TSRE Read of status or
write of character TPB leading edge
(Transmitter done)
PSI
Read of status TPB trailing edge
(Negative edge)
CTS
Read of st :it us TPB leading edge
(Positive edge when TH RE · TSRE)
• Interrupts will occur o nly after lhe 1£ bit in the Co ntrol Rcgislcr (sec F ig. 3) has been set.
• TH RE will cause an interrupt only :after the TR bit in the Control Register (see Fig. 3) has been se t.

FUNCTIONAL DEFINITIONS FOR CDP1854A INTERRUPT (INT):

TERMINALS ~1 0DE I A low·lcvel voltage al this output indicates the
p1escncc of one of more of the interrupt con·
ditions listed in Table 2.
SIGNAL: FUNCTION FRAMI NG ERROR (FE):
vDD: A high-level voltage at this output indicatt!S
Positive supply voltage that the 1eceivecl character has no valid stop
bit , i.e .. the bit following the paii ty bit ( if
programmed) is not a high·levcl volt:tgc. This
MODE SELECT (MODc): ou tput is updated each lime a chnraclcr is
A higll·level voltage at this input selects transferred 10 the Receiver Holding Register.
MODE I operation. PARITY ERROR or OVERRUN ERROR
(PE{OE):
VSS: A hig)l·lcvcl voltage at this output indicates
Ground that either the PE or OE bit in the Sll1Us
CHIP SELECT 2 (CS2): Register has been set (see Status Register Bit
A low·lcvcl voltage at this input ll>gether with Assignment , F ig. 4).
CS I and CS3 selects the COPI 8S4A UART. REGIST ER SELECT ( RSEL):
This Input is used to choose eit her the
RECEIVER BUS ( R BUS 7 · R BUS 0): Control/Statlls Register (high input) or the
Receiver parallel data outputs (may be ex· transrnltter{receiver data registers (low input)
ternally connected to corresponding transmit·
according 10 the lruth table in Table I.
tcr bus terminals).

16
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RECEIVER CLOCK (RCLOCK):

Clock input with a frequency 16 times the de·sired receiver shift rate.
TPB :
,\ positive inJ)Ut pulse used as a da ta load or reset strobe.
DATA AVAI LABLE(DA)
A low·levcl voltage at this ou tput indica tes tltat an entire character has been received and transferred
to the Recei\•er Holding Register.
SERIAL DATA IN (SDI):
Serial data r-cceived on this input line enters the Receiver Shift Register at a point detennined by
the charac ter length. A high·level input voltage must be present when data is not being received .
CLEAR (CLEAiR):
A low.level voltage at this input resets tl1e Interrupt Flip.Flop, Receiver Holding Register, Control
Register, ancl Sta tus Register, and sets SERIAL DATA OUT (SDO) high.
TRANSMITTER HOLDING REGISTER EMPTY (THRE):
A low.level voltage at th is output indicates that tl1e Transmitter Holding Register has transferred its
contents to the Transmitter Shift Register and may be reloaded with a new character.
CHIP SELECT :I (CS!) :
A high·level voltage at tllis input toge ther wit.h CS2 and CS3 selects the UART.
REQUEST TO SEND (RTS):
Tltis output signal tells the peripheral to to get ready to receive data. CLEAR TO SEND (CTS) is
the response from the peripheral. RTS is set to a low·level voltage when data is latched in the Trans·
milter Molding Register or TR is set high, and is reset high when both tbe Transrnitter Holding
Register and Transmitter Shift Register are empty and TR is low.
SE RI AL DATA OUTPUT (SDO) :
The contents of the Transmitter Shift Reg;s1er (start bit, data bits, parity bit, and stop bit(s) are
serially shifted out on this output. When no character is being transmitted, at high level is main·
taincd. Start of transmission is defined as tlle transit ion of the start bit from a high.level to a low·
level oulpul vollage.
TRANSMITTE R BUS (T BUS 0 · T BUS 7):
Transmitter parallel data inpu t. These may be externally connected to corresponding Receive r bus
1cnninals.
RD/WR :
A low.Jcvel voltage at this input gates data from the transmitter bus to the Transmitter Molding
Register or the Con trol Register as chosen by register select. A high-level vohage gates data from the
Receiver Holding Register or the Sta tus Register, as chosen by register select, 10 the receiver bus.
CH IP SELECT 3 (CS3)
With high·levcl voltage at this input together with CS I and CS2 selects the UART.
PE RIPHERA L STATUS INTERRUPT (PSI) :
A high·tO·low transition on this input line ·sets a bit in the Status Register and causes an INTER·
ROPT (INT = low}.
EXTERNAL STATUS (ES):
A low.Jcvcl voltage at tllis input sets a bit in the Status Register.
CLEAR TO SEND (CTS):
When this input from peripheral is high, transfer of a character to the Transmitter Shiirt Register
and shifting of serial dala on\ is inhibited.
TRANSM ITTE!R CLOCK (TCLOCK):
Clock input with a frequency 16 times the desired transmitter shift rate.

17
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7. IC PIN CONNECTION
TC40Hl38P
Pin connections Logic diagram
DA TA OUTPUT
w
y;
SELEC T B w
w DATA
w OUT PUT

• ') f> "I • VS'

A 8 C ffi628 Gl Y7 Vss Vlf
SELECT ENABLE 8Cf~UT VY
• Protect ivc circuits provided for all inputs

TC40H074P TC40HOJOP

Block diagram Pin connections

Voo 14 IC 1Y 3C 38
13

2 0 0 5 12 0 0 g

3 CK 0 6 1t CK o 8 1/\ 18 2A 2Y Vu

TR PR'

• V$S : 7
10

TC40H368P TC40H027P
Pin con nections
IC 3A

2C v..
I 8
Gl 11\ 1Y 2A 2V 3A Vss

18
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HD14569B

• PIN ARRANGEMENT

TOP Vlf.W

• BLOCK DIAGRAM
0PA?. 0 J>o\4
0PA1 Di>AJ en... CY t~ 0.-tP C..t') l'l~) =Mi·
y

CTL = "O" AT BINARY COUNTING

UCO IB1N r'f 4 ·C•! 6 CO f!ln.try
c H•(;-1'. Sf!Oeti
Joti~n C.oo.itw:tt
1----''"-
?E'°---l s .,n.:ri10f101.1l
C o.1"1:111
Q CTL = "J " AT BCD COUNTING

P oe).(!! ( r..•l.>!t'
CF<>-- - - < (lnt1..c1,"l.l !':.1:!y ~eto O ciec11on >-- --0· PEout

• LOG IC DIAGRAM

<
)T 0 ,.,

::u J <> J

o.... o •••

19
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BLOCK DIAGRAM OF CDP1 854A

l AAN$MITT £R SC:CTION

""c
"
~ I~ IG 12.voo
:l .vss
21.ct f ,,R

s oo.. ~o

TRANSMITTER
24 Ji

RECEIV E A
. - - - i TIM ING & CONlROL J...+<~-----r T t M l t-.'G & CON TROL
36· N (;

SHIF T
A l;(i
20
SOI

ncvn
HOL DING
PARITY REG
GEN

TRANS
S HI F T
MUX
AE G

$TATU $ 3 ·STATE
IN T
REG ORlV ERS

13

"' 1~
0 0 g(.) I~
Iz
~ : : o I~
~ it'-
fA.AN5MITTER BUS +. ~CEI VEA &JS •
1 26~33~ , llf 1.S · l ~l
l. ~ :::::::::::::::::::::::.:::::::::::::::::::: ..-..::::::::::::::::::_·:::_
-::::::::.-_·_-...-...-.-.-'. .;
• · USER INTERL0 NN£Cl

1 cT E p N sc
s
M
R OU
I
,
I I 1
aus 31.S ao
1 s
0
R
1
c
s ..,,' "•'
s s I c l 0 l 1 I '"0 0 s I
' "
"
"COP1854ACE "
10 ii
v v v c
0 0 s
0 0 s s '
N • """
E O< l
~ ..
C~IXX ~
1 0
A 0
s
\
' T

20
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 II
I! 1111 W.l!lf 1111 It'll II 8111111 11'~.__i;J ,,, '
e~ '°rOG>".:< ~ ~"' -o ()
zG)o~"'
0
. . , l~ o
(lO

~
o a o o a o o a
0

i=:5
"
· z () s -- >--=tJ-'--.;>:;:O>'.C~~::;JNo---..._~---3;x?.3
'I). - :s:
- )> )> ;p. )> ;nc;: ,~ ~
m- :n....o-.o~o-oJn
o:;;w~ - ,,. I
VI (.:\ o
... ~~
g'
~ {.O

Q
~
..._ -

I
,
!J.._
18?1N FLAT CABLE
- -
-
c 0
~

• • • .. • - -~LI ..+-
sc:
0
0
l[)
.--
'
(.)
Q_ -
~
;;:
:::::
0.. 8. 0CD
~.OTR
- 7. GND
0
0
"' S. OSR u..
0
l[)
.-- 5.CTS a...
()' en
Q_
a.
~

"'
~. RTS

3. RO -
.J::.
< !)
Cll

-
~ 2. TO en
-
(J)

::J 0
c
0
.Q
....
"' a:
Q) 0
0
~

0 ct
E :::c
"O
c: u
"' a:
<(
0
...J
0
u
.
a>
p p p p p p p p p p v
8 8 8 8 8 B 8 C C C 0
1 Z3 t 56'176o0
®
N
N
13PIN
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..

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8. CIRCUIT DIAGRAM

.' .'
·' 1 l t ~} ; ~; i ;~;~: ~ ·: Al~I ~ fi
.. .. ~ "

!!i
.
• " '
• •
COP1854ACE

t ' •• •
•
"
'
'
..
•
'•
. . :1::_r;-;,i• • ' ••
~ • 'l; •
• ~ •
... •
)'\

T :r
_[
''"
~SN?5188
,,..,. .,
.., .c(lt.
TC401i368P~ rl-HI -1--HI-==

"' A •~ !·:".ot '. ,.,

Sim
"'°
1

.~-
,

~ Wli ' iu.~~

:'.""' :
1
v. ~ .,
'~ TC40~
010P
l ' - -- -H---1----t-HH+'
~1~ · I

OB- 25(8) '

_ _ _ _ ______ ______ j l TC40HOZ?P .
< Fl I
_____

, - - - + i --'«
' '
" f
-, (( ~, .. .. ·"r-H-t-r:_[;:::t:=::tt ~ Eifi:": l
),~~~' ·~:tr: d_~; ··: l ·~~
T'
!• !·l~

SN?4LS04
t• W

"" .. , u· •
·~ · J:
H0 145699

·1_1 ·· .. '·_r_"i:-
• -~

_J
·~ ' !~ :• : :· ... •• ,. ~· :?. : < ~..
SN?S189A •· SN75188
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' ..- ·1..,..

r.

-!$>.

TC40H368P TC40H027P

"''
., ~
-~ TC40H027P
:,.[ ~ TC40H010 P

. ~ --- - - -----.
• •'

;Jt=~;;:;~~~~~~~~~~~.A...••. ~·
'
-~~-------------rl----1-------------<?'" '
:
--i---------------tt-----'-------------<?~
:
'
~fi.HF~;:;=::::rr-~~~~--:·

•'"''
....:i ......
'
••
J. ...
T ""
\,60PIN
. ·--w----
CONNECTOR

r·
--· _J
T'"

21
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10. PARTS GUIDE

cur···

24
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OU UCDCDal CDCDCDCDZ
> a.. Cl. a.. Cl. Cl. a.. Cl. <9
Cl. Cl. Cl. Cl.

,--------~.--~ 0

0
5.

0.

0 25P
CUT
~~QI
0

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1 0
GND

13PIN
FLAT CABLE
I SN?!LSC4 PIN5
PC6CLH581 1)
0.01
/' F

v 1.5
KO
4
=
,•, =
11 . INIT
fT"
10. BUSY
U1

0.
9. DATAS
8. DATA7
-re
? . DATA6
6. DATA5
5. DATA4
4. DATA3
3. DATA2
2. DATA1
1 .STROBE <'. .0I

23
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PARTS CODE OESCRiPTiON N EW PARTS P ft1C E

No. MARK RANK RANK

1 GCABB2681CCZZ TOP CABiNET N D AM

2 GCABA2680CCZZ BOTTOM CABiNET N D AL
3 HDECA2087CCZZ DEC PANEL N D AG
4 LANGT1476CCZZ ANGLE-A N c AE
5 LAN GT 14 77CCZZ ANGLE·B N. c AE
6 LA NGT 147 5CCZZ BOTTOM PANEL FOR Ni·cd BATTERY N c AO
7 LFiX- 11 44CCZZ HO.LDER FOR FiXiNG OF Ni·cd BATTERY N c AO
8 PCUSS 1200CCZZ CUSHiON N c AA
9 PZE TL 1 469CCZZ iNSULATOR N c AA
10 PZETL 14 70CCZZ iNSULATOR N c AA
11 CPWBF2133 CSNA PWB UNiT (A) (RS232C) E
12 CPWBF2133CSNB PWB UNiT (B) (RS232C) E
13 CPWBF2134CSNC PWB UNiT (C) (PARAREL) E
14 QCNW- 1233CCZZ FLAT WiRE N B AH
15 QCNW- 12 3 4CCZZ FLAT WiRE N B AO
16 QCNCM 1 295CC6.J 60PiN CONNECTOR (M) 8 AV
17 QCNCW1305CC 2F 25PiN CONNECTOR (RS232C) N 8 BA
18 QCNCM1304CC 2F 25PiN CONNECTOR (PARAREL) N B BA
19 QSW- S1346CCZZ POWER SWiTCH N 8 AG
20 Q.J AKC 1003CC ZZ JACK FOR ADAPTOR c AO
21 XBBSF20 P 10000 SC REW (M 2X 10) c AA
22 XNESD20 - 16000 NUT AA
23 XBBSD26 P 0800 0 SC REW (M2.6XB) c AA
24 XNESD26 - 2 0 0 0 0 NUT c AA
25 XBPS020P04000 SCREW (M2X4) c AA
26 XUPS026P06000 SCREW (M2.6X 6) c AA
28 XNESDJ0 - 2 4 000 NUT c AA
29 QLUGE 1 008CCZZ LUG c AA
30 CBATZ1054CC01 Ni·cd BATTERY B AZ
31 PCAPH10 1 3CCZZ CONNECTOR COVER N D AO
32 PCAPH10 1 5CCZZ CONNECTOR COVER N 0 AC
33 PCAPH 1 0 1 4CCZZ CONNECTOR COVER N 0 AD
LX ~BZ 1 1 3 5 CCZZ SCREW (SPECiAL) OTHER CONTRY
35
SCREW (SPECiAL) USA, CANADA
N c AC
L X- BZ 1 141CCZZ
36 LX- BZ 1 135CCZZ SCREW(SPECiAL) N c AC
~ CPWBF2133CSNA PWB UNiT A
H QCNCM 1 295CC6.J 60PiN CONNECTOR (M) B AV
QSOCZTD28ACZZ iC SOCKET 28Pi N 8 AH
RCRS Z 1045CCZZ X'TAL 1~3 .6KHZ N 8 AH
VCCCPU1 HH 470.J CAPACiTOR (CERAMiC) 50V 47PF c AA
VCTYPU1NX 104M CAPCiTOR (SEMiCONOUCTOR) 12V 0. 1µF c AB
.'-I VHi CDP1854ACE UART CDP! 854ACE N B BE

25
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NE. '.'I PAR T $ PA1CE
NJ . PARTS CODE DESCRiPTiON MARK. HAN K RANK
;- VHiSC613 1 28P7 ROM LSi N B BG
VHi TC4Q HQ 1 QPN iC TC40H01 OP N B AF
VHiTC40H027P 1 iC TC40H027P B AF
VH iTC40H074PN iC TC40H074P B AL
VH i TC40Hl38P1 iC TC40H I 38P B AN
VH ITC40H368PN TC40H368P N B AK
VRD- ST2EY154J RESiSTOR 150Kn Y.W c AA
VRD- ST2EV222J RESiSTOR 2.2KO Y.W c AA
VRD- ST2EV333J RES iSTOR 33KO y.w c AA
VRD- ST2EV475J RESiSTOR 4.7Mfi Y.W c AA
XBPSD20P10000 SCREW (M2 XI 0) c AA
'-" XNESD20 - l 6000 NUT c AA

,... CPWBF2133CSNB PBW UNiT B

I- PZETL1 1 72CCZZ iNSULATOR c AA
QCNCM1254CCOB CONNECTOR 2PiN (M) B AC
QCNOM2331RCOE CONNECTOR 5PiN (M) B AF
QCNCW 1305CC 2 F CONNECTOR 25PiN (F) N B BA
QCNCW- 12 33CCZ2 WiRE N B AH
QJAKC1003CCZZ JACK FOR ADAPTOR c AD
RC- EZ1 05ACC1H CAPACiTOR 50V l µF c AB
RC- EZ106ACCJC CAPACiTOR 16V 10µ F c AB
RC- EZ227BCCJC CAPACiTOR 16V 220µ F c AC
RC- EZ335ACC1H CAPACiTOR 50V 3.3µ F c AB
RFiLN 1 005 CCZZ FiLTER N c AH
RMPTC0154QCKJ RESiSTOR 150KflX 10 Y,.W B AO
RTRNH1750CCZZ CONVERTER TRANSFORMER N B AK
RVR- MB4 I OQCZZ VARiABLE RESiSTOR 22Kn B AD
VCKVPUIHB103K CAPACiTOA (CERAM iC) 50V 0.0 1µ: F c AA
VCKVPUI HB22 1K CAPACiTOA (CEAAMiC) 50V 220PF c AB
VCKVPUIHB222K CAPACiTOA (CERAM iC) 50V 2200PF c AA
VCKVPU1 HB472K CAPACiTOR (CERAM iC) 50V 4700PF c AA
VCTVPU 1EX10 4M CAl'lACi'l'OR (SEMiCONDUCTOR)!\OVO.lµF c AB
VCT VPU 1NX1 04M CAPACITOR (SEMiCONDUCTOFI) 12V 0. 1µ F c AB
VHDDSl588 L l - 1 DiODE B AD
VHDDS 158 8L2- 1 D;OOE B AB
VHD 1001 /// /-1 DiODE B AD
VHEHZ3BLL 0 1- 1 ZENER DiODE B AO
VHERO 1 1 E6 I /- 1 ZENER DiOOE B AC
VHiHD14569B- 1 iC HD1 4569B N B AN
VH i LH58 11 // - 1 iC LH58 11 B AZ
1-1 VH i SN75188N- 1 iC SN75 188N B AM

26
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No. PARTS COOE DESCRiPTiON N E WPARTS PRICE

MARK R A NI<. R A NK
r-1 VH ri SN75189A- I iC SN7 5 189A 8 AP
VHiTA78 LOOSAP i C TA78 L00 5AP B AH
VRO- ST2EYR56.J RESiSTOR o.56 n y.w 5% c AA
VRD- ST2EYI03.J RESiSTOR lOKO Y.W 5% c AA
-
VRD- ST2EYl04.J RESiSTOR lOOKO y,w 5% c AA
VRO- ST2EYl23.J RESiSTOR 12KO Y,W5% c AA
--- --·
VRO- ST2EY153G RESiSTOR 15KO '/,IV 5% c AA
VR0- ST2EY153,J RESiSTOR 15Kn y.w 5% c AA
VRO- ST2EYl54.J RESiSTOR 150 K0 y.W 5% c AA
VRO- ST2EY222 .J RESiSTOR 2.2Kn y.w 5% c AA
VRO- ST2EY332.J RESiSTOR 3.3K0 y.W 5% c AA
VRO- S T2E Y333.J RESiSTOR 33K!l Y,W 5% c AA
VRO-S T2EY47 1 G RESiSTOR 4700 y.w 2% c AA
VRO- ST2EY472G RESiSTOR 4.7K!l Y.W 2% c AA
VRO- ST2EY564 .J RESiSTOR 5GOKO y.w !'>% c AA
VRO- ST2EY68 1.J RESiSTOR Gaon y.w 5% c AA
VRS- PT3A8101.J RESiSTOR 100 0 l W 5% c AB
VS2SA937 - R / - 1 TRANSiST OR (2SA937) 8 AC
VS :2S B822 - / / - 1 TRANSiSTOR (2SB822) 8 AD
VS :2 SC2021 - RSC TRANSiSTOR (2SC202 1) 8 AF
VS :2 SC945 - P / QC TRANSiSTOR (2SC945) B AC
VS :2S D7 94AP / QC TRANSiSTOR (2$0794) N B AE
XBBSD26P08000 SCREW (M2 XS) c AA
'- XNESD26 - 20000 NUT c AA

r- CPWBF2134CSNC PWB UN1T C

t- QCNCM1304CC2F CONNECTOR 25Pi N (M ) N B BA
QCNW- 1 234CCZ Z FLAT CABLE N B AO
VCTYPU1NX104M CAPACiTOR (SEMiCONDUCTON) 12V0.11<F c AB
VHiSN74LS04 - 1 SN 74LS04 iC B AE
V RD - ST2EYI03.J RESiSTOR 1OKO y.w c AA
XBBSD26P08000 SCREW (tv\2 XS) c AA
'- XNESD26 - 20000 NUT c AA

TC AUH 1 201CCZZ CAUTiON LABEL N D AA

TLABB 1 713CCZZ NAME LABEL N D AB
TL ABN 1 1 52CCZZ SER NO LABEL 0 AA
L HLDZ 1181CCZZ HOLDER A N c AN
LHLDZ118 2CCZZ HOLDER B N c AL
L PLTP1102CCZZ TEMR...ATE N D AL
PGUMS 14 5 OCCZZ CUSHiON FOR iC N c AA
QCNCW I 31 JCCO1 CONNECTOR 2PiN (F) N B AF

27
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 All and more about Sharp PC-1500 at http:/lwww.PC-1500.info

N E.W PARTS PR•CF

No. PARTS CODE DESCR1PT10N MARK RANK RA NK
QCNCWI 31 2CCO I CONNECTOR 5P1N (F) N B AD

OUNT- 3710CC02 EA-21A USA CANADA SD AW

OUNT- 3711CC02 EA-21A MA AX
OUNT- 3712CC02 EA-2 1A MB AY
OUNT- 3 7 I 3CCO I EA-21A MV AY
OUNT- 3 7 I 4 CCO 2 EA-21A SB AY
OUNT- 3 7 I sec 0 I EA·2 1A SC BA
CUNT- 3 7 I 6CCO I EA- 21A SE BC
OUNT- 3717C CO1 EA- 2 1A SH BA
OUNT- 3 7 18CCO1 EA·21A SK AY
CUNT- 3 7 19CCO1 EA- 2 1A SM BC
OUNT- 3721CC0 1 EA-21A SN AZ
T i NSE3719CC ZZ iNSTRUCT;QN MANUAL USA N D BF
T i NSM3720CCZZ iNSTRUCToON MANUAL OTHERS N D BR
SPAKA7406CCZZ PACKiNG AD FOR CE158 N D EF
SPAKA7407CCZZ PACKiNG AD A FOR ATACHMENT N D DC
SPAKA7408CC ZZ PAC KiNG AD B FOR ATACHMENT N D OB
SPAKC7610CCZ Z PACKi NG CASE I N D AH
SPAKC74 1 lCCZ Z PAC Ki NG CASE (USA ONLY] N 0 All

28
Do not sale this PDF !!!
All and more about Sharp PC-1500 at http://www.PC-1500.info

Do not sale this PDF!!!

All and more about Sharp PC-1500 at http://www.PC-1500.info

SHARP CORPORATION
lndus1rial lnst1uments Group
Rcliabili1y &. Qualily CQnltQI O.;ip;ir!!l)~OI
Yamarokoriyama, Nara 639 · I I , Jap;in
October 1982 Prin1ad in Japan

Do not sale this PDF!!!