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Computer Architecture

The document contains Verilog code for behavioral modeling and testbenches of common logic gates - OR, NAND, NOR, XOR, XNOR and NOT gates. The behavioral models use always blocks to define the output based on input conditions. The testbenches initialize inputs, apply stimulus and monitor outputs over time.

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samsam67315
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© © All Rights Reserved
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Download as ODT, PDF, TXT or read online on Scribd
14 views

Computer Architecture

The document contains Verilog code for behavioral modeling and testbenches of common logic gates - OR, NAND, NOR, XOR, XNOR and NOT gates. The behavioral models use always blocks to define the output based on input conditions. The testbenches initialize inputs, apply stimulus and monitor outputs over time.

Uploaded by

samsam67315
Copyright
© © All Rights Reserved
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
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//OR gate with behavioral modeling

module orgate_veriloghdl(output reg Y, input A, B);


always @ (A or B)
begin
if (A == 1'b0 & B == 1'b0)
begin
Y = 1'b0;
end
else
Y = 1'b1;
end
endmodule

//OR gate with Testbench


module orgate_veriloghdl_test;
reg A, B;
wire Y;
orgate_veriloghdl Indtance0 (Y, A, B);
initial begin
A = 0; B = 0;
#300 A = 0; B = 1;
#300 A = 1; B = 0;
#300 A = 1; B = 1;
end
initial begin
$monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule
//NAND gate with
behavioral modeling
module
nandgate_veriloghdl
(output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b1 & B == 1'b1) begin
Y = 1'b0;
end
else
Y = 1'b1;
end
endmodule
//NAND gate with testbench
module nandgate_veriloghdl_test;
reg A, B;
wire Y;
nandgate_veriloghdl Indtance0 (Y, A, B);
initial begin
A = 0; B = 0;
#300 A = 0; B = 1;
#300 A = 1; B = 0;
#300 A = 1; B = 1;
end
initial begin
$monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

//NOR gate with


behavioral modeling
module
norgate_veriloghdl
(output reg Y, input A,
B);
always @ (A or B) begin
if (A == 1'b0 & B ==
1'b0) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule

//NOR Gate with testbench


module norgate_veriloghdl_test;
reg A, B;
wire Y;
norgate_veriloghdl Instance0 (Y, A, B);
initial begin
A = 0; B = 0;
#300 A = 0; B = 1;
#300 A = 1; B = 0;
#300 A = 1; B = 1;
end
initial begin
$monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
$dumpfile("dump.vcd");

$dumpvars();
end
endmodule

//XOR gate with behavioral modeling


module xorgate_veriloghdl (output reg Y, input A, B);
always @ (A or B) begin
if (A == 1'b0 & B == 1'b0) begin
Y = 1'b0;
end
else if (A == 1'b1 & B == 1'b1) begin
Y = 1'b0;
end
else
Y = 1'b1;
end
endmodule

//XOR gate with testbench


module xorgate_veriloghdl_test;
reg A, B;
wire Y;
xorgate_veriloghdl Instance0 (Y, A, B);
initial begin
A = 0; B = 0;
#300 A = 0; B = 1;
#300 A = 1; B = 0;
#300 A = 1; B = 1;
end
initial begin
$monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

//XNOR gate with behavioral


modeling
module
xnorgate_veriloghdl(output reg
Y, input A, B);
always @ (A or B) begin
if (A == 1'b0 & B == 1'b0) begin
Y = 1'b1;
end
else if (A == 1'b1 & B == 1'b1) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule

//XNOR gate with testbench


module xnorgate_veriloghdl_test;
reg A, B;wire Y;
xnorgate_veriloghdl Instance0 (Y, A, B);
initial begin
A = 0; B = 0;
#1 A = 0; B = 1;
#1 A = 1; B = 0;
#1 A = 1; B = 1;
end
initial begin
$monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

//NOT gate with


behavioral modeling
module
notgate_veriloghdl(output
reg Y, input A);
always @ (A) begin
if (A == 1'b0 ) begin
Y = 1'b1;
end
else if (A == 1'b1) begin
Y = 1'b0;
end
end
endmodule

//NOT Gate with testbench


module notgate_veriloghdl_test;
reg A;wire Y;
notgate_veriloghdl Instance0 (Y, A);
initial begin
A = 0;
#300 A = 1;
#300 A = 0;
end
initial begin
$monitor ("%t | A = %d| Y = %d", $time, A, Y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

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