Step-Down DC/DC Controller TLE 6389

Datasheet
1 Overview

1.1 Features
• Input voltage range from < 5V up to 60V
• Output voltage: 5V fixed or adjustable (7V to 15V) P-DSO-14-3, -8, -9, -11, 14
• Output voltage accuracy: 3%
• Output current up to 2.3A
• 100% maximum duty cycle
• Less than 120µA quiescent current at low loads1)
• 2µA max. shutdown current at device off
(TLE 6389-2 GV)
• Fixed 350kHz switching frequency
• Frequency synchronization input for external clocks
• Current Mode control scheme
• Integrated output under voltage Reset circuit
• On chip low battery detector (on chip comparator)
• Automotive temperature range -40°C to 150 °C

1)
Depending on external components.
RSENSE=
VIN 47mΩ M1 L1 = 47 µH V OUT

IOUT

C IN1 = COUT =
100 µF C BDS= D1 100 µF
220 nF

11 14 12 2 M1: Infineon BSO613SPV

Infineon BSP613P
BDS CS GDRV FB 3
13 D1: Motorola MBRD360
VS VOUT
RSI1= CIN2 = 9 L1: EPCOS B82479-A1473-M
400kΩ 220nF
7 SI
TLE6389-3 GV50 SO
8
Coilcraft DO3340P-473
CIN1 : Electrolythic
COMP
CIN2 : Ceramic
RSI2= SI_GND SI_ENABLE SYNC GND RO 2.2nF 680Ω COUT: Low ESR Tantalum
100kΩ 6 1 5 4 10
ON OFF

Type Package Description

TLE 6389-2 GV P-DSO-14-3 adjustable
TLE 6389-2 GV50 P-DSO-14-3 5V, RO-Hysteresis <<
TLE 6389-3 GV50 P-DSO-14-3 5V, RO-Hysteresis 1V

Datasheet Rev. 2.0 1 2006-08-24

 TLE 6389

1.2 Short functional description

The TLE 6389 step-down DC-DC switching controllers provide high efficiency over loads
ranging from 1mA up to 2.5A. A unique PWM/PFM control scheme operates with up to
a 100% duty cycle, resulting in very low dropout voltage. This control scheme eliminates
minimum load requirements and reduces the supply current under light loads to 120µA,
depending on dimensioning of external components. In addition the adjustable version
TLE6389-2 GV can be shut down via the Enable input reducing the input current to
<2µA. The TLE 6389 step-down controllers drive an external P-channel MOSFET,
allowing design flexibility for applications up to 12.5W of output power. A high switching
frequency and operation in continuous-conduction mode allow the use of tiny surface-
mount inductors. Output capacitor requirements are also reduced, minimizing PC board
area and system costs. The output voltage is preset at 5V (TLE6389-2 GV50 and
TLE6389-3 GV50) and adjustable for the TLE6389-2 GV. The version TLE6389-2 GV50
features a reset function with a threshold between 4.5V and 4.8V, including a small
hysteresis of typ. 50mV. In the version TLE6389-3 GV50 the device incorporates a reset
with a typ. 1V hysteresis. Input voltages of all TLE 6389 can be up to 60V.

1.3 Pin Configuration (top view)

ENABLE /
1 14 CS
SI_ENABLE

FB 2 13 VS

VOUT 3 12 GDRV

GND 4 P-D-SO-14 11 BDS

SYNC 5 10 RO

SI_GND 6 9 SO

SI 7 8 COMP

Datasheet Rev. 2.0 2 2006-08-24

 TLE 6389

1.4 Basic block diagram

ENA SI-
VS SI
BLE GND

RO
VOUT Battery Sense and
Internal Power Undervoltage Reset
Supply and
Biasing SO
BDS

FB PWM / PFM G
Driver DRV
Regulator

CS

COMP

Clock generator
Voltage SYNC
Reference
Block

TLE 6389GV
GND

Datasheet Rev. 2.0 3 2006-08-24

 TLE 6389

1.5 Pin Definitions and Functions

Pin No Symbol Function

SO-14
1 ENABLE Active-High enable input (only at adjustable version, TLE6389-2 GV)
for the device.
The device is shut down when ENABLE is driven low. In this shut down-
mode the reference, the output and the external MOSFET are turned off.
Connect to logic high for normal operation.
1 SI_ENA Active-High enable input (only at 5V version, TLE6389-2 GV50 and
BLE TLE6389-3 GV50) for SI_GND input.
SI_GND is switched to high impedance when SI_ENABLE is low. High
level at SI_ENABLE connects SI_GND to GND with low impedance. SO is
undefined when SI_ENABLE is low.
2 FB Feedback input.
1. For adjustable version (-2GV) connect this pin to an external voltage
divider from the output to GND (see the determining the output voltage,
application section).
2. At the 5V fixed output voltage version (-3GV50 and -2GV50) the FB is
connected internally to an on-chip voltage divider. It does not have to be
connected externally to the output.
3 VOUT Buck output voltage input.
Input for the internal supply. Connect always to the output of the buck
converter (output capacitor).
4 GND Ground connection. Analog signal ground.
5 SYNC Input for external frequency synchronization.
An external clock signal connected to this pin allows switching frequency
synchronization of the device. The internal oscillator is clocked then by the
frequency applied at the SYNC input.
6 SI_GND SI-Ground input.
Ground connection for SI comparator resistor divider. Depending on
SI_ENABLE this input is switched to high impedance or low ohmic to GND.
7 SI Sense comparator input.
Input of the low-battery comparator. This input is compared to an internal
1.25V reference where SO gives the result of the comparison. Can be
used for any comparison, not necessarily as battery sense.
8 COMP Compensation input.
Connect via RC-compensation network to GND.
9 SO Sense comparator output.
Open drain output from SI comparator at the adjustable version (TLE6389-
2 GV),
Pull down structure with an internal 20kΩ pull up resistor to VOUT at the
5V version (TLE6389-2 GV50 and TLE6389-3 GV50).

Datasheet Rev. 2.0 4 2006-08-24

 TLE 6389

Pin No Symbol Function

SO-14
10 RO Reset output.
Open drain output from undervoltage reset comparator at the adjustable
version (TLE6389-2 GV),
Pull down structure with an internal 20kΩ pull up resistor to VOUT at the
5V version (TLE6389-2 GV50 and TLE6389-3 GV50).
11 BDS Buck driver supply input.
Connect a ceramic capacitor between BDS and VS to generate clamped
gate-source voltage to supply the driver of the PMOS power stage.
12 GDRV Gate drive output.
Connect to the gate of the external P-Channel MOSFET. The voltage at
GDRV swings between the levels of VS and BDS.
13 VS Device supply input.
Connect a 220nF ceramic cap close to the pin in addition to the low ESR
tantalum input capacitance.
14 CS Current-sense input.
Connect current-sense resistor between VS and CS. The voltage drop
over the sense-resistor determines the peak current flowing in the buck
circuit. The external MOSFET is turned off when the peak current is
exceeded.

Datasheet Rev. 2.0 5 2006-08-24

 TLE 6389

2 Absolute Maximum Ratings

Item Parameter Symbol Limit Values Unit Remarks
min. max.
Device supply input VS
2.1 Voltage VVS -0.3 61 V –
2.2 Current IVS – – –
Current sense input CS
2.3 Voltage VCS -0.3 61 V |VVS – VCS|<0.3V
2.4 Current ICS – – –
Gate drive output GDRV
2.5 Voltage VGDRV – 0.3 61 V -0.3V<|VVS –
VGDRV|<6.8V;
-0.3V<|VBDS –
VGDRV|<6.8V
2.6 Current IGDRV – – – limited internally
Buck driver supply input BDS
2.7 Voltage VBDS – 0.3 61 V -0.3<|VVS –
VBDS|<6.8V
2.8 Current IBDS – – –
Feedback input FB
2.9 Voltage VFB – 0.3 6.8 V
2.10 Current IFB – – –
Enable input SI_ENABLE
2.11 Voltage VSI_ENAB – 0.3 61 V (TLE6389-2 GV50,
LE
TLE6389-3 GV50)

2.12 Current ISI_ENABL – – –

E

SI-Ground input SI_GND

2.13 Voltage VSI_GND – 0.3 61 V
2.14 Current ISI_GND – – –
Enable input ENABLE
2.15 Voltage VENABLE – 0.3 61 V (TLE6389-2 GV)
2.16 Current IENABLE – – –

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 TLE 6389

2 Absolute Maximum Ratings (cont’d)

Item Parameter Symbol Limit Values Unit Remarks
min. max.
Sense comparator input SI
2.17 Voltage VSI – 0.3 61 V
2.18 Current ISI – – –
Sense comparator output SO
2.19 Voltage VSO – 0.3 6.8 V
2.20 Current ISO – – – limited internally
Buck output voltage input VOUT
2.21 Voltage VVOUT – 0.3 15 V (TLE6389-2 GV)
2.22 Voltage VVOUT – 0.3 6.8 V (TLE6389-2 GV50,
TLE6389-3 GV50)
2.23 Current IVOUT – – mA
Compensation input COMP
2.24 Voltage VCOMP – 0.3 6.8 V
2.25 Current ICOMP – – mA
Reset output RO
2.26 Voltage VRO – 0.3 6.8 V
2.27 Current IRO – – mA limited internally
Frequency synchronization input SYNC
2.28 Voltage VSYNC – 0.3 6.8 V
2.29 Current ISYNC – – mA

ESD-Protection

2.30 Electrostatic discharge VESD –1.5 1.5 kV HBM1),

voltage pin VOUT
2.31 VESD -2 2 kV HBM1),
all pins except
VOUT
2.32 VESDCDM –500 500 V CDM2)

Datasheet Rev. 2.0 7 2006-08-24

 TLE 6389

2 Absolute Maximum Ratings (cont’d)

Item Parameter Symbol Limit Values Unit Remarks
min. max.

Temperatures

2.33 Junction temperature Tj – 40 150 °C –

2.34 Storage temperature Tstg – 50 150 °C –

1)
ESD susceptibility HBM according to EIA/JESD 22-A 114B.

2)
ESD susceptibility CDM according to JESD 22-C101.

Note: Stresses above the ones listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault
conditions described in the data sheet. Fault conditions are considered as
“outside” normal operating range. Protection functions are not designed for
continuous repetitive operation.

Datasheet Rev. 2.0 8 2006-08-24

 TLE 6389

3 Operating Range

Item Parameter Symbol Limit Values Unit Remarks

min. max.
3.1 Supply voltage range VVS 5 60 V
3.2 Output voltage adjust VOUT 7 15 V TLE 6389-2 GV
range TLE 6389-2 GV
3.3 Sense Resistor RSENSE 10 47 mΩ Calculation see
section 7
3.4 PMOS, on+off delay ton+off - tmin- ns tmin=VVOUT/
delay 3001) (VVS*fSW)
3.5 Buck driver supply CBDS 220 - nF
capacitor
3.6 Buck inductance L1 47 - µH recommended
value
3.7 Buck inductance L1 22 100 µH
3.8 Buck output capacitor COUT 100 - µF
3.9 Junction temperature Tj – 40 150 °C

Thermal Resistance

3.10 Junction ambient Rthj-a 140 K/W Footprint only

3.11 Junction pin Rthj-p 50 K/W –

1)
A too high PMOS on+off delay might cause an instable output voltage

Note: Within the functional range the IC operates as described in the circuit
description. The electrical characteristics are specified within the
conditions given in the related electrical characteristics table.

Datasheet Rev. 2.0 9 2006-08-24

 TLE 6389

4 Electrical Characteristics
5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Current Consumption1) TLE6389-2 GV50 and TLE6389-3 GV50

4.1 Current IVS 80 150 µA VVS = 48V;

consumption of VS PFM mode;
4.2 70 85 µA VVS = 13.5V;
PFM mode;
Tj = 25 °C
4.3 Current ISI_ENABLE 9 30 µA VVS = 48V;
consumption of VSI_ENABLE = 48V;
SI_ENABLE PFM mode;
4.4 Current IVOUT 95 130 µA VSI_ENABLE = L;
consumption of VVOUT = 5.5V;
VOUT VVS=13.5V;
PFM mode;
Tj = 25°C
4.5 140 220 µA VSI_ENABLE = H;
VVOUT = 5.5V;
VVS = 13.5V;
VSI > VSI, high;
PFM mode;
4.6 Current ISI 0.2 0.5 µA VVS = 13.5V;
consumption of SI VSI_ENABLE = H;
VSI = 10V ;
PFM mode;

Datasheet Rev. 2.0 10 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Current Consumption1) TLE6389-2 GV (variable)

4.7 Current IVS 80 150 µA VVS = 48V; VENABLE

consumption of VS = H; PFM mode;
VOUT > 7V
4.8 Current 70 85 µA VVS = 13.5V;
consumption of VS VENABLE = H; PFM
mode;
Tj = 25 °C;
VOUT > 7V
4.9 Current 2 µA VENABLE=0V;
consumption of VS Tj < 105°C
4.10 Current IEN 9 30 µA VVS = 48V; VENABLE
consumption of = H; PFM mode;
ENABLE
4.11 Current IVOUT 140 220 µA VOUT = 8V;
consumption of VVS = 13.5V;
VOUT VENABLE = H;
VSI > VSI, high; PFM
mode;
4.12 Current ISI 0.2 0.5 µA VVS = 13.5V;
consumption of SI VENABLE = H;
VSI = 10V ;
PFM mode;
Tj = 25°C
4.13 Current IFB 0.2 0.5 µA VVS = 13.5V;
consumption of FB VFB = 1.25V;
VENABLE = H; PFM
mode;
Tj = 25°C

Buck Controller

Datasheet Rev. 2.0 11 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
4.14 Output voltage VVOUT 4.85 5.00 5.15 V TLE6389-2 GV50,
TLE6389-3 GV50;
VVS=13.5V&
48V;PWM
IOUT = 0.5 to 2A;
RSENSE = 22mΩ;
RM1 = 0.25Ω;
RL1 = 0.1Ω;
4.15 4.75 5.00 5.25 V TLE6389-2 GV50,
TLE6389-3 GV50;
VVS = 24V;PFM;
IOUT = 15mA;
RSENSE = 22mΩ;
RM1 = 0.25Ω;
RL1 = 0.1Ω;
4.16 3.8 V TLE6389-3 GV50;
VVS decreasing
from 5.8V to 4.2V;
ILOAD = 0mA to
500mA;
RSENSE = 22mΩ;
RM1 = 0.4Ω;
RL1 = 0.1Ω;
4.17 FB threshold VFB, th 1.225 1.25 1.275 V TLE6389-2 GV
voltage
4.18 Output voltage VVOUT 9.7 10.0 10.3 V TLE6389-2 GV;
Calibrated
divider, see
section 7.3;
VVS = 13.5V & 48V;
IOUT = 0.5 to 2A;
PWM Mode;
RSENSE = 22mΩ;
RM1 = 0.25Ω;
RL1 = 0.1Ω;

Datasheet Rev. 2.0 12 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
4.19 Output voltage VVOUT 9.5 10.0 10.5 V TLE6389-2 GV;
Calibrated
divider, see
section 7.3;
VVS = 24V;
IOUT = 15mA;
PFM Mode;
RSENSE = 22mΩ;
RM1 = 0.25Ω;
RL1 = 0.1Ω;
4.20 Buck output voltage VVOUT VFB, th 7 V TLE6389-2 GV,
adjust range supplied by VS
only, complete
current to supply
the IC drawn from
VS,
no reset function 2)
4.21 Buck output voltage VVOUT 7 15 V TLE6389-2 GV,
adjust range current to supply
the IC drawn from
VS and VOUT, as
specified, 2)
4.22 Buck output voltage VVOUT 0.97* 1.03* TLE6389-2 GV,
accuracy VOUT_n VOUT_n PWM mode, 2)
om om

4.23 Buck output voltage VVOUT 0.95* 1.05* TLE6389-2 GV,

accuracy VOUT_n VOUT_n PFM mode, 2)
om om

4.24 Line regulation | ∆VVOUT | 35 mV TLE6389-2 GV50,

TLE6389-3 GV50,
VVS = 9V to 16V;
IOUT = 1A;
RSENSE=22mΩ;
PWM mode

Datasheet Rev. 2.0 13 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
4.25 Line regulation | ∆VVOUT | 50 mV TLE6389-2 GV50,
TLE6389-3 GV50,
VVS = 16V to 32V;
IOUT = 1A;
RSENSE=22mΩ;
PWM mode
4.26 Line regulation ∆VVOUT / 2.5 % TLE6389-2 GV,
VVOUT VVS = 12V to 36V;
VVOUT=10V
IOUT = 1A;
RSENSE=22mΩ;
PWM mode

Datasheet Rev. 2.0 14 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
4.27 Load regulation ∆VVOUT / 40 mV/ TLE6389-2 GV50,
∆ILOAD A TLE6389-3 GV50,
IOUT=0.5A to 2A;
VVS=5.8V&48V;
RSENSE=22mΩ
4.28 8* mV/ TLE6389-2 GV,
VOUT A IOUT = 0.5 to 2A;
_nom/ VVS=13.5V&4V;
V RSENSE=22mΩ
4.29 Gate driver, VVS – 0 0.2 V VENABLE/SI_ENABLE =
PMOS off VGDRV 5V
CBDS = 220 nF
CGDRV = 4.7nF
4.30 Gate driver, VVS – 6 8.2 V VENABLE/SI_ENABLE =
PMOS on VGDRV 5V
CBDS = 220 nF
CGDRV = 4.7nF3)
4.31 Gate driver, VVS – 2.75 4 V Decreasing (VVS-
UV lockout VBDS VBDS) until GDRV
is permanently at
VS level
4.32 Gate driver, IGDRV 1 A PMOS dependent;
2)
peak charging
current
4.33 Gate driver, IGDRV 1 A PMOS dependent;
2)
peak discharging
current
4.34 Gate driver, tr 45 60 ns VENABLE/SI_ENABLE =
gate voltage, rise 5V
time CBDS = 220 nF
CGDRV = 4.7nF

Datasheet Rev. 2.0 15 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
4.35 Gate driver, tf 50 65 ns VENABLE/SI_ENABLE =
gate voltage, fall 5V
time CBDS = 220 nF
CGDRV = 4.7nF
4.36 Peak current limit VLIM = 50 70 90 mV
threshold voltage VVS –
VCS
4.37 Oscillator frequency fOSC 290 360 420 kHz PWM mode only
4.38 Maximum duty dMAX 100 % PWM mode only
cycle
4.39 Minimum on time tMIN 220 400 ns PWM mode only
4.40 SYNC capture ∆fsync 250 530 kHz PWM mode only
range
2)
4.41 SYNC trigger level VSYNC,h 4.0 V
high
2)
4.42 SYNC trigger level 0.8 V
low

Reset Generator

4.43 Reset threshold VVOUT, RT 3.5 3.65 3.8 V TLE6389-3 GV50;

VVOUT decreasing
4.44 4.5 4.65 4.8 V TLE6389-3 GV50;
VVOUT increasing
4.45 Reset headroom VRT,HEAD 80 mV TLE6389-2 GV50;
VOUT(VS=6V,
ILOAD=1A)
-VVOUT,RT
4.46 Reset threshold VVOUT, RT 4.5 4.65 4.8 V TLE6389-2 GV50;
VVOUT increasing/
decreasing
4.47 Reset threshold ∆VVOUT, 50 mV TLE6389-2
hysteresis RT GV50;2)

Datasheet Rev. 2.0 16 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
4.48 Reset threshold VFB, RT 1.12 V TLE6389-2 GV;
VVOUT
decreasing
4.49 1.17 V TLE6389-2 GV;
VVOUTincreasing
4.50 Reset output pull up RRO 10 20 40 kΩ TLE6389-2 GV50,
resistor TLE6389-3 GV50;
Internally
connected to VOUT
4.51 Reset output High VRO, H 0.8* V TLE6389-2 GV50,
voltage VVOUT TLE6389-3
GV50;IRO=0mA
4.52 Reset output Low VRO,L 0.2 0.4 V IRO, L=1mA;
voltage 2.5V < VVOUT < VRT
4.53 Reset output Low VRO,L 0.2 0.4 V IRO, L=0.2mA;
voltage 1V < VVOUT < 2.5V
4.54 Reset delay time trd 17 21 25 ms TLE6389-2 GV
TLE6389-3 GV50
4.55 Reset delay time trd 70 82 100 ms TLE6389-2 GV50
2)
4.56 Reset reaction time trr 10 µs

Overvoltage Lockout

4.57 Overvoltage VVOUT, OV VOUT_ V TLE6389-2 GV50,

threshold nom/V TLE6389-3 GV50;
+0.1 VVOUTincreasing
4.58 Overvoltage VFB, OV VFB,th_ V TLE6389-2 GV;
nom/V
threshold +0.02
VVOUT increasing

ENABLE Input

4.59 Enable ON- VENABLE, 4.5 V

threshold ON

Datasheet Rev. 2.0 17 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
4.60 Enable OFF- VENABLE, 0.8 V
threshold OFF

SI_ENABLE Input

4.61 Enable ON- VENABLE, 4.5 V

threshold ON

4.62 Enable OFF- VENABLE, 0.8 V

threshold OFF

SI_GND Input

4.63 Switch ON RSW 50 100 230 Ω VSI_ENABLE=5V;

resistance ISI_GND = 3mA;

Battery Voltage Sense

4.64 Sense threshold VSI, low 1.22 1.25 1.28 V VVS decreasing
4.65 Sense threshold VSI, high 1.33 V VVS increasing
4.66 Sense threshold VSI, hys 50 80 120 mV
hysteresis
4.67 Sense output pull RSO 10 20 40 kΩ TLE6389-2 GV50,
up resistor TLE6389-3 GV50;
Internally
connected to
VVOUT
4.68 Sense out output VSO, H 0.8* V ISO, H=0mA
High voltage VVOUT

Datasheet Rev. 2.0 18 2006-08-24

 TLE 6389

4 Electrical Characteristics (cont’d)

5V< VVS <48V; - 40°C< Tj <150 °C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified

Item Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
4.69 Sense out output VSO, L 0.2 0.4 V ISO, L=1mA;
Low voltage 2.5V < VVOUT;
VSI < 1.13 V
4.70 0.4 VVOUT V ISOL=0.2mA;
/V 1V <VVOUT <2.5V;
VSI < 1.13 V

Thermal Shutdown

2)
4.71 Thermal shutdown TjSD > 175 200 °C
junction 150
temperature
2)
4.72 Temperature ∆T 30 K
hysteresis

1)
The device current measurements for IVS and IFB exclude MOSFET driver currents.

2)
Not subject to production test - specified by design

3)
≈
For 4V<VVS<6V: VGDRV 0V.

Datasheet Rev. 2.0 19 2006-08-24

 TLE 6389

5 Typical performance
characteristics
Current consumption IVS vs. temperature Tj Current consumption IVOUT vs. temperature
at enabled device and VVS=13.5V Tj at enabled device and VVOUT=5.5V
90 180
IVS IVOUT
µA µA
80 170

70 160

60 150

50 140

40 130

30 120

20 110
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj
°C °C

Current consumption IVS vs. temperature Tj Current consumption IVOUT vs. temperature
at enabled device and VVS=48V Tj at enabled device and VVOUT=10V(-2GV)
110 160
IVS IVOUT
µA µA
100 150

90 140

80 130

70 120

60 110

50 100

40 90
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj
°C °C

Datasheet Rev. 2.0 20 2006-08-24

 TLE 6389

Internal oscillator frequency fOSC vs. Peak current limit threshold voltage VLIM
temperature Tj vs. temperature Tj
380 110
fOSC VLIM

kHz mV
370 100

360 90

350 80

340 70

330 60

320 50

310 40
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Minimum on time tMIN (blanking) vs. Gate driver supply VVS - VBDS vs.
temperature Tj temperature Tj
350 8.6
tMIN VVS-VBDS

ns V
325 8.4

300 8.2

275 8.0

250 7.8

225 7.6

200 7.4

175 7.2
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Datasheet Rev. 2.0 21 2006-08-24

 TLE 6389

Output voltage VVOUT vs. temperature Tj in Lower Reset threshold VFB,RT vs.
PFM mode (VVS=24V,ILoad=15mA,-3GV50) temperature Tj (-2GV)
5.15 1.14
VVOUT VFB,RT

V V
5.10 1.13

5.05 1.12

5.00 1.11

4.95 1.10

4.90 1.09

4.85 1.08

4.80 1.07
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Lower Reset threshold VVOUT, RT vs. Internal pull up resistors RRO and RSO vs.
temperature Tj (-3GV50) temperature Tj (-3GV50)
3.72 45
VVOUT,RT RRO

V kΩ
3.70 40
RSO

kΩ
3.68 35

3.66 30

3.64 25

3.62 20

3.60 15

3.58 10
-50 -20 10 40 70 100 130 160 -50 -20 10 40 70 100 130 160
Tj Tj

°C °C

Datasheet Rev. 2.0 22 2006-08-24

 TLE 6389

Lower Sense threshold VSI, low vs. Output Voltage vs. Load Current,
temperature Tj TLE6389-2 GV50
1.28 7
V OUT TLE 6389-2 GV50
VSI,low
RSENSE = 50mΩ
V V VVS = 13.5V
1.27 6 App. Circuit Fig. 3

1.26 5

1.25 4

1.24 3

1.23 2

1.22 1

1.21 0
-50 -20 10 40 70 100 130 160 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75
Tj ILOAD
°C A

On resistance of SI_GND switch RSW vs. Output Current vs. Load Current,
temperature Tj TLE6389-3 GV50
280 7
RSW VOUT TLE 6389-3 GV50
RSENSE = 50mΩ
Ω V VVS = 13.5V
240 6 App. Circuit Fig. 3

200 5

160 4

120 3

80 2

40 1

0 0
-50 -20 10 40 70 100 130 160 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75
Tj ILOAD
°C A

Datasheet Rev. 2.0 23 2006-08-24

 TLE 6389

Output Voltage vs Load Current

1.4
VOUT TLE 6389-2 GV
RSENSE = 50mΩ
VOUT,nom VVS = 13.5V
1.2 App. Circuit Fig. 3

1.0

0.8

0.6

0.4

0.2

0
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75
ILOAD
A

Datasheet Rev. 2.0 24 2006-08-24

 TLE 6389

6 Detailed circuit description

In the following, some internal blocks of the TLE6389 are described in more detail. For
the right choice of the external components please refer to the section application
information.

6.1 PFM/PWM Step-down regulator

To meet the strict requirements in terms of current consumption demanded by all Body-
and 42V PowerNet applications a special PFM (Pulse Frequency Modulation) - PWM
(Pulse Width Modulation) control scheme for highest efficiency is implemented in the
TLE 6389 regulators. Under light load conditions the output voltage is able to increase
slightly and at a certain threshold the controller jumps into PFM mode. In this PFM
operation the PMOS is triggered with a certain on time (depending on input voltage,
output voltage, inductance- and sense resistor value) whenever the buck output voltage
decreases to the so called WAKE-threshold. The switching frequency of the step down
regulator is determined in the PFM mode by the load current. It increases with increasing
load current and turns finally to the fixed PWM frequency at a certain load current
depending on the input voltage, current sense resistor and inductance. The diagram
below shows the buck regulation circuit of the TLE 6389 .

VS CS VFB, OV VREF VREF VDIODE

+ - + - + -
Current- Over- Over-
sense Voltage Temp.
Amplifier Lockout Shutdown

VS

Blanking
VREF
+
>1
+ R
GDRV
-
S Q &
VFB
Error PWM
Amplifier Comparator
Level-
Wake- shift
Slope- VREF Comparator BDS
+

compensation PFM
-
VFB, WK MUX
PWM

SYNC

MODE
Oscillator

Figure 1 Buck control scheme

The TLE 6389 uses a slope-compensated peak current mode PWM control scheme in
which the feedback or output voltage of the step down circuit and the peak current of the
current through the PMOS are compared to form the OFF signal for the external PMOS.

Datasheet Rev. 2.0 25 2006-08-24

 TLE 6389

The ON-trigger is set periodically by the internal oscillator when acting in PWM mode
and is given by the output of the WAKE-comparator when operating in PFM mode. The
Multiplexer (MUX) is switched by the output of the MODE-detector which distinguishes
between PFM and PWM by tracking the output voltage (goto PFM) and by tracking the
gate trigger frequency (goto PWM). In PFM mode the peak current limit is reduced to
prevent overshoots at the output of the buck regulator. In order to avoid a gate turn off
signal due to the current peak caused by the parasitic capacitance of the catch diode the
blanking filter is necessary. The blanking time is set internally to 200ns and determines
(together with the PMOS turn on and turn off delay) the minimum duty cycle of the
device. In addition to the PFM/PWM regulation scheme an overvoltage lockout and
thermal protection are implemented to guarantee safe operation of the device and of the
supplied application circuit.

6.2 Battery voltage sense

To detect undervoltage conditions at the battery a sense comparator block is available
within the TLE 6389. The voltage at the SI input is compared to an internal reference of
typ. 1.25V. The output of the comparator drives a NMOS structure giving a low signal at
SO as soon as the voltage at SI decreases below this threshold. In the 5V fixed version
an internal pull up resistor is connected from the drain of the NMOS to the output of the
buck converter, in the variable version SO is open drain.
The sense in voltage divider can be switched to high impedance by a low signal at the
SI_ENABLE to avoid high current consumption to GND (TLE6389-2 GV50 and
TLE6389-3 GV50 only).
Of course the sense comparator can be used for any input voltage and does not have to
be used for the battery voltage sense only.

6.3 Undervoltage Reset

The output voltage is monitored continuously by the internal undervoltage reset
comparator. As soon as the output voltage decreases below the thresholds given in the
characteristics the NPN structure pulls RO low (latched). In the 5V fixed version an
internal pull up resistor is connected from the collector of the NPN to the output of the
buck converter, in the variable version RO is open collector.
At power up RO is kept low until the output voltage has reached its reset threshold and
stayed above this threshold for the power on reset delay time.

Datasheet Rev. 2.0 26 2006-08-24

 TLE 6389

7 Application information
Note: The following information is given as a hint for the implementation of the
device only and shall not be regarded as a description or warranty of a
certain functionality, condition or quality of the device.

7.1 General
The TLE 6389 step-down DC-DC controllers are designed primarily for use in
Automotive applications where high input voltage range requirements have to be met.
Using an external P-MOSFET and current-sense resistor allows design flexibility and the
improved efficiencies associated with high-performance P-channel MOSFETs. The
unique, peak current-limited, PWM/PFM control scheme gives these devices excellent
efficiency over wide load ranges, while drawing around 100µA current from the battery
under no load condition. This wide dynamic range optimizes the TLE 6389 for
automotive applications, where load currents can vary considerably as individual circuit
blocks are turned on and off to conserve energy. Operation to a 100% duty cycle allows
the lowest possible dropout voltage, maintaining operation during cold cranking. High
switching frequencies and a simple circuit topology minimize PC board area and
component costs.

7.2 Typical application circuits

Note: These are very simplified examples of an application circuit. The function
must be verified in the real application.
RSENSE=
VIN 47mΩ M1 L1 = 47 µH V OUT

IOUT

C IN1 = COUT =
100 µF C BDS= D1 100 µF
220 nF

11 14 12 2 M1: Infineon BSO613SPV

Infineon BSP613P
13 BDS CS GDRV FB 3
VOUT D1: Motorola MBRD360
VS
RSI1= CIN2 = TLE6389-2 GV50 SO
9 L1: EPCOS B82479-A1473-M
400kΩ 220nF Coilcraft DO3340P-473
7 SI TLE6389-3 GV50 COMP
8 CIN1 : Electrolythic
CIN2 : Ceramic
RSI2= SI_GND SI_ENABLE SYNC GND RO 2.2nF 680Ω COUT: Low ESR Tantalum
100kΩ 6 1 5 4 10
ON OFF

Figure 2 Application circuit TLE6389-2 GV50 and TLE6389-3 GV50

Datasheet Rev. 2.0 27 2006-08-24

 TLE 6389

RSENSE=
VIN 47mΩ M1 L1 = 47 µH V OUT

to e.g. 5V rail
C IN1 = COUT =
100 µF C BDS= D1 RSO=
100 µF
220 nF RRO=
20kΩ RFB1=
M1: Infineon BSO613SPV
11 14 12 3 330kΩ
Infineon BSP613P
13 BDS CS GDRV VOUT D1: Motorola MBRD360
VS SO 9 to µC L1: EPCOS B82479-A1473-M
RSI1= CIN2 =
Coilcraft DO3340P-473
400kΩ 220nF TLE6389-2 GV FB
2
2.2nF CIN1: Electrolythic
SI COMP
7 8 CIN2: Ceramic
RSI2= SI_GND ENABLE SYNC GND RO RFB2= COUT: Low ESR Tantalum
100kΩ 6 1 5 4 10 680Ω 47kΩ
ON OFF to µC

Figure 3 Application circuit TLE6389-2 GV

7.3 Output voltage at adjustable version - feedback divider

The output voltage is sensed either by an internal voltage divider connected to the VOUT
pin (TLE6389-2 GV50 and TLE6389-3 GV50, fixed 5V versions) or an external divider
from the Buck output voltage to the FB pin (TLE6389-2 GV, adjustable version). Pin
VOUT has to be connected always to the Buck converter output regardless of the
selected output voltage for the -2GV version.
To determine the resistors of the feedback divider for the desired output voltage VOUT at
the TLE6389-2 GV select RFB2 between 5kΩ and 500kΩ and obtain RFB1 with the
following formula:

V OUT
R FB1 = R FB2 ⋅  ---------------- – 1
V 
FB, th

VFB is the threshold of the error amplifier with its value of typical 1.25V which shows that
the output voltage can be adjusted in a range from 1.25 to 15V. However the integrated
Reset function will only be operational if the output voltage level is adjusted to >7V. Also

Datasheet Rev. 2.0 28 2006-08-24

 TLE 6389

the current consumption will be increased in PFM mode in the range between 1.25 and
7V.

7.4 SI_Enable
Connecting SI_ENABLE to 5V causes SI_GND to have low impedance. Thus the SI
comparator is in operation and can be used to monitor the battery voltage. SO output
signal is valid. Connecting SI_ENABLE to GND causes SI_GND to have high
impedance. Thus the SI comparator is not able to monitor the battery voltage. SO output
signal is invalid.

7.5 Battery sense comparator - voltage divider

The formula to calculate the resistor divider for the sense comparator is basically the
same as for the feedback divider in section before. With the selected resistor RSI2, the
desired threshold of the input voltage VIN, UV and the lower sense threshold VSI, low the
resistor RSI1 is given to:

V IN, UV 
R SI1 = R SI2 ⋅  ------------------
-–1
V 
SI, low

For high accuracy and low ohmic resistor divider values the On-resistance of the
SI_GND NMOS (typ. 100Ω) has to be added to RSI2.

7.6 Undervoltage reset - delay time

The diagram below shows the typical behavior of the reset output in dependency on the
input voltage VIN, the output voltage VVOUT or VFB.

Datasheet Rev. 2.0 29 2006-08-24

 TLE 6389

VIN

< trr t
VVOUT
VVOUT, RT
VFB VFB,RT

trr t

VRO trd trd trd trd

t
thermal under over
shutdown voltage load

Figure 4 Reset timing

7.7 100% duty-cycle operation and dropout

The TLE 6389 operates with a duty cycle up to 100%. This feature allows to operate with
the lowest possible drop voltage at low battery voltage as it occurs at cold cranking. The
MOSFET is turned on continuously when the supply voltage approaches the output
voltage level, conventional switching regulators with less than 100% duty cycle would fail
in that case.
The drop- or dropout voltage is defined as the difference between the input and output
voltage levels when the input is low enough to drop the output out of regulation. Dropout
depends on the MOSFET drain-to-source on-resistance, the current-sense resistor and
the inductor series resistance. It is proportional to the load current:

V drop = I LOAD ⋅ ( R DS ( ON )PMOS + R SENSE + R INDUCTANCE )

Datasheet Rev. 2.0 30 2006-08-24

 TLE 6389

7.8 SYNC Input and Frequency Control

The TLE 6389’s internal oscillator is set for a fixed PWM switching frequency of 360kHz
or can be synchronized to an external clock at the SYNC pin. When the internal clock is
used SYNC has to be connected to GND. SYNC is a negative-edge triggered input that
allows synchronization to an external frequency ranging between 270kHz and 530kHz.
When SYNC is clocked by an external signal, the converter operates in PWM mode until
the load current drops below the PWM to PFM threshold. Thereafter the converter
continues operation in PFM mode.

7.9 Shutdown Mode

Connecting ENABLE to GND places the TLE6389-2 GV in shutdown mode. In
shutdown, the reference, control circuitry, external switching MOSFET, and the oscillator
are turned off and the output falls to 0V. Connect ENABLE to voltages higher than 4.5V
for normal operation. As this input operates analog the voltage applied at this pin should
have a slope of 0.5V/3µs to avoid undefined states within the device.

7.10 Buck converter circuit

A typical choice of external components for the buck converter circuit is given in figure
2 and 3. For basic operation of the buck converter the input capacitors CIN1, CIN2, the
driver supply capacitor CBDS, the sense resistor RSENSE, the PMOS device, the catch
diode D1, the inductance L1 and the output capacitor COUT are necessary. In addition for
low electromagnetic emission a Pi-filter at the input and/or a small resistor in the path
between GDRV and the gate of the PMOS may be necessary.

7.10.1 Buck inductance (L1) selection in terms of ripple current:

The internal PWM/PFM control loop includes a slope compensation for stable operation
in PWM mode. This slope compensation is optimized for inductance values of 47µH and
Sense resistor values of 47mΩ for the 5V output voltage versions. When choosing an
inductance different from 47µH the Sense resistor has to be changed also:

R SENSE 3Ω
------------------- = (0,5...1,0 ) ×10 ----
L1 H

Increasing this ratio above 1000 Ω/H may result in sub harmonic oscillations as well-
known for peak current mode regulators without integrated slope compensation.

Datasheet Rev. 2.0 31 2006-08-24

 TLE 6389

To achieve the same effect of slope compensation in the adjustable voltage version also
the inductance in µH is given by

H
 2,0 × 10 – 4 ⋅ -------- H
- ⋅ V OUT ⋅ R SENSE < L1 <  4,0 × 10 ⋅ --------- ⋅ V ⋅ R SENSE
–4
 VΩ   VΩ OUT 

The inductance value determines together with the input voltage, the output voltage and
the switching frequency the current ripple which occurs during normal operation of the
step down converter. This current ripple is important for the all over ripple at the output
of the switching converter.

( V IN – V OUT ) ⋅ V OUT
∆I = ------------------------------------------------------
f SW ⋅ V IN ⋅ L1

In this equation fsw is the actual switching frequency of the device, given either by the
internal oscillator or by an external source connected to the SYNC pin. When picking
finally the inductance of a certain supplier (Epcos, Coilcraft etc.) the saturation current
has to be considered. The saturation current value of the desired inductance has to be
higher than the maximum peak current which can appear in the actual application.

7.10.2 Determining the current limit

The peak current which the buck converter is able to provide is determined by the peak
current limit threshold voltage VLIM and the sense resistor RSENSE. With a maximum peak
current given by the application (IPEAK, PWM=ILOAD+0.5∆I) the sense resistor is calculated
to

V LIM
R SENSE = ------------------------------------
-
2 ⋅ I PEAK, PWM

The equation above takes account for the foldback characteristic of the current limit as
shown in the Fig. ’Output Voltage vs. Load Current’ on page 24/25 by introducing a factor
of 2. It must be assured by correct dimensioning of RSENSE that the load current doesn’t
reach the foldback part of the characteristic curve.

Datasheet Rev. 2.0 32 2006-08-24

 TLE 6389

7.10.3 PFM and PWM thresholds

The crossover thresholds PFM to PWM and vice versa strongly depend on the input
voltage VIN, the Buck converter inductance L1, the sense resistor value RSENSE and the
turn on and turn off delays of the external PMOS.
For more details on the PFM to PWM and PWM to PFM thresholds please refer to the
application note “TLE6389 - Determining PFM/PWM current thresholds”.

7.10.4 Buck output capacitor (COUT) selection:

The choice of the output capacitor effects straight to the minimum achievable ripple
which is seen at the output of the buck converter. In continuous conduction mode the
ripple of the output voltage can be estimated by the following equation:

1
V Ripple = ∆I ⋅  RESRCOUT + ------------------------------------
 8⋅f ⋅C 
SW OUT

From the formula it is recognized that the ESR has a big influence in the total ripple at
the output, so low ESR tantalum capacitors are recommended for the application.
One other important thing to note are the requirements for the resonant frequency of the
output LC-combination. The choice of the components L and C have to meet also the
specified range given in section 3 otherwise instabilities of the regulation loop might
occur.

7.10.5 Input capacitor (CIN1) selection:

At high load currents, where the current through the inductance flows continuously, the
input capacitor is exposed to a square wave current with its duty cycle VOUT/VI. To
prevent a high ripple to the battery line a capacitor with low ESR should be used. The
maximum RMS current which the capacitor has to withstand is calculated to:

V OUT 1 ∆I 2
I RMS = I LOAD ⋅ -------------- ⋅ 1 + --- ⋅  -----------------------
V IN 3 2 ⋅ I LOAD

For low ESR an e.g. Al-electrolytic capacitance in parallel to an ceramic capacitance

could be used.

Datasheet Rev. 2.0 33 2006-08-24

 TLE 6389

7.10.6 Freewheeling diode / catch diode (D1)

For lowest power loss in the freewheeling path Schottky diodes are recommended. With
those types the reverse recovery charge is negligible and a fast hand over from
freewheeling to forward conduction mode is possible. Depending on the application (12V
battery systems) 40V types could be also used instead of the 60V diodes. Also for high
temperature operation select a Schottky-diode with low reverse leakage.
A fast recovery diode with recovery times in the range of 30ns can be also used if smaller
junction capacitance values (smaller spikes) are desired.

7.10.7 Buck driver supply capacitor (CBDS)

The voltage at the ceramic capacitor is clamped internally to 7V, a ceramic type with a
minimum of 220nF and voltage class 16V would be sufficient.

7.10.8 Input pi-filter components for reduced EME

At the input of Buck converters a square wave current is observed causing
electromagnetical interference on the battery line. The emission to the battery line
consists on one hand of components of the switching frequency (fundamental wave) and
its harmonics and on the other hand of the high frequency components derived from the
current slope. For proper attenuation of those interferers a π-type input filter structure is
recommended which is built up with inductive and capacitive components in addition to
the Input caps CIN1 and CIN2. The inductance can be chosen up to the value of the Buck
converter inductance, higher values might not be necessary, the additional capacitance
should be a ceramic type in the range up to 100nF.
Inexpensive input filters show due to their parasitrics a notch filter characteristic, which
means basically that the low pass filter acts from a certain frequency as a high pass filter
and means further that the high frequency components are not attenuated properly. To
slower down the slopes at the gate of the PMOS switch and get down the emission in the
high frequency range a small gate resistor can be put between GDRV and the PMOS
gate.

7.10.9 Frequency compensation

The external frequency compensation pin should be connected via a 2.2nF (>10V)
ceramic capacitor and a 680 Ω (1/8W) resistor to GND. This node should be kept free
from switching noise.

Datasheet Rev. 2.0 34 2006-08-24

 TLE 6389

7.11 Components recommendation - overview

Device Type Supplier Remark

CIN1 Electrolytic /Foil type various 100µF, 60V
CIN2 Ceramic various 220nF, 60V
L1 B82464-A4473 EPCOS 47µH, 1.6A, 145mΩ
B82479-A1473-M EPCOS 47µH, 3.5A, 47mΩ
DO3340P-473 Coilcraft 47µH, 3.8A, 110mΩ
DO5022P-683 Coilcraft 68µH, 3.5A, 130mΩ
DS5022P-473 Coilcraft 47µH, 4.0A, 97mΩ
M1 BSO 613SPV Infineon 60V, 3.44A, 130mΩ, NL
BSP 613P Infineon 60V, 2.9A, 130mΩ, NL
SPD09P06PL Infineon 60V, 9A, 250mΩ, LL
CBDS Ceramic various 220nF, 16V
D1 MBRD360 Motorola Schottky, 60V, 3A
MBRD340 Motorola Schottky, 40V, 3A
SS34 various Schottky, 40V, 3A
COUT B45197-A2107 EPCOS Low ESR Tantalum, 100µF, 10V
CCOMP Ceramic various see 7.10.9.

7.12 Layout recommendation

The most sensitive points for Buck converters - when considering the layout - are the
nodes at the input, output and the gate of the PMOS transistor and the feedback path.
For proper operation and to avoid stray inductance paths the external catch diode, the
Buck inductance and the input capacitor CIN1 have to be connected as close as possible
to the PMOS device. Also the GDRV path from the controller to the MosFet has to be as
short as possible. Best suitable for the connection of the cathode of the catch diode and
one terminal of the inductance would be a small plain located next to the drain of the
PMOS.
The GND connection of the catch diode must be also as short as possible. In general the
GND level should be implemented as surface area over the whole PCB as second layer,
if necessary as third layer. The feedback path has to be well grounded also, a ceramic
capacitance might help in addition to the output cap to avoid spikes.

Datasheet Rev. 2.0 35 2006-08-24

 TLE 6389

To obtain the optimum filter capability of the input pi-filter it has to be located also as
close as possible to the input. To filter the supply input of the device (VS) the ceramic cap
should be connected directly to the pin.
As a guideline an EMC optimized application board / layout is available.

Datasheet Rev. 2.0 36 2006-08-24

 TLE 6389

8 Package Outlines:

Dimensions in mm

Datasheet Rev. 2.0 37 2006-08-24

 TLE 6389

Edition 2005-09-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 8/24/06.
All Rights Reserved.

Attention please!
The information given in this data sheet shall in no event be regarded as a guarantee of
conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples
or hints given herein, any typical values stated herein and/or any information regarding
the application of the device, Infineon Technologies hereby disclaims any and all
warranties and liabilities of any kind, including without limitation warranties of non-
infringement of intellectual property rights of any third party.

Information
For further information on technology, delivery terms and conditions and prices please
contact your nearest Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements components may contain dangerous substances. For
information on the types in question please contact your nearest Infineon Technologies
Office.
Infineon Technologies Components may only be used in life-support devices or systems
with the express written approval of Infineon Technologies, if a failure of such
components can reasonably be expected to cause the failure of that life-support device
or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/
or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume
that the health of the user or other persons may be endangered.

Datasheet Rev. 2.0 38 2006-08-24