Lecture 6

Lecture: Pipelining Extensions
• Topics: bypassing, deeper pipelines, control hazards
1
RISC/CISC Loads/Stores
Registers and memory

Complex and reduced instrs 2
Format of a load/store
Pipeline Summary
RR ALU DM RW
ADD R3  R1, R2 Rd R1,R2 R1+R2 -- Wr R3
BEZ R1, [R5] Rd R1, R5 -- -- --

Compare, Set PC
LD R6  8[R3] Rd R3 R3+8 Get data Wr R6
ST R6  8[R3] Rd R3,R6 R3+8 Wr data --
3
Problem 4
• For the following code sequence, show how the instrs
flow through the pipeline:
ADD R3  R1, R2
LD R7  8[R6]
ST R9  4[R8]
BEZ R4, [R5]
4
Problem 4
• For the following code sequence, show how the instrs
flow through the pipeline:
ADD R3  R1, R2
LD R7  8[R6]
ST R9  4[R8]
BEZ R4, [R5]
ADD ADD ADD ADD ADD

LD LD LD LD LD
ST ST ST ST
BEZ BEZ
5
Hazards
• Structural hazards: different instructions in different stages

(or the same stage) conflicting for the same resource
• Data hazards: an instruction cannot continue because it

needs a value that has not yet been generated by an
earlier instruction
• Control hazard: fetch cannot continue because it does

not know the outcome of an earlier branch – special case
of a data hazard – separate category because they are
treated in different ways
6
Structural Hazards
• Example: a unified instruction and data cache 

stage 4 (MEM) and stage 1 (IF) can never coincide
• The later instruction and all its successors are delayed

until a cycle is found when the resource is free  these
are pipeline bubbles
• Structural hazards are easy to eliminate – increase the

number of resources (for example, implement a separate
instruction and data cache)
7
Problem 5
• Show the instruction occupying each stage in each cycle (no bypassing)
if I1 is R1+R2R3 and I2 is R3+R4R5 and I3 is R7+R8R9
CYC-1 CYC-2 CYC-3 CYC-4 CYC-5 CYC-6 CYC-7 CYC-8
IF IF IF IF IF IF IF IF
D/R D/R D/R D/R D/R D/R D/R D/R
ALU ALU ALU ALU ALU ALU ALU ALU
DM DM DM DM DM DM DM DM
RW RW RW RW RW RW RW RW 8
Problem 5
• Show the instruction occupying each stage in each cycle (no bypassing)
if I1 is R1+R2R3 and I2 is R3+R4R5 and I3 is R7+R8R9
I1 I2 I3 I3 I3 I4 I5
I1 I2 I2 I2 I3 I4
I1 I2 I3
I1 I2 I3
I1 I2
Bypassing: 5-Stage Pipeline
PC/L1 L2 L3 L4 L5
10
Source: H&P textbook
Problem 6
• Show the instruction occupying each stage in each cycle (with bypassing)
if I1 is R1+R2R3 and I2 is R3+R4R5 and I3 is R3+R8R9.
Identify the input latch for each input operand.
Problem 6
• Show the instruction occupying each stage in each cycle (with bypassing)
if I1 is R1+R2R3 and I2 is R3+R4R5 and I3 is R3+R8R9.
Identify the input latch for each input operand.
I1 I2 I3 I4 I5
I1 I2 I3 I4
L3 L3 L4 L3 L5 L3
I1 I2 I3
I1 I2 I3
RW RW RW RW RW RW RW RW
I1 I2 I3
Pipeline Implementation
• Signals for the muxes have to be generated – some of this can happen during ID
• Need look-up tables in decode stage to identify situations that merit bypassing/stalling
– the number of inputs to the muxes goes up
13
Problem 7
• For the 5-stage pipeline (RR and RW take half a cycle)

D/
IF AL DM RW
RR
• For the following pairs of instructions, how many stalls will the 2nd
instruction experience (with and without bypassing)?
 ADD R3  R1+R2
ADD R5  R3+R4
 LD R2  [R1]
ADD R4  R2+R3
 LD R2  [R1]
SD R3  [R2]
 LD R2  [R1]
SD R2  [R3]
14
Problem 7
• For the 5-stage pipeline (RR and RW take half a cycle)

D/
IF AL DM RW
RR
• For the following pairs of instructions, how many stalls will the 2nd
instruction experience (with and without bypassing)?
 ADD R3  R1+R2
ADD R5  R3+R4 without: 2 with: 0
 LD R2  [R1]
ADD R4  R2+R3 without: 2 with: 1
 LD R2  [R1]
SD R3  [R2] without: 2 with: 1
 LD R2  [R1]
SD R2  [R3] without: 2 with: 0
15
Summary
• For the 5-stage pipeline, bypassing can eliminate delays

between the following example pairs of instructions:
add/sub R1, R2, R3
add/sub/lw/sw R4, R1, R5
lw R1, 8(R2)
sw R1, 4(R3)
• The following pairs of instructions will have intermediate

stalls:
lw R1, 8(R2)
add/sub/lw R3, R1, R4 or sw R3, 8(R1)
fmul F1, F2, F3

fadd F5, F1, F4
16
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Lecture: Pipelining Extensions

• Topics: bypassing, deeper pipelines, control hazards

Registers and memory

ADD R3  R1, R2 Rd R1,R2 R1+R2 -- Wr R3

BEZ R1, [R5] Rd R1, R5 -- -- --

LD R6  8[R3] Rd R3 R3+8 Get data Wr R6

ST R6  8[R3] Rd R3,R6 R3+8 Wr data --

ADD ADD ADD ADD ADD

• Structural hazards: different instructions in different stages

• Data hazards: an instruction cannot continue because it

• Control hazard: fetch cannot continue because it does

• Example: a unified instruction and data cache 

• The later instruction and all its successors are delayed

• Structural hazards are easy to eliminate – increase the

D/R D/R D/R D/R D/R D/R D/R D/R

ALU ALU ALU ALU ALU ALU ALU ALU

D/R D/R D/R D/R D/R D/R D/R D/R

ALU ALU ALU ALU ALU ALU ALU ALU

• For the 5-stage pipeline (RR and RW take half a cycle)

• For the 5-stage pipeline (RR and RW take half a cycle)

• For the 5-stage pipeline, bypassing can eliminate delays

• The following pairs of instructions will have intermediate

fmul F1, F2, F3

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