COMPUTER ORGANIZATION AND

ARCHITECTURE
BY
Dr.Anisha P Rodrigues
Assistant Professor
Department of Computer Science and Engineering
NMAMIT,Nitte

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Unit 3

Basic Processing Unit

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Fundamental Concepts
◼ Processor fetches one instruction at a time and perform
the operation specified.
◼ Instructions are fetched from successive memory
locations until a branch, or a jump instruction is
encountered.
◼ Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
◼ Instruction Register (IR) holds the instruction fetched
from memory

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Executing an Instruction
◼ Fetch the contents of the memory location pointed to by
the PC. The contents of this location are loaded into the
IR (fetch phase)
❑ IR← [[PC]]

◼ Assuming that an instruction is 4bytes long, increment

the contents of the PC by 4 to point to the next
instruction.(fetch phase)
❑ PC← [PC] + 4

◼ Carry out the actions specified by the instruction in the

IR (execution phase)

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
 Processor Organization

MDR HAS
TWO
INPUTS
AND TWO
OUTPUTS

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Internal organization of the processor
◼ ALU – Used to perform arithmetic and logical
operation.
◼ Registers for temporary storage

◼ Various digital circuits for executing different

microoperations.(Gates,MUX,decoders,counters).

◼ Internal path for movement of data between ALU

and registers.

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
◼ PC:
❑ Keeps track of execution of a program

❑ Contains the memory address of the next instruction to be

fetched and executed.

◼ MAR:
❑ Holds the address of the location to be accessed.

❑ Input of MAR is connected to Internal bus and an Output to

external bus.
◼ MDR:
❑ Contains data to be written into or read out of the addressed

location.
❑ It has 2 inputs and 2 Outputs.

❑ Data can be loaded into MDR either from memory bus or from

internal processor bus.

◼ The data and address lines are connected to the internal bus via
MDR and MAR
Dr. Anisha P Rodrigues, Dept of
11/26/2021 CSE,NMAMIT, Nitte
◼ Registers:
❑ The processor registers R0 to Rn-1 vary considerably from one
processor to another.
❑ Registers are provided for general purpose, used by
programmer.
❑ Registers Y,Z &TEMP are temporary registers used by
processor during the execution of some instruction.
◼ Multiplexer:
❑ Select either the output of the register Y or a constant value 4 to
be provided as input A of the ALU.
❑ Constant 4 is used by the processor to increment the contents of
PC.
◼ Data Path:
❑ The registers, ALU and interconnecting bus are collectively
referred to as the data path.

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Executing an Instruction
◼ Execution of an instruction involves one or more of the
following operations:

❑ Register Transfers: Transfer a word of data from one processor

register to another or to the ALU.

❑ ALU operations: Perform an arithmetic or a logic operation and

store the result in a processor register.

❑ Load operation: Fetch the contents of a given memory location

and load them into a processor register.

❑ Store operation: Store a word of data from a processor register

into a given memory location.
Dr. Anisha P Rodrigues, Dept of
11/26/2021 CSE,NMAMIT, Nitte
Register Transfers

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
◼ The input and output gates for register Ri are
controlled by signals Riin and Riout .

◼ Riin is set to1 – data available on internal bus

are loaded into Ri.

◼ Riout is set to1 – the contents of register are

placed on the bus.

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Data transfer between two registers
Example:
Transfer the contents of R1 to R4.
1. Enable output of register R1 by setting
R1out=1. This places the contents of R1 on the
processor bus.

2. Enable input of register R4 by setting R4in=1.

This loads the data from the processor bus into
register R4.

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Performing an Arithmetic or Logic
Operation
◼ The ALU is a combinational circuit that has no internal
storage.
◼ ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.

◼ What is the sequence of operations to add the

contents of register R1 to those of R2 and store the
result in R3?

◼ i.e. Add R1, R2, R3

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
◼ Step 1: Output of the register R1 and input of the register
Y are enabled, causing the contents of R1 to be
transferred to Y.

◼ Step 2: The multiplexer’s select signal is set to select Y

causing the multiplexer to gate the contents of register Y
to input A of the ALU.

◼ Step 3: The contents of Z are transferred to the

destination register R3.

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
 Add R1, R2, R3
1.R1out, Yin
2.R2out, SelectY, Add, Zin
3.Zout, R3in

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Load Operation - Fetching a Word from
Memory
◼ To fetch a word of information from memory, the
processor has to specify the address of the memory
location where this information is stored and request a
read operation.
◼ The processor transfers the required address to MAR
whose output is connected to the address lines of the
memory bus.
◼ At the same time, processor uses the control lines of the
memory bus to indicate that a read operation is needed.
◼ When requested data is received from the memory they
are stored in register MDR , from where they can be
transferred to other register in the processor.
 Figure 7.4. Connection and control signals for register MDR.
◼ It has 4 control signals.
◼ MDRin and MDRout control the connection to the internal
bus
◼ MDRinE and MDRoutE control the connection to the
external bus
Dr. Anisha P Rodrigues, Dept of
11/26/2021 CSE,NMAMIT, Nitte
Fetching a Word from Memory
◼ The response time of each memory access varies
◼ To accommodate this, the processor waits until it
receives an indication that the requested operation has
been completed (Memory-Function-Completed, MFC).

◼ Move (R1), R2
➢ MAR ← [R1]
➢ Start a Read operation on the memory bus
➢ Wait for the MFC response from the memory
R1out, MARin, Read
➢ Load MDR from the memory bus
MDRinE,WMFC
➢ R2 ← [MDR]
MDRout, R2in
 MDRinE

Data

MFC

MDR out

Figure 7.5. Timing of a memory Read operation.

Timing
MAR ← [R1]
Assume MAR
is always available
on the address lines
of the memory bus. Start a Read operation on the memory bus

Wait for the MFC response from the memory

Load MDR from the memory bus

R2 ← [MDR]
Storing a word in memory

◼ Move R2,(R1)

1. R1out, MARin
2. R2out, MDRin, Write
3. MDRoutE, WMFC
Execution of a Complete Instruction

◼ Add (R3), R1
❑ Fetch the instruction
❑ Fetch the first operand (the contents of the
memory location pointed to by R3)
❑ Perform the addition
❑ Load the result into R1
 Step

1
Action
Execution of a Complete Instruction
PCout , MAR in , Read, Select4,A dd, Zin
2 Zout , PCin , Y in , WMF C
3 MDR out , IR in
4 R3out , MAR in , Read
5 R1out , Y in , WMF C
6 MDR out , SelectY,Add, Zin
7 Zout , R1 in , End

Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.

Add (R3), R1
Execution of Branch Instructions

◼ A branch instruction replaces the contents of PC with the

branch target address, which is usually obtained by
adding an offset X given in the branch instruction.

◼ The offset X is usually the difference between the branch

target address and the address immediately following
the branch instruction.

❑ Unconditional branch – Jump instructions

❑ Conditional branch
Execution of unconditional Branch Instruction

Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in
4 Offset-field-of-IR out, Select Y, Add, Zin
5 Z out , PC in , End

Figure 7.7(a). Control sequence for an unconditional branch instruction.

Execution of conditional Branch Instruction
Example : Branch <0 for branch on negative case(N=1)

Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in
4 Offset-field-of-IR out, Select Y, Add, Z in , If N=0 then End
5 Z out , PC in , End

Figure 7.7(b). Control sequence for an unconditional branch instruction.

If N=1 then branch is taken; execute an instruction from branch target.
N=0 branch is not taken; execute a sequentially next instruction.
Multiple-Bus Organization
◼ General purpose registers are combined into a single
block called register file.

◼ Two output ports allow the contents of two different

registers to be accessed simultaneously and have their
contents placed on buses A and B.
◼ Third port allows the data on bus C to be loaded into a
third register during the same clock cycle.

◼ Bus A & B are used to transfer the source operands to A

& B inputs of the ALU.
◼ The result of ALU operation is transferred to the
destination over the bus C.
◼ ALU may simply pass one of its 2 input operands
unmodified to bus C.

◼ The ALU control signals for such an operation R=A or

R=B.

◼ Incrementer unit is used to increment the PC by 4.

◼ Using the incrementer eliminates the need to add the

constant value 4 to the PC using the main ALU.

◼ The source for the constant 4 at the ALU input

multiplexer can be used to increment other address
such as loadmultiple & storemultiple
 Multiple-Bus Organization
◼ Add R4, R5, R6

Control sequence for the instruction Add R4,R5,R6,

on three-bus organization

Step Action

1 PC out, R=B, MAR in , Read, IncPC

2 WMF C
3 MDR outB , R=B, IR in

4 R4 outA , R5 outB , SelectA, Add, R6 in , End

Quiz
◼ What is the control
sequence for
execution of the
instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)
Hardwired Control
Overview
◼ To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.

◼ Computer designers use a wide variety of

technology to solve this problem

◼ This approach fall in two categories: hardwired

control and microprogrammed control
◼ Hardwired system can operate at high speed; but with
little flexibility.
◼ The control unit uses a fixed logic circuit to interpret
instructions and generate sequence of control signals
from them.
◼ Each steps in this sequence is completed in one clock
cycle.
◼ A counter may be used to keep the track of the control
steps (refer fig in next slide)
◼ Each count of this counter corresponds to one control
step
The required control signals are determined by the
following information.
1. contents of the control step counter
2. contents of the instruction register
3. contents of the condition code flags
4. External input signals such as MFC and interrupt
request.
Hardwired Control Unit Organization
such as MFC,
interrupt requests
◼ The decoder/encoder block diagram is a combinational
circuit that generate the required control outputs,
depending on the state of all its inputs.

◼ In the figure in next slide the decoding and encoding

functions are separated.

◼ The step decoder provide a separate signal line for each

step, in the control sequence.
◼ The output of the instruction decoder consists of a
separate line for each machine instruction.

◼ For any instruction loaded in the IR, one of the output

lines INS1 through INSm is set to 1, and all other lines are
set to 0.

◼ The encoder generate appropriate control signals yin,

pcout , Add, End and so on by combining the input
signals.
Detailed Block Diagram
 Example: Generation of Zin by the encoder in a
signal for the single-bus processor
◼ Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Zin is asserted during time slot T1 for all instructions, during T6 for an Add instruction,
during T4 for an unconditional branch instruction, and son
Generating End control signal
◼ End = T7 • ADD + T5 • BR + ( T5 • N + T4 • Nˡ ) • BRN +…

The END signals starts a new instruction fetch cycle by resetting

the control step counter to its starting value.
◼ RUN ,set to 1, causes the counter to be
incremented by 1 at the end of every clock
cycle

◼ when it set to 0 the counter stop counting.

◼ This is needed whenever the WMFC signal is

issued.
Microprogrammed Control
Overview
◼ Control signals are generated by a program similar to
MDRout

WMFC
MAR in

Select
Read
PCout

R1out

R3out
Micro -

End
PCin

R1in
Add

Z out
IRin
Yin

Zin
instruction

1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0

machine language programs.

2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An example of microinstructions for Figure 7.6.

◼ Control Word (CW); microroutine; microinstruction

Overview Step

1
2
3
4
5
6
7
Action

PCout , MAR in , Read, Select4,A dd, Zin

Zout , PCin , Y in , WMF C
MDR out , IR in
R3out , MAR in , Read
R1out , Y in , WMF C
MDR out , SelectY,Add, Zin
Zout , R1 in , End

Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.

◼ Control Word (CW) is a word whose individual bits
represent various control signals.

◼ Every instruction will need a sequence of CWs for its

execution.

◼ At every step, some control signals are asserted (=1)

and all others are 0

◼ Sequence of CWs for an instruction forms the micro

routine for that instruction.

◼ Each CW in this micro routine is referred to as a

microinstruction.
◼ Every instruction will have its own microroutine
which is made up of microinstructions.

◼ Microroutines for all instructions in the instruction

set of a computer are stored in a special
memory called Control Store.

◼ Control signals are generated by sequentially

reading the CWs of the corresponding
microroutine from the control store.
Basic organization of a microprogrammed control unit
◼ Microprogram counter (µPC) is used to read
CWs from control store sequentially.
◼ When a new instruction is loaded into IR,
starting address generator generates the
starting address of the microroutine.
◼ This address is loaded into the µPC.
◼ µPC is automatically incremented by the clock,
so successive microinstructions are read from
the control store.
Execution of conditional Branch
Instruction
Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in
4 Offset-field-of-IR out, Add, Select Y, Z in , If N=0 then End
5 Z out , PC in , End

Figure 7.7(b). Control sequence for an conditional branch instruction.

If N=1 then branch is taken; execute an instruction from branch target.

N=0 branch is not taken; execute a sequentially next instruction.
Overview
◼ The previous organization cannot handle the situation when the
control unit is required to check the status of the condition codes or
external inputs to choose between alternative courses of action.
◼ Use conditional branch microinstruction.
Address Microinstruction

0 PC out , MAR in , Read, Select4, Add, Z in

1 Z out , PC in , Y in , WMF C
2 MDR out , IR in
3 Branch to starting address of appropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction 0
26 Offset-field-of-IR out , SelectY, Add, Z in
27 Z out , PC in , End

Figure 7.17. Microroutine for the instruction Branch<0.

Overview
External
inputs

Starting and
branch address Condition
IR codes
generator

Clock mPC

Control
store CW

Figure 7.18. Organization of the control unit to allow

conditional branching in the microprogram.
◼ In control unit, µPC incremented every time a new
microinstruction is fetched except,
❑ 1. When a new instruction is loaded into IR, the µPC is

loaded with the starting address of the micro routine

for that instruction
❑ 2.When a Branch instruction is encountered, and

branch condition is satisfied, the µPC is loaded with

the branch address
❑ 3.When an end microinstruction encountered, the µPC

is loaded with the address of the first CW in the micro

routine for the instruction fetch cycle(address 0)

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte
Comparison of hardwired and microprogrammed control
 Thank You..

Dr. Anisha P Rodrigues, Dept of

11/26/2021 CSE,NMAMIT, Nitte