Computer Organization and Architecture

22CS302

Dr. Raghunandan K. R.𝑩.𝑬.,𝑴.𝑻𝒆𝒄𝒉,𝑷𝒉.𝑫

Associate Professor
Department of Computer Science and Engg.
Computer Organization and Architecture 19CS304
 Fundamental Concepts

• Processor fetches one instruction at a time and perform the

operation specified.
• Instructions are fetched from successive memory locations
until a branch or a jump instruction is encountered.
• Processor keeps track of the address of the memory location
containing the next instruction to be fetched using Program
Counter (PC).
• Instruction Register (IR)
 Executing an Instruction
• Fetch the contents of the memory location pointed to by the
PC. The contents of this location are loaded into the IR (fetch
phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable, increment
the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction in the IR
(execution phase).
 Constant 4 R0

Select MUX

Processor Organization
Add
A B
ALU Sub R( n - 1)
control ALU
lines
Carry -in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

MDR HAS
TWO INPUTS
AND TWO
OUTPUTS
 Executing an Instruction

• Transfer a word of data from one processor

register to another or to the ALU.
• Perform an arithmetic or a logic operation and
store the result in a processor register.
• Fetch the contents of a given memory location
and load them into a processor register.
• Store a word of data from a processor register
into a given memory location.
 Register Transfers
Internal processor
bus
R iin

Ri

R iout

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Input and output gating for the registers

 Performing an Arithmetic or Logic Operation

• The ALU is a combinational circuit that has no internal

storage.
• ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.
• What is the sequence of operations to add the contents
of register R1 to those of R2 and store the result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
 Fetching a Word from Memory
Memory -bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure 7.4. Connection and control signals for

gister
re MDR.

• Address into MAR; issue Read operation; data into MDR.

Figure 7.4. Connection and control signals for register MDR.

 Fetching a Word from Memory

• The response time of each memory access varies (cache

miss, memory-mapped I/O,…).
• To accommodate this, the processor waits until it
receives an indication that the requested operation has
been completed (Memory-Function-Completed, MFC).
• Move (R1), R2
➢ MAR ← [R1]
➢ Start a Read operation on the memory bus
➢ Wait for the MFC response from the memory
➢ Load MDR from the memory bus
➢ R2 ← [MDR]
 Address

Timing
Read

MR

MDRinE

Data

MFC

MDR out

Figure 7.5. Timing of a memory Read operation.

MAR ← [R1]
Assume MAR
is always available
on the address lines
of the memory bus. Start a Read operation on the memory bus

Wait for the MFC response from the memory

Load MDR from the memory bus

R2 ← [MDR]
 Execution of a Complete
Instruction
• Add (R3), R1
• Fetch the instruction
• Fetch the first operand (the contents of the
memory location pointed to by R3)
• Perform the addition
• Load the result into R1
 Architecture Internal processor
bus
Riin

Ri

Riout

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
 Execution of a Complete
Memory
bus

Select

ALU
control
lines
Address
lines

Data
lines

Constant 4

Add
Sub

XOR
MUX

A
PC

MAR

MDR

ALU

Z
B
Internal processor
bus

Carry -in
Control signals

Instruction
decoder and
control logic

IR

R0

R( n - 1)

TEMP

Instruction
Figure 7.1. Single-bus organization of the datapath inside a processor.

Step Action

1 PCout , MAR in , Read, Select4,A dd, Zin

2 Zout , PCin , Y in , WMF C
3 MDR out , IR in
4 R3out , MAR in , Read
5 R1out , Y in , WMF C
6 MDR out , SelectY,Add, Zin
7 Zout , R1 in , End

Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.

Add (R3), R1
 Execution of Branch Instructions

• A branch instruction replaces the contents of

PC with the branch target address, which is
usually obtained by adding an offset X given in
the branch instruction.
• The offset X is usually the difference between
the branch target address and the address
immediately following the branch instruction.
• Conditional branch
Execution of Branch Instructions

Step Action

1 PC out , MAR in , Read, Select4, Add, Z in

2 Z out , PC in , Y in , WMF C
3 MDR out , IR in
4 Offset-field-of-IR out, Add, Z in
5 Z out , PC in , End

Figure 7.7. Control sequence for an unconditional branch instruction.

Multiple-Bus Organization
Bus A Bus B

Constant 4
Incrementer

PC

Register
f ile
Bus C

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory bus Address

data lines lines

Figure 7.8. Three-bus organization of the datapath.

 Multiple-Bus Organization
• Add R4, R5, R6

Step Action

1 PC out, R=B, MAR in , Read, IncPC

2 WMF C
3 MDR outB , R=B, IR in

4 R4 outA , R5 outB , SelectA, Add, R6 in , End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
 Quiz
Memory
bus

Select

ALU
control
lines
Address
lines

Data
lines

Constant 4

Add
Sub

XOR
MUX

A
PC

MAR

MDR

ALU

Z
B
Internal processor
bus

Carry -in
Control signals

Instruction
decoder and
control logic

IR

R0

R( n - 1)

TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

• What is the control

sequence for
execution of the
instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)
Hardwired Control
 Overview

• To execute instructions, the processor must

have some means of generating the control
signals needed in the proper sequence.
• Two categories: hardwired control and
microprogrammed control
• Hardwired system can operate at high speed;
but with little flexibility.
Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.
Control Unit Organization
CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Control unit organization.

IR
Clock

Instruction
decoder
CLK

INS1
INS2

INSm

Run
Detailed Block Description
Control step
counter

Step decoder

T 1 T2

Encoder
Tn

Control signals
Reset

End
External
inputs

Condition
codes

Figure 7.11. Separation of the decoding and encoding functions.

 Generating Zin

• Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Generation of the Zin control signal for the processor in Figure 7.1.
 Generating End
Branch<0
Add Branch
N N

T7 T5 T4 T5

• End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

End

Figure 7.13. Generation of the End control signal.

Microprogrammed Control
 IR

Clock
Starting
address
generator

PC

Control
store CW
Overview
Figure 7.16. Basic organization of a microprogrammed control unit.

• Control store

One function
cannot be carried
out by this simple
organization.
 Overview
• Control signals are generated by a program similar to machine language
MDRout

WMFC
MAR in

Select
Read
PCout

R1out

R3out
Micro -

End
PCin

R1in
Add

Z out
IRin
Yin

Zin
instruction

programs.
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An example of microinstructions for Figure 7.6.

• Control Word (CW); microroutine; microinstruction

 Step

1
2
Action

PCout , MAR in , Read, Select4,A dd, Zin

Zout , PCin , Y in , WMF C
Overview
3 MDR out , IR in
4 R3out , MAR in , Read
5 R1out , Y in , WMF C
6 MDR out , SelectY,Add, Zin
7 Zout , R1 in , End

Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.

 Overview
• The previous organization cannot handle the situation when the control unit is
required to check the status of the condition codes or external inputs to
choose between alternative courses of action.
• Use conditional branch microinstruction.
Address Microinstruction

0 PC out , MAR in , Read, Select4, Add, Z in

1 Z out , PC in , Y in , WMF C
2 MDR out , IR in
3 Branch to starting address of appropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction 0
26 Offset-field-of-IR out , SelectY, Add, Z in
27 Z out , PC in , End

Figure 7.17. Microroutine for the instruction Branch<0.

 Overview
External
inputs

Starting and
branch address Condition
IR codes
generator

Clock PC

Control
store CW

Figure 7.18. Organization of the control unit to allow

conditional branching in the microprogram.
 Microinstructions

• A straightforward way to structure

microinstructions is to assign one bit position
to each control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are
not needed simultaneously, and many signals
are mutually exclusive.
• All mutually exclusive signals are placed in the
same group in binary coding.
END

36