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Module V

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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Sequential Circuits.
We discussed various combinational circuits. All these circuits
have a set of output(s), which depends only on the combination
of present inputs. The following figure shows the block
diagram of sequential circuit.

This sequential circuit contains a set of inputs and output(s).

The output(s) of sequential circuit depends not only on the
combination of present inputs but also on the previous
output(s). Previous output is nothing but the present state.

Therefore, sequential circuits contain combinational circuits

along with memory (storage) elements. Some sequential
circuits may not contain combinational circuits, but only
memory elements.

Following table shows the differences between combinational

circuits and sequential circuits.

Combinational Circuits Sequential Circuits

Outputs depend on both
Outputs depend only on
present inputs and present
present inputs.
state.
Feedback path is not
Feedback path is present.
present.

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Memory elements are not

Memory elements are required.
required.
Clock signal is not
Clock signal is required.
required.
Easy to design. Difficult to design.

Types of Sequential Circuits

Following are the two types of sequential circuits −
 Asynchronous sequential circuits
 Synchronous sequential circuits

Asynchronous sequential circuits

If some or all the outputs of a sequential circuit do not change
(affect) with respect to active transition of clock signal, then that
sequential circuit is called as Asynchronous sequential
circuit. That means, all the outputs of asynchronous sequential
circuits do not change (affect) at the same time. Therefore, most
of the outputs of asynchronous sequential circuits are not in
synchronous with either only positive edges or only negative
edges of clock signal.

Synchronous sequential circuits

If all the outputs of a sequential circuit change (affect) with
respect to active transition of clock signal, then that sequential
circuit is called as Synchronous sequential circuit. That
means, all the outputs of synchronous sequential circuits change
(affect) at the same time. Therefore, the outputs of synchronous
sequential circuits are in synchronous with either only positive
edges or only negative edges of clock signal.

Clock Signal and Triggering

In this section, let us discuss about the clock signal and types of
triggering one by one.

Clock signal
Clock signal is a periodic signal and it’s ON time and OFF time
need not be the same. We can represent the clock signal as a

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

square wave, when both its ON time and OFF time are same.
This clock signal is shown in the following figure.

In the above figure, square wave is considered as clock signal.

This signal stays at logic High (5V) for some time and stays at
logic Low (0V) for equal amount of time. This pattern repeats
with some time period. In this case, the time period will be
equal to either twice of ON time or twice of OFF time.

We can represent the clock signal as train of pulses, when ON

time and OFF time are not same. This clock signal is shown in
the following figure.

In the above figure, train of pulses is considered as clock signal.

This signal stays at logic High (5V) for some time and stays at
logic Low (0V) for some other time. This pattern repeats with
some time period. In this case, the time period will be equal to
sum of ON time and OFF time.

The reciprocal of the time period of clock signal is known as the

frequency of the clock signal. All sequential circuits are
operated with clock signal. So, the frequency at which the
sequential circuits can be operated accordingly the clock signal
frequency has to be chosen.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

Types of Triggering
Following are the two possible types of triggering that are used
in sequential circuits.
 Level triggering
 Edge triggering

Level triggering
There are two levels, namely logic High and logic Low in clock
signal. Following are the two types of level triggering.
 Positive level triggering
 Negative level triggering
If the sequential circuit is operated with the clock signal when it
is in Logic High, then that type of triggering is known as
Positive level triggering. It is highlighted in below figure.

If the sequential circuit is operated with the clock signal when it

is in Logic Low, then that type of triggering is known as
Negative level triggering. It is highlighted in the following
figure.

Edge triggering
There are two types of transitions that occur in clock signal.
That means, the clock signal transitions either from Logic Low
to Logic High or Logic High to Logic Low.

Following are the two types of edge triggering based on the

transitions of clock signal.
 Positive edge triggering
 Negative edge triggering

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If the sequential circuit is operated with the clock signal that is

transitioning from Logic Low to Logic High, then that type of
triggering is known as Positive edge triggering. It is also called
as rising edge triggering. It is shown in the following figure.

If the sequential circuit is operated with the clock signal that is

transitioning from Logic High to Logic Low, then that type of
triggering is known as Negative edge triggering. It is also
called as falling edge triggering. It is shown in the following
figure.

Latches
There are two types of memory elements based on the type of
triggering that is suitable to operate it.
 Latches
 Flip-flops
Latches operate with enable signal, which is level sensitive.
Whereas, flip-flops are edge sensitive. We will discuss about
flip-flops in next chapter. Now, let us discuss about SR Latch &
D Latch one by one.

SR Latch
SR Latch is also called as Set Reset Latch. This latch affects the
outputs as long as the enable, E is maintained at ‘1’. The circuit
diagram of SR Latch is shown in the following figure.

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This circuit has two inputs S & R and two outputs Q(t) & Q(t)’.
The upper NOR gate has two inputs R & complement of present
state, Q(t)’ and produces next state, Q(t+1) when enable, E is ‘1’.
Similarly, the lower NOR gate has two inputs S & present state,
Q(t) and produces complement of next state, Q(t+1)’ when
enable, E is ‘1’.

We know that a 2-input NOR gate produces an output, which is

the complement of another input when one of the input is ‘0’.
Similarly, it produces ‘0’ output, when one of the input is ‘1’.
 If S=1, then next state Q(t+1) will be equal to ‘1’ irrespective
of present state, Q(t) values.
 If R=1, then next state Q(t+1) will be equal to ‘0’ irrespective
of present state, Q(t) values.

At any time, only of those two inputs should be ‘1’. If both inputs
are ‘1’, then the next state Q(t+1) value is undefined.
The following table shows the state table of SR latch.
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 -

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

Therefore, SR Latch performs three types of functions such as

Hold, Set & Reset based on the input conditions.

D Latch
There is one drawback of SR Latch. That is the next state value
can’t be predicted when both the inputs S & R are one. So, we
can overcome this difficulty by D Latch. It is also called as Data
Latch. The circuit diagram of D Latch is shown in the following
figure.

This circuit has single input D and two outputs Q(t) & Q(t)’. D
Latch is obtained from SR Latch by placing an inverter between
S amp;& R inputs and connect D input to S. That means we
eliminated the combinations of S & R are of same value.
 If D=0 → S=0 & R=1, then next state Q(t+1) will be equal to
‘0’ irrespective of present state, Q(t) values. This is
corresponding to the second row of SR Latch state table.
 If D=1 → S=1 & R=0, then next state Q(t+1) will be equal to
‘1’ irrespective of present state, Q(t) values. This is
corresponding to the third row of SR Latch state table.

The following table shows the state table of D latch.

D Q(t+1)
0 0
1 1
Therefore, D Latch Hold the information that is available on data
input, D. That means the output of D Latch is sensitive to the
changes in the input, D as long as the enable is High.
Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]
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We implemented various Latches by providing the cross

coupling between NOR gates. Similarly, you can implement
these Latches using NAND gates.

Flip-flops
Latches are the basic building blocks of flip-flops. We can
implement flip-flops in two methods.

In first method, cascade two latches in such a way that the first
latch is enabled for every positive clock pulse and second latch
is enabled for every negative clock pulse. So that the
combination of these two latches become a flip-flop.

In second method, we can directly implement the flip-flop,

which is edge sensitive. In this chapter, let us discuss the
following flip-flops using second method.
 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop

SR Flip-Flop
SR flip-flop operates with only positive clock transitions or
negative clock transitions. Whereas, SR latch operates with
enable signal. The circuit diagram of SR flip-flop is shown in
the following figure.

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

This circuit has two inputs S & R and two outputs Q(t) & Q(t)’.
The operation of SR flip-flop is similar to SR Latch. But, this flip-
flop affects the outputs only when positive transition of the
clock signal is applied instead of active enable.

The following table shows the state table of SR flip-flop.

S R Q(t+1)
0 0 Q(t+1)
0 1 0
1 0 1
1 1 -

Here, Q(t) & Q(t+1) are present state & next state respectively.
So, SR flip-flop can be used for one of these three functions such
as Hold, Reset & Set based on the input conditions, when
positive transition of clock signal is applied. The following table
shows the characteristic table of SR flip-flop.

Present Inputs Present State Next State

S R Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x

By using three variable K-Map, we can get the simplified

expression for next state, Q(t+1). The three variable K-Map for
next state, Q(t+1) is shown in the following figure.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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The maximum possible groupings of adjacent ones are already

shown in the figure. Therefore, the simplified expression for
next state Q(t+1) is
Q(t+1)=S+R′Q(t)

D Flip-Flop
D flip-flop operates with only positive clock transitions or
negative clock transitions. Whereas, D latch operates with
enable signal. That means, the output of D flip-flop is insensitive
to the changes in the input, D except for active transition of the
clock signal. The circuit diagram of D flip-flop is shown in the
following figure.

This circuit has single input D and two outputs Q(t) & Q(t)’. The
operation of D flip-flop is similar to D Latch. But, this flip-flop
affects the outputs only when positive transition of the clock
signal is applied instead of active enable.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

The following table shows the state table of D flip-flop.

D Q(t+1)
0 0
0 1
Therefore, D flip-flop always Hold the information, which is
available on data input, D of earlier positive transition of clock
signal. From the above state table, we can directly write the next
state equation as
Q(t+1)=D

Next state of D flip-flop is always equal to data input, D for every

positive transition of the clock signal. Hence, D flip-flops can be
used in registers, shift registers and some of the counters.

JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates
with only positive clock transitions or negative clock
transitions. The circuit diagram of JK flip-flop is shown in the
following figure.

This circuit has two inputs J & K and two outputs Q(t) & Q(t)’.
The operation of JK flip-flop is similar to SR flip-flop. Here, we
considered the inputs of SR flip-flop as S=J Q(t)’ and R=KQ(t) in
order to utilize the modified SR flip-flop for 4 combinations of
inputs.
Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]
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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

The following table shows the state table of JK flip-flop.

J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)'

Here, Q(t) & Q(t+1) are present state & next state respectively.
So, JK flip-flop can be used for one of these four functions such
as Hold, Reset, Set & Complement of present state based on the
input conditions, when positive transition of clock signal is
applied. The following table shows the characteristic table of
JK flip-flop.

Present Inputs Present State Next State

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

By using three variable K-Map, we can get the simplified

expression for next state, Q(t+1). Three variable K-Map for
next state, Q(t+1) is shown in the following figure.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

The maximum possible groupings of adjacent ones are already

shown in the figure. Therefore, the simplified expression for
next state Q(t+1) is
Q(t+1)=JQ(t)′+K′Q(t)

T Flip-Flop
T flip-flop is the simplified version of JK flip-flop. It is obtained
by connecting the same input ‘T’ to both inputs of JK flip-flop. It
operates with only positive clock transitions or negative clock
transitions. The circuit diagram of T flip-flop is shown in the
following figure.

This circuit has single input T and two outputs Q(t) & Q(t)’. The
operation of T flip-flop is same as that of JK flip-flop. Here, we
considered the inputs of JK flip-flop as J=T and K=T in order to
utilize the modified JK flip-flop for 2 combinations of inputs. So,
we eliminated the other two combinations of J & K, for which
those two values are complement to each other in T flip-flop.

The following table shows the state table of T flip-flop.

D Q(t+1)
0 Q(t)
1 Q(t)’
Here, Q(t) & Q(t+1) are present state & next state respectively.
So, T flip-flop can be used for one of these two functions such as
Hold, & Complement of present state based on the input
conditions, when positive transition of clock signal is applied.
Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]
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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

The following table shows the characteristic table of T flip-

flop.
Inputs Present State Next State
T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
From the above characteristic table, we can directly write the
next state equation as
Q(t+1)=T′Q(t)+TQ(t)′
⇒Q(t+1)=T⊕Q(t)

The output of T flip-flop always toggles for every positive

transition of the clock signal, when input T remains at logic High
(1). Hence, T flip-flop can be used in counters.

The NAND Gate SR Flip-Flop

The simplest way to make any basic single bit set-reset SR flip-
flop is to connect together a pair of cross-coupled 2-input NAND
gates as shown, to form a Set-Reset Bistable also known as an
active LOW SR NAND Gate Latch, so that there is feedback from
each output to one of the other NAND gate inputs. This device
consists of two inputs, one called the Set, S and the other called
the Reset, R with two corresponding outputs Q and its inverse
or complement Q’ (not-Q) as shown below.

The Basic SR Flip-flop

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The Set State

Consider the circuit shown above. If the input R is at logic level
“0” (R = 0) and input S is at logic level “1” (S = 1), the NAND gate
Y has at least one of its inputs at logic “0” therefore, its output
Q’ must be at a logic level “1” (NAND Gate principles). Output Q’
is also fed back to input “A” and so both inputs to NAND gate X
are at logic level “1”, and therefore its output Q must be at logic
level “0”.

Again NAND gate principals. If the reset input R changes state,

and goes HIGH to logic “1” with S remaining HIGH also at logic
level “1”, NAND gate Y inputs are now R = “1” and B = “0”. Since
one of its inputs is still at logic level “0” the output at Q’ still
remains HIGH at logic level “1” and there is no change of state.
Therefore, the flip-flop circuit is said to be “Latched” or “Set”
with Q’ = “1” and Q = “0”.

Reset State
In this second stable state, Q’ is at logic level “0”, (not Q = “0”) its
inverse output at Q is at logic level “1”, (Q = “1”), and is given by
R = “1” and S = “0”. As gate X has one of its inputs at logic “0” its
output Q must equal logic level “1” (again NAND gate
principles). Output Q is fed back to input “B”, so both inputs to
NAND gate Y are at logic “1”, therefore, Q’ = “0”.

If the set input, S now changes state to logic “1” with input R
remaining at logic “1”, output Q’ still remains LOW at logic level
“0” and there is no change of state. Therefore, the flip-flop
circuits “Reset” state has also been latched and we can define
this “set/reset” action in the following truth table.

Truth Table for this Set-Reset Function

State S R Q Q’ Description
1 0 0 1 Set Q’ » 1
Set
1 1 0 1 no change
0 1 1 0 Reset Q’ » 0
Reset
1 1 1 0 no change
Invalid 0 0 1 1 Invalid Condition
Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]
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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

It can be seen that when both inputs S = “1” and R = “1” the
outputs Q and Q’ can be at either logic level “1” or “0”, depending
upon the state of the inputs S or R BEFORE this input condition
existed. Therefore the condition of S = R = “1” does not change
the state of the outputs Q and Q’.

However, the input state of S = “0” and R = “0” is an undesirable

or invalid condition and must be avoided. The condition of S = R
= “0” causes both outputs Q and Q’ to be HIGH together at logic
level “1” when we would normally want Q’ to be the inverse of
Q. The result is that the flip-flop looses control of Q and Q’, and
if the two inputs are now switched “HIGH” again after this
condition to logic “1”, the flip-flop becomes unstable and
switches to an unknown data state based upon the unbalance as
shown in the following switching diagram.

S-R Flip-flop Switching Diagram

This unbalance can cause one of the outputs to switch faster

than the other resulting in the flip-flop switching to one state or
the other which may not be the required state and data
corruption will exist. This unstable condition is generally known
as its Meta-stable state.
Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]
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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

Then, a simple NAND gate SR flip-flop or NAND gate SR latch can

be set by applying a logic “0”, (LOW) condition to its Set input
and reset again by then applying a logic “0” to its Reset input.
The SR flip-flop is said to be in an “invalid” condition (Meta-
stable) if both the set and reset inputs are activated
simultaneously.

As we have seen above, the basic NAND gate SR flip-flop

requires logic “0” inputs to flip or change state from Q to Q’ and
vice versa. We can however, change this basic flip-flop circuit to
one that changes state by the application of positive going input
signals with the addition of two extra NAND gates connected as
inverters to the S and R inputs as shown.

Positive NAND Gate SR Flip-flop

As well as using NAND gates, it is also possible to construct

simple one-bit SR Flip-flops using two cross-coupled NOR gates
connected in the same configuration. The circuit will work in a
similar way to the NAND gate circuit above, except that the
inputs are active HIGH and the invalid condition exists when
both its inputs are at logic level “1”, and this is shown below.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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The NOR Gate SR Flip-flop

Switch Debounce Circuits

Edge-triggered flip-flops require a nice clean signal transition,
and one practical use of this type of set-reset circuit is as a latch
used to help eliminate mechanical switch “bounce”. As its name
implies, switch bounce occurs when the contacts of any
mechanically operated switch, push-button or keypad are
operated and the internal switch contacts do not fully close
cleanly, but bounce together first before closing (or opening)
when the switch is pressed.

This gives rise to a series of individual pulses which can be as

long as tens of milliseconds that an electronic system or circuit
such as a digital counter may see as a series of logic pulses
instead of one long single pulse and behave incorrectly. For
example, during this bounce period the output voltage can
fluctuate wildly and may register multiple input counts instead
of one single count. Then set-reset SR Flip-flops or Bistable
Latch circuits can be used to eliminate this kind of problem and
this is demonstrated below.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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SR Flip Flop Switch Debounce Circuit

Depending upon the current state of the output, if the set or

reset buttons are depressed the output will change over in the
manner described above and any additional unwanted inputs
(bounces) from the mechanical action of the switch will have no
effect on the output at Q.
When the other button is pressed, the very first contact will
cause the latch to change state, but any additional mechanical
switch bounces will also have no effect. The SR flip-flop can then
be RESET automatically after a short period of time, for example
0.5 seconds, so as to register any additional and intentional
repeat inputs from the same switch contacts, such as multiple
inputs from a keyboards “RETURN” key.

Gated or Clocked SR Flip-Flop

It is sometimes desirable in sequential logic circuits to have a
bistable SR flip-flop that only changes state when certain
conditions are met regardless of the condition of either the Set
or the Reset inputs. By connecting a 2-input AND gate in series
with each input terminal of the SR Flip-flop a Gated SR Flip-flop
can be created. This extra conditional input is called an “Enable”
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input and is given the prefix of “EN“. The addition of this input
means that the output at Q only changes state when it is HIGH
and can therefore be used as a clock (CLK) input making it level-
sensitive as shown below.

Gated SR Flip-flop

When the Enable input “EN” is at logic level “0”, the outputs of
the two AND gates are also at logic level “0”, (AND Gate
principles) regardless of the condition of the two inputs S and R,
latching the two outputs Q and Q’ into their last known state.
When the enable input “EN” changes to logic level “1” the circuit
responds as a normal SR bistable flip-flop with the two AND
gates becoming transparent to the Set and Reset signals.

This additional enable input can also be connected to a clock

timing signal (CLK) adding clock synchronization to the flip-flop
creating what is sometimes called a “Clocked SR Flip-flop“. So a

Gated Bistable SR Flip-flop operates as a standard bistable

latch but the outputs are only activated when a logic “1” is
applied to its EN input and deactivated by a logic “0”.

Edge triggered flip flops

Another type of simple edge-triggered flip-flop which is very
similar to the RS flip-flop called a JK Flip-flop named after its
inventor, Jack Kilby. The JK flip-flop is the most widely used of
all the flip-flop designs as it is considered to be a universal
device.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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The S = 0 and R = 0 condition (S = R = 0) must always be avoided,

and if S or R change state while the enable input is high the
correct latching action may not occur. Then to overcome these
two fundamental design problems with the SR flip-flop design,
the JK flip Flop was developed.

This simple JK flip Flop is the most widely used of all the flip-
flop designs and is considered to be a universal flip-flop circuit.
The sequential operation of the JK flip flop is exactly the same as
for the previous SR flip-flop with the same “Set” and “Reset”
inputs. The difference this time is that the “JK flip flop” has no
invalid or forbidden input states of the SR Latch even when S
and R are both at logic “1”.

The JK flip flop is basically a gated SR flip-flop with the addition

of a clock input circuitry that prevents the illegal or invalid
output condition that can occur when both inputs S and R are
equal to logic level “1”. Due to this additional clocked input, a JK
flip-flop has four possible input combinations, “logic 1”, “logic
0”, “no change” and “toggle”. The symbol for a JK flip flop is
similar to that of an SR Bistable Latch as seen in the previous
tutorial except for the addition of a clock input.
The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bistable have now
been replaced by two inputs called the J and K inputs,
respectively after its inventor Jack Kilby. Then this equates to:
J = S and K = R.

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The two 2-input AND gates of the gated SR bistable have now
been replaced by two 3-input NAND gates with the third input
of each gate connected to the outputs at Q and Q’. This cross
coupling of the SR flip-flop allows the previously invalid
condition of S = “1” and R = “1” state to be used to produce a
“toggle action” as the two inputs are now interlocked.

If the circuit is now “SET” the J input is inhibited by the “0” status
of Q’ through the lower NAND gate. If the circuit is “RESET” the
K input is inhibited by the “0” status of Q through the upper
NAND gate. As Q and Q’ are always different we can use them to
control the input. When both inputs J and K are equal to logic
“1”, the JK flip flop toggles as shown in the following truth table.

The Truth Table for the JK Function

Input Output
Description
J K Q Q’
0 0 0 0 Memory
same as
0 0 0 1 no change
for the
0 1 1 0
SR Latch Reset Q » 0
0 1 0 1
1 0 0 1
Set Q » 1
1 0 1 0
toggle 1 1 0 1
Toggle
action 1 1 1 0

Then the JK flip-flop is basically an SR flip flop with feedback

which enables only one of its two input terminals, either SET or
RESET to be active at any one time thereby eliminating the
invalid condition seen previously in the SR flip flop circuit.

Also when both the J and the K inputs are at logic level “1” at the
same time, and the clock input is pulsed “HIGH”, the circuit will
“toggle” from its SET state to a RESET state, or visa-versa. This
results in the JK flip flop acting more like a T-type toggle flip-flop
when both terminals are “HIGH”.

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Although this circuit is an improvement on the clocked SR flip-

flop it still suffers from timing problems called “race” if the
output Q changes state before the timing pulse of the clock input
has time to go “OFF”. To avoid this the timing pulse period ( T )
must be kept as short as possible (high frequency). As this is
sometimes not possible with modern TTL IC’s the much
improved Master-Slave JK Flip-flop was developed.

The Master-Slave JK Flip-flop

The Master-Slave Flip-Flop is basically two gated SR flip-flops
connected together in a series configuration with the slave
having an inverted clock pulse. The outputs from Q and Q’ from
the “Slave” flip-flop are fed back to the inputs of the “Master”
with the outputs of the “Master” flip flop being connected to the
two inputs of the “Slave” flip flop. This feedback configuration
from the slave’s output to the master’s input gives the
characteristic toggle of the JK flip flop as shown below.

The Master-Slave JK Flip Flop

The input signals J and K are connected to the gated “master” SR

flip flop which “locks” the input condition while the clock (Clk)
input is “HIGH” at logic level “1”. As the clock input of the “slave”
flip flop is the inverse (complement) of the “master” clock input,
the “slave” SR flip flop does not toggle. The outputs from the
“master” flip flop are only “seen” by the gated “slave” flip flop
when the clock input goes “LOW” to logic level “0”.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

When the clock is “LOW”, the outputs from the “master” flip flop
are latched and any additional changes to its inputs are ignored.
The gated “slave” flip flop now responds to the state of its inputs
passed over by the “master” section.

Then on the “Low-to-High” transition of the clock pulse the

inputs of the “master” flip flop are fed through to the gated
inputs of the “slave” flip flop and on the “High-to-Low” transition
the same inputs are reflected on the output of the “slave” making
this type of flip flop edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is
“HIGH”, and passes the data to the output on the falling-edge of
the clock signal. In other words, the Master-Slave JK Flip flop
is a “Synchronous” device as it only passes data with the timing
of the clock signal.

Counters
An ‘N’ bit binary counter consists of ‘N’ T flip-flops. If the counter
counts from 0 to 2𝑁 − 1, then it is called as binary up counter.
Similarly, if the counter counts down from 2𝑁 − 1 to 0, then it is
called as binary down counter.

There are two types of counters based on the flip-flops that are
connected in synchronous or not.
 Asynchronous counters
 Synchronous counters

Asynchronous Counters
If the flip-flops do not receive the same clock signal, then that
counter is called as Asynchronous counter. The output of
system clock is applied as clock signal only to first flip-flop. The
remaining flip-flops receive the clock signal from output of its
previous stage flip-flop. Hence, the outputs of all flip-flops do not
change (affect) at the same time.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

Now, let us discuss the following two counters one by one.

 Asynchronous Binary up counter
 Asynchronous Binary down counter

Asynchronous Binary Up Counter

An ‘N’ bit Asynchronous binary up counter consists of ‘N’ T flip-
flops. It counts from 0 to 2𝑁 − 1. The block diagram of 3-bit
Asynchronous binary up counter is shown in the following
figure.

The 3-bit Asynchronous binary up counter contains three T flip-

flops and the T-input of all the flip-flops are connected to ‘1’. All
these flip-flops are negative edge triggered but the outputs
change asynchronously. The clock signal is directly applied to
the first T flip-flop. So, the output of first T flip-flop toggles for
every negative edge of clock signal.

The output of first T flip-flop is applied as clock signal for second

T flip-flop. So, the output of second T flip-flop toggles for every
negative edge of output of first T flip-flop. Similarly, the output
of third T flip-flop toggles for every negative edge of output of
second T flip-flop, since the output of second T flip-flop acts as
the clock signal for third T flip-flop.

Assume the initial status of T flip-flops from rightmost to

leftmost is Q2Q1Q0=000. Here, Q2 & Q0 are MSB & LSB
respectively. We can understand the working of 3-bit
asynchronous binary counter from the following table.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

No of negative
Q0(LSB) Q1 Q2(MSB)
edge of Clock
0 0 0 0
1 1 0 0
2 0 1 0
3 1 1 0
4 0 0 1
5 1 0 1
6 0 1 1
7 1 1 1

Here Q0 toggled for every negative edge of clock signal. Q1

toggled for every Q0 that goes from 1 to 0, otherwise remained
in the previous state. Similarly, Q2 toggled for every Q1 that goes
from 1 to 0, otherwise remained in the previous state.

The initial status of the T flip-flops in the absence of clock signal

is Q2Q1Q0=000. This is incremented by one for every negative
edge of clock signal and reached to maximum value at 7th
negative edge of clock signal. This pattern repeats when further
negative edges of clock signal are applied.

Asynchronous Binary Down Counter

An ‘N’ bit Asynchronous binary down counter consists of ‘N’ T
flip-flops. It counts from 2𝑁 − 1 to 0. The block diagram of 3-bit
Asynchronous binary down counter is shown in the following
figure.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

The block diagram of 3-bit Asynchronous binary down counter

is similar to the block diagram of 3-bit Asynchronous binary up
counter. But, the only difference is that instead of connecting the
normal outputs of one stage flip-flop as clock signal for next
stage flip-flop, connect the complemented outputs of one stage
flip-flop as clock signal for next stage flip-flop. Complemented
output goes from 1 to 0 is same as the normal output goes from
0 to 1.

Assume the initial status of T flip-flops from rightmost to

leftmost is Q2Q1Q0=000. Here, Q2 & Q0 are MSB & LSB
respectively. We can understand the working of 3-bit
asynchronous binary down counter from the following table.

No of negative
Q0(LSB) Q1 Q2(MSB)
edge of Clock
0 0 0 0
1 1 1 1
2 0 1 1
3 1 0 1
4 0 0 1
5 1 1 0
6 0 1 0
7 1 0 0

Here Q0 toggled for every negative edge of clock signal. Q1

toggled for every Q0 that goes from 0 to 1, otherwise remained
in the previous state. Similarly, Q2 toggled for every Q1 that goes
from 0 to 1, otherwise remained in the previous state.

The initial status of the T flip-flops in the absence of clock signal

is Q2Q1Q0=000. This is decremented by one for every negative
edge of clock signal and reaches to the same value at 8th negative
edge of clock signal. This pattern repeats when further negative
edges of clock signal are applied.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

Synchronous Counters
If all the flip-flops receive the same clock signal, then that
counter is called as Synchronous counter. Hence, the outputs
of all flip-flops change (affect) at the same time.

Now, let us see the following two counters one by one.

 Synchronous Binary up counter
 Synchronous Binary down counter

Synchronous Binary Up Counter

An ‘N’ bit Synchronous binary up counter consists of ‘N’ T flip-
flops. It counts from 0 to 2𝑁 − 1. The block diagram of 3-bit
Synchronous binary up counter is shown in the following figure.

The 3-bit Synchronous binary up counter contains three T flip-

flops & one 2-input AND gate. All these flip-flops are negative
edge triggered and the outputs of flip-flops change (affect)
synchronously. The T inputs of first, second and third flip-flops
are 1, Q0 & Q1Q0 respectively.

The output of first T flip-flop toggles for every negative edge of

clock signal. The output of second T flip-flop toggles for every
negative edge of clock signal if Q0 is 1. The output of third T flip-
flop toggles for every negative edge of clock signal if both Q0 &
Q1 are 1.

Synchronous Binary Down Counter

An ‘N’ bit Synchronous binary down counter consists of ‘N’ T
flip-flops. It counts from 2𝑁 − 1 to 0. The block diagram of 3-bit

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

Synchronous binary down counter is shown in the following

figure.

The 3-bit Synchronous binary down counter contains three T

flip-flops & one 2-input AND gate. All these flip-flops are
negative edge triggered and the outputs of flip-flops change
(affect) synchronously. The T inputs of first, second and third
flip-flops are 1, Q0′ &' Q1′Q0′ respectively.

The output of first T flip-flop toggles for every negative edge of

clock signal. The output of second T flip-flop toggles for every
negative edge of clock signal if Q0′ is 1. The output of third T flip-
flop toggles for every negative edge of clock signal if both Q1′ &
Q0′ are 1.

Shift Register
We know that one flip-flop can store one-bit of information. In
order to store multiple bits of information, we require multiple
flip-flops. The group of flip-flops, which are used to hold (store)
the binary data is known as register.

If the register is capable of shifting bits either towards right

hand side or towards left hand side is known as shift register.
An ‘N’ bit shift register contains ‘N’ flip-flops. Following are the
four types of shift registers based on applying inputs and
accessing of outputs.
 Serial In - Serial Out shift register
 Serial In - Parallel Out shift register
 Parallel In - Serial Out shift register
 Parallel In - Parallel Out shift register

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

Serial In - Serial Out (SISO) Shift Register

The shift register, which allows serial input and produces serial
output is known as Serial In – Serial Out (SISO) shift register.

The block diagram of 3-bit SISO shift register is shown in the

following figure.

This block diagram consists of three D flip-flops, which are

cascaded. That means, output of one D flip-flop is connected as
the input of next D flip-flop. All these flip-flops are synchronous
with each other since, the same clock signal is applied to each
one.

In this shift register, we can send the bits serially from the input
of left most D flip-flop. Hence, this input is also called as serial
input. For every positive edge triggering of clock signal, the data
shifts from one stage to the next. So, we can receive the bits
serially from the output of right most D flip-flop. Hence, this
output is also called as serial output.

Example
Let us see the working of 3-bit SISO shift register by sending the
binary information “011” from LSB to MSB serially at the input.
Assume, initial status of the D flip-flops from leftmost to
rightmost is Q2Q1Q0=000. We can understand the working of
3-bit SISO shift register from the following table.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

No of positive Serial
Q2 Q1 Q0
edge of Clock Input
0 - 0 0 0
1 1(LSB) 1 0 0
2 1 1 1 0
3 0(MSB) 0 1 1(LSB)
4 - - 0 1
5 - - - 0(MSB)
The initial status of the D flip-flops in the absence of clock signal
is Q2Q1Q0=000. Here, the serial output is coming from Q0. So,
the LSB (1) is received at 3rd positive edge of clock and the MSB
(0) is received at 5th positive edge of clock.

Therefore, the 3-bit SISO shift register requires five clock pulses
in order to produce the valid output. Similarly, the N-bit SISO
shift register requires 2N-1 clock pulses in order to shift ‘N’ bit
information.

Serial In - Parallel Out (SIPO) Shift Register

The shift register, which allows serial input and produces
parallel output is known as Serial In – Parallel Out (SIPO) shift
register. The block diagram of 3-bit SIPO shift register is shown
in the following figure.

This circuit consists of three D flip-flops, which are cascaded.

That means, output of one D flip-flop is connected as the input
of next D flip-flop. All these flip-flops are synchronous with each
other since, the same clock signal is applied to each one.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

In this shift register, we can send the bits serially from the input
of left most D flip-flop. Hence, this input is also called as serial
input. For every positive edge triggering of clock signal, the data
shifts from one stage to the next. In this case, we can access the
outputs of each D flip-flop in parallel. So, we will get parallel
outputs from this shift register.

Example
Let us see the working of 3-bit SIPO shift register by sending the
binary information “011” from LSB to MSB serially at the input.
Assume, initial status of the D flip-flops from leftmost to
rightmost is Q2Q1Q0=000. Here, Q2 & Q0 are MSB & LSB
respectively. We can understand the working of 3-bit SIPO
shift register from the following table.

No of positive Serial
Q2(MSB) Q1 Q0(LSB)
edge of Clock Input
0 - 0 0 0
1 1(LSB) 1 0 0
2 1 1 1 0
3 0(MSB) 0 1 1
The initial status of the D flip-flops in the absence of clock signal
is Q2Q1Q0=000. The binary information “011” is obtained in
parallel at the outputs of D flip-flops for third positive edge of
clock.

So, the 3-bit SIPO shift register requires three clock pulses in
order to produce the valid output. Similarly, the N-bit SIPO shift
register requires N clock pulses in order to shift ‘N’ bit
information.

Parallel In - Serial Out (PISO) Shift Register

The shift register, which allows parallel input and produces
serial output is known as Parallel In – Serial Out (PISO) shift
register. The block diagram of 3-bit PISO shift register is shown
in the following figure.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

This circuit consists of three D flip-flops, which are cascaded.

That means, output of one D flip-flop is connected as the input
of next D flip-flop. All these flip-flops are synchronous with each
other since, the same clock signal is applied to each one.

In this shift register, we can apply the parallel inputs to each D

flip-flop by making Preset Enable to 1. For every positive edge
triggering of clock signal, the data shifts from one stage to the
next. So, we will get the serial output from the right most D flip-
flop.

Example
Let us see the working of 3-bit PISO shift register by applying
the binary information “011” in parallel through preset inputs.
Since the preset inputs are applied before positive edge of Clock,
the initial status of the D flip-flops from leftmost to rightmost
will be Q2Q1Q0=011. We can understand the working of 3-bit
PISO shift register from the following table.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

No of positive
Q2 Q1 Q0
edge of Clock
0 0 1 1(LSB)
1 - 0 1
2 - - 0(LSB)

Here, the serial output is coming from Q0. So, the LSB (1) is
received before applying positive edge of clock and the MSB (0)
is received at 2nd positive edge of clock.

Therefore, the 3-bit PISO shift register requires two clock pulses
in order to produce the valid output. Similarly, the N-bit PISO
shift register requires N-1 clock pulses in order to shift ‘N’ bit
information.

Parallel In - Parallel Out (PIPO) Shift Register

The shift register, which allows parallel input and produces
parallel output is known as Parallel In − Parallel Out (PIPO) shift
register. The block diagram of 3-bit PIPO shift register is
shown in the following figure.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]

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CS1CMT01 Fundamentals of Digital Systems (Complementary) MG University, Kottayam

This circuit consists of three D flip-flops, which are cascaded.

That means, output of one D flip-flop is connected as the input
of next D flip-flop. All these flip-flops are synchronous with each
other since, the same clock signal is applied to each one.

In this shift register, we can apply the parallel inputs to each D

flip-flop by making Preset Enable to 1. We can apply the parallel
inputs through preset or clear. These two are asynchronous
inputs. That means, the flip-flops produce the corresponding
outputs, based on the values of asynchronous inputs. In this
case, the effect of outputs is independent of clock transition. So,
we will get the parallel outputs from each D flip-flop.

Example
Let us see the working of 3-bit PIPO shift register by applying
the binary information “011” in parallel through preset inputs.
Since the preset inputs are applied before positive edge of Clock,
the initial status of the D flip-flops from leftmost to rightmost
will be Q2Q1Q0=011. So, the binary information “011” is
obtained in parallel at the outputs of D flip-flops before applying
positive edge of clock.

Therefore, the 3-bit PIPO shift register requires zero clock

pulses in order to produce the valid output. Similarly, the N-bit
PIPO shift register doesn’t require any clock pulse in order to
shift ‘N’ bit information.

Eugin Lopez. F, Asst. Prof in Computer, CAS, IHRD, Thodupuzha [email protected]