RAYMING PCB & ASSEMBLY

Creating the Layout from your

Schematic

The schematic capture is an important first step in the design cycle of an

electronic circuit or system. It allows the designer to plan out and test the

circuit functionality and connectivity on paper or in a CAD program prior to

physically realizing it.

However, in order to manufacture a printed circuit board (PCB) and assemble

the components, the physical dimensions, component footprints, trace widths,

etc must all be precisely defined. This is known as board layout or PCB layout.

This article provides guidance on taking a completed schematic and translating

it into an initial board layout that is ready for further refinement and

optimization. Key topics include:

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 Exporting netlists
 Placing components
 Routing connections
 Implementing layout best practices
 Performing design rule checks

Properly creating the layout ensures your design intent is maintained and the

PCB can be physically manufactured without errors.

Export the Netlist

After completing the schematic design, the first step is to export an electronic

netlist file. This netlist contains a listing of all the electronic connections in a

textual file format which will serve as the guide for layout.

Common netlist formats used in PCB design include:

 EDIF
 Protel
 OrCad
 PADS
 Cadence Allegro

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The netlist can be exported directly from within the schematic CAD program.

Consult your tool documentation on the recommended format.

Additional key data is also exported alongside the netlist including:

 Part library footprint assignments

 Component parametric data
 Design rules

If your schematic tool does not support exporting all required data, manual

entry into the layout tool may be required later.

Table 1 - Common Netlist Formats

Common Netlist Formats

Place Components

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With the netlist file imported, the basic parts placement process can begin.

There are a few methods and order of operations to follow for initial

placement:

Method 1 - By Circuit Section

1. Identify circuit sections - Break the design into functional blocks like microcontroller,
power supply, connectors, etc
2. Define section outlines - Create board outlines for each section for initial component
grouping
3. Place section components - Within each section, place related components near each
other

This method provides organized placement grouped per function. Drawbacks

are needing sufficient board space upfront and potential difficulty routing

between sections.

Method 2 - By Schematic Sheet

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1. Place sheet components - Follow the same schematic sheet order placing components
2. Route sheet connections - Route connections for each sheet before moving to the next
3. Complete overall routing - Finish routing between sheets

This mirrors the schematic hierarchy for intuitive component findability. It can

also simplify routing into a sequential process. However, interleaving

component placement and routing by section provides more flexibility.

General Placement Guidelines

Some general guidelines to follow during parts placement:

 Start with special placement requirements - First place components with fixed locations
like connectors that interface with external hardware
 Observe clearance rules - Ensure sufficient spacing between part footprints and
enclosure walls based on voltage separation design rules
 Group associated parts - Place interacting components with short connections near each
other
 Plan for routing channels - Leave sufficient routing channels between sections at 50-100
mil widths

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Following these basic rules sets the foundation for part placement

optimization later.

Connectivity and Routing

With components approximately placed, creating physical connectivity

between parts is the next priority. This is known as routing and includes tracing

out copper tracks and adding vias between layers.

Routing guidelines include:

Logical Organization

 Route by net or circuit signals first for clarity before optimization

 Create bus routes with parallel lines for multi-bit data flows
 Identify key routes that shouldn't change when optimizing

Layout Practices

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 Use grid snapping to connect pins/pads precisely

 Choose trace widths based on current flow from tables or calculators
 Mind trace length matching for differential pairs
 Limit acid traps caused by unconnected copper fills

Via Usage

 Minimize drill transitions between layers for cost savings

 Bring all connections down to one layer first if possible
 Place stitching vias alongside balls of BGAs for thermal relief

Table 2 - Typical Trace Widths vs Current

Typical Trace Widths vs Current

Properly organizing and routing the connections transforms the logical netlist

into a physical layout matching the schematic.

Implementation Best Practices

Beyond just routing the basic connectivity, additional best practices ensure

good manufacturability, assembly yield, and circuit performance.

Specify Stackup

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Choose a fabrication stackup that provides the right number of routing layers

and dielectric materials based on density requirements and signal speeds.

Common options:

 4-layer FR4
 4-layer high frequency material
 6-layer with power and ground planes
 8-layer or more for advanced designs

Power Distribution

Set up clean power distribution with:

 Complete uninterrupted ground planes

 Filtered power planes for each supply
 Enough decoupling capacitors in a star distribution
 Separate analog and digital supplies

High Speed Routing

Minimize parasitics for high speed signals like memory buses with:

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 Short controlled impedance paths

 Proper line termination
 Matched lengths for differential pairs
 Lack of 90 degree turns or acid traps

Thermal Management

Ensure power devices and ICs can dissipate heat efficiently through:

 Adequate copper connected to pads

 Thermal reliefs and minimal thermal barriers
 Sufficient ground plane heat sinking
 Supplemental cooling options if needed

Keeping each of these best practices in mind improves design robustness.

Design Rule Checking

To validate manufacturability and catch physical errors, running design rule

checks is essential prior to tape out. Typical checks include:

Connectivity

 No open connections or stubs

 All pins properly connected to nets
 No invalid acid traps

Spacing

 Trace spacing meets voltage isolation needs

 Components have sufficient clearance
 Teardrop pads on connector leads

Routing

 Trace widths can carry required current

 Thickness can support number of layers

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 Controlled impedance lines are properly terminated

Tools analyze the full layout and generate detailed reports listing any design

violations found that require correction. Repeated cycles of layout

optimization and design rule validation are key leading up to final tape out.

Next Steps

Upon passing design validation, the layout can then be released for board

fabrication and assembly. Additional steps in the development process include:

 Order PCB fabrication with assembly quotes

 Create assembly drawings for the CM
 Fabricate advance prototypes for testing
 Refine layout based on measured results
 Release to volume production

With attention to the guidance provided throughout this article during layout,

your completed design should progress smoothly towards manufacturing.

FQA

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What are the key differences when laying out a double sided vs

multilayer board?

The most significant differences are around routing capabilities and best

practices. For double sided, all routing must be completed on the two external

layers. This limits routing capability and often requires wider traced to carry

more current flow. Also without internal planes acting as shields, care must be

taken to properly separate analog and digital signals.

In contrast on multilayer, two or more routing layers provide much more

flexibility plus integrated power and ground planes shield signals while serving

as heat sinks. Components can be placed closer together and trace widths

reduced. The design process focuses more on optimal use of layers,

minimizing vias, and reducing plane splits.

How can I calculate the target characteristic impedance for a

trace?

Use an impedance calculator which incorporates:

 Dielectric constant for the material

 Trace width
 Trace thickness
 Separation from reference planes

With controlled impedance transmission lines, matching calculated Z0 values

for traces within a certain tolerance ensures proper transmission and

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termination of high speed signals. This prevents reflection and parasitics which

corrupt signal integrity.

What is a stub and why are they problematic?

A stub refers to an unintended resonant transmission line caused by branches

off a route that are left unterminated. At high frequencies they can become

small antennas leading to radiated emissions. Stubs should always be removed

or terminated properly usually with a resistor matching the impedance close to

the branch location.

What checks can help determine if my layout is manufactureable?

The key manufacturability checks are:

1. Design validation testing - run design rule checks that model manufacturing capabilities
looking for violations
2. DFM analysis - sophisticated tools can run simulations based on proposed stackup, layer
materials, trace specs, etc to predict manufacturability
3. Prototype testing - submit prototypes to the intended fabricator to confirm capabilities
firsthand and uncover process limitations

Together these validate the design against electrical and physical

manufacturing constraints.

How can thermal analysis be done on the PCB layout?

Thermal profiles can be simulated across the layout in dedicated thermal

modeling tools like Ansys Icepak. The material properties, layer construction,

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weight/volume of components, and potential air flows are modeled. Applying

power loads then predicts overall temperatures to identify hot spots.

Analysis is critical for high power boards. External changes like adding a heat

sink, relocating components, or routing to improve heat spreading may be

done to pass thermal requirements. IR inspection of prototypes validates

temperature performance before production.

Summary

The translation from schematic to layout completes an electronic product's

journey from logical concept to physical implementation. Careful attention to

organizing, routing connections, and integration best practices ensures the

board can progress smoothly to fabrication, assembly, and reliable operation

in the field.

Leveraging the guidance provided throughout this 3500+ word article equips

you with the methodology to tackle PCB layout for a robust design. Let the

completion of routing be the start of the next exciting stage of testing and

refinement as your product nears deployment.

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