Tuesday, October 31, 2023 10:53 PM

Consider the following instructions are executed in five stage pipeline:

lw
add
sub

RI, O(R2)
R3, R4, R5
R6, RI, R3

fixplain the flow of execution in a pipeline using a simple diagram. 2. a.Consider the following
instructions are executed five stage pipclinc: lw R
Explain the now of execution in a pipeline using a simple diagram

b. For the instruction mix above, on what instruction results does the last add instruction depend on?
3. Indicate the type of hazards and data dependences for the following instructions: (5)
b. Iw R5, - 16(R5)
sw R5, - - 6(R5)
add R5, R5, R5

4. For the above sequence, add nop instructions to eliminate the hazards. Assume that there is no
forwarding in this pipelined processor.
5. Discuss, the schemes for dealing with the pipeline stalls caused by branch hazards. (3)

Discuss, the schemes for dealing with the pipeline stalls caused by branch hazards.
ChatGPT
Sure, let's dive into the strategies for mitigating pipeline stalls caused by branch hazards.
1. Branch Prediction:
• Static Prediction: This involves predicting branches at compile-time based on the program's
structure. However, it may not be very accurate for dynamic and runtime-dependent branches.
• Dynamic Prediction: Here, the processor predicts the outcome of a branch during runtime.
Two-level predictors, tournament predictors, and neural branch predictors are examples of
dynamic prediction techniques.
2. Branch Target Buffer (BTB):
• A BTB is a cache that stores target addresses of recent branches. When a branch instruction
is encountered, the BTB is checked to fetch the predicted target address. This can help in
reducing stalls as the pipeline can continue with the predicted instruction.
3. Delayed Branching:
• Instructions following a branch are executed regardless of the branch outcome. If the branch is
taken, the pipeline is flushed, and incorrect instructions are discarded. This reduces the impact
of branch stalls but may lead to wasted cycles if the prediction is incorrect.
4. Out-of-Order Execution:
• Modern processors often use out-of-order execution, allowing instructions after a branch to be
executed even before the branch outcome is determined. If the branch prediction was correct,
the results are committed; otherwise, the pipeline is rolled back.
5. Speculative Execution:

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5. Speculative Execution:
• Similar to out-of-order execution, speculative execution involves executing instructions based
on predicted branch outcomes. If the prediction is correct, the results are committed;
otherwise, the speculatively executed instructions are discarded.
6. Loop Buffer:
• A loop buffer is a small, fast cache that stores recently executed instructions in loops. It helps
in predicting loop branches more accurately, reducing the number of mispredicted branches.
7. Software Pipelining:
• This is a compiler optimization technique that reorganizes the code to minimize pipeline stalls.
It can be used to overlap the execution of multiple iterations of a loop, reducing the impact of
branch hazards.
Each of these techniques comes with its advantages and limitations. The effectiveness of a
particular scheme may depend on the characteristics of the code being executed and the
architecture of the processor.

From <https://chat.openai.com/c/cb22d345-9d92-4035-ad45-9cbc0fb32bb6>

4.13.1: As we know lw used to load word from memory to a register. and sw same but stores a
register into memory add to adds together its two operands.

Instruction sequence Dependences

a
I1: lw $1,40($6)
I2: add $6,$2,$2
I3: sw $6,50($1)

RAW on $1 from I1 to I3
RAW on $6 from I2 to I3
WAR on $6 from I1 to I2 and I3

b
I1: lw $5,-16($5)
I2: sw $5,-16($5)
I3: add $5,$5,$5

RAW on $5 from I1 to I2 and I3

WAR on $5 from I1 and I2 to I3
WAW on $5 from I1 to I3

4.13.2: In the basic five-stage pipeline WAR and WAW dependences do not cause any hazards. Without
forwarding, any RAW dependence between an instruction and the next two instructions (if register read
happens in the second half of the clock cycle and the register write happens in the fi rst half). The code
that eliminates these hazards by inserting nop instructions is:

Instruction sequence
a
lw $1,40($6)
add $6,$2,$2
nop
sw $6,50($1)

Delay I3 to avoid RAW hazard on $1 from I1

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b
lw $5,-16($5)
nop
nop
sw $5,-16($5)
add $5,$5,$5

Delay I2 to avoid RAW hazard on $5 from I1

Note: No RAW hazard from on $5 from I1 now

4.13.3: With full forwarding, an ALU instruction can forward a value to EX stage of the next instruction
without a hazard. However, a load cannot forward to the EX stage of the next instruction (by can to the
instruction after that).The code that eliminates these hazards by inserting nop instructions is:

Instruction sequence
a
lw $1,40($6)
add $6,$2,$2
sw $6,50($1)

No RAW hazard on $1 from I1 (forwarded)

b
lw $5,-16($5)
nop
sw $5,-16($5)
add $5,$5,$5

Delay I2 to avoid RAW hazard on $5 from I1

Value for $5 is forwarded from I2 now
Note: no RAW hazard from on $5 from I1 now

4.13.4 The total execution time is the clock cycle time times the number of cycles. Without any stalls, a
three-instruction sequence executes in 7 cycles (5 to complete the fi rst instruction, then one per
instruction). The execution without forwarding must add a stall for every nop we had in 4.13.2, and
execution forwarding must add a stall cycle for every nop we had in 4.13.3. Overall, we get:

No forwarding With forwarding Speed-up due to forwarding

(7 + 1) × 300ps = 2400ps

7 × 400ps = 2800ps

0.86 (This is really a slowdown)

(7 + 2) × 200ps = 1800ps

(7 + 1) × 250ps = 2000ps

0.90 (This is really a slowdown)

4.13.5 With ALU-ALU-only forwarding, an ALU instruction can forward to the next instruction, but not to
the second-next instruction (because that would be forwarding from MEM to EX). A load cannot forward

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the second-next instruction (because that would be forwarding from MEM to EX). A load cannot forward
at all, because it determines the data value in MEM stage, when it is too late for ALU-ALU forwarding.
We have:

Instruction sequence
a

lw $1,40($6)
add $6,$2,$2
nop
sw $6,50($1)

Can’t use ALU-ALU forwarding, ($1 loaded in MEM)

lw $5,-16($5)
nop
nop
sw $5,-16($5)
add $5,$5,$5

Can’t use ALU-ALU forwarding ($5 loaded in MEM)

4.13.6: Total execulation time of this instruction sequence with different condition ALU-ALU, NO
forwarding are given bellow.

No forwarding With ALU-ALU forwarding only Speed-up with ALU-ALU forwarding

(7 + 1) × 300ps = 2400ps

(7 + 1) × 360ps = 2880ps

0.83 (This is really a slowdown)

(7 + 2) × 200ps = 1800ps

(7 + 2) × 220ps = 1980ps

0.91 (This is really a slowdown)

2A

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