ME (Updated)
ME (Updated)
Microelectronics L P C
3 3
Marking Scheme:
1. Teachers Continuous Evaluation: 25 marks
2. Term end Theory Examinations: 75 marks
Instructions for paper setter:
1. There should be 9 questions in the term end examinations question paper.
2. The first (1st) question should be compulsory and cover the entire syllabus. This question should be
objective, single line answers or short answer type question of total 15 marks.
3. Apart from question 1 which is compulsory, rest of the paper shall consist of 4 units as per the syllabus.
Every unit shall have two questions covering the corresponding unit of the syllabus. However, the student
shall be asked to attempt only one of the two questions in the unit. Individual questions may contain upto
5 sub-parts / sub-questions. Each Unit shall have a marks weightage of 15.
4. The questions are to be framed keeping in view the learning outcomes of the course / paper. The standard
/ level of the questions to be asked should be at the level of the prescribed textbook.
5. The requirement of (scientific) calculators / log-tables / data tables may be specified if required.
Course Objectives :
1. To comprehend semiconductor physics, band theory, and material behavior, demonstrating
knowledge of semiconductor applications in electronic devices.
2. To analyze and design analog and digital circuits, exhibiting skills in circuit analysis techniques for
complex electronic systems.
3.
4.
CO 4
Course Outcomes (CO) to Programme Outcomes (PO) mapping (scale 1: low, 2: Medium, 3: High)
PO01 PO02 PO03 PO04 PO05 PO06 PO07 PO08 PO09 PO10 PO11 PO12
CO 1 3 3 3 2 2 1 1 - - 2 1 2
CO 2 2 3 3 2 3 1 2 - 1 2 2 2
CO 3 2 3 3 2 3 1 2 - 1 2 2 2
CO 4 2 3 3 2 3 1 2 - 1 2 2 2
UNIT I
Applicable from Batch Admitted in Academic Session 2021-22 Onwards Page 1112
Handbook of B.Tech. Programmes offered by USICT at Affiliated Institutions of the University.
UNIT II
CMOS inverter and its DC characteristics, Static & dynamic power dissipation. Rise time, fall time delays, noise
margin. Combinational CMOS logic circuits, pass transistor and transmission gate designs, Sequential MOS
logic circuits: SR latch, CMOS D latch and edge triggered flip flop. Dynamic CMOS logic circuits: Domino CMOS
logic, NORA CMOS logic, Zipper, TSPC.
UNIT III
Current Mirrors and Differential Amplifiers, Operational Amplifiers (Op-Amps) Design: Ideal vs. Practical
Models, Frequency Response of Op-Amps, Feedback Topologies (Voltage, Current, and Transconductance
Feedback), Voltage Reference Circuits, Linear Voltage Regulators, Switching Voltage Regulators, Stability
Analysis and Compensation Techniques.
Unit IV
Static RAM (SRAM) Design: 6T Cell, Read and Write Operations, Dynamic RAM (DRAM) Design: Basic Cell,
Refresh Techniques, Flash Memories: NOR and NAND Architectures, Non-Volatile Memories Design: EEPROM,
Ferroelectric RAM (FeRAM), MRAM, Low-Power IC Design Techniques, Analog-to-Digital Converters (ADCs),
Digital-to-Analog Converters (DACs), Radio-Frequency Integrated Circuits (RFICs): Basics and Applications.
Textbooks:
1. Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2016). Digital Integrated Circuits: A Design Perspective.
Pearson.
2. Razavi, B. (2016). Design of Analog CMOS Integrated Circuits. McGraw-Hill Education.
3. Weste, N. H. E., & Harris, D. (2015). CMOS VLSI Design: A Circuits and Systems Perspective. Pearson.
4. Kang, S. M., & Leblebici, Y. (2016). CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill
Education.
References:
1. Gray, P. R., Hurst, P. J., Lewis, S. H., & Meyer, R. G. (2001). Analysis and Design of Analog Integrated
Circuits. Wiley.
2. Malvino, A. P., & Bates, J. A. (2012). Electronic Principles. McGraw-Hill Education.
3. Sedra, A. S., & Smith, K. C. (2014). Microelectronic Circuits. Oxford University Press.
4. Lee, T. H. (2004). The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press.
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