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6 Addressingmodes

This document discusses ARM addressing modes including: - Pre-indexed addressing with fixed offsets, offset registers, and scaled offset registers. - Pre-indexed with write-back and fixed offsets. - Post-indexed addressing with fixed offsets. It also covers little vs big endian, LDR and ADR pseudo-instructions for PC relative addressing, and accessing bit-addressable memory in SRAM and peripherals.

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41 views21 pages

6 Addressingmodes

This document discusses ARM addressing modes including: - Pre-indexed addressing with fixed offsets, offset registers, and scaled offset registers. - Pre-indexed with write-back and fixed offsets. - Post-indexed addressing with fixed offsets. It also covers little vs big endian, LDR and ADR pseudo-instructions for PC relative addressing, and accessing bit-addressable memory in SRAM and peripherals.

Uploaded by

vokhacnam2k1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPS, PDF, TXT or read online on Scribd
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Arm Addressing Modes

Chapter 6

Sepehr Naimi

www.NicerLand.com
Topics
• Alignment
• Little endian vs. Big endian
• Advanced Indexed Addressing Modes
• LDR pseudo-instruction & PC relative addressing
• Bit-addressable memory

2
ARM Memory

3
Alignment and misalignment

4
16-bit data and memory alignment

5
Little endian vs. Big endian
LDR R2, =0x7698E39F
; R2=0x7698E39F
LDR R1, =0x80000000
STR R2, [R1]
• Little endian

• Big endian

6
Advanced indexed
addressing modes

7
Advanced Indexed Addressing Modes
• Pre-indexed addressing
– with Fixed Offset
– with Offset register
– With scaled offset register
• Pre-indexed with write-back
– With fixed offset
• Post-indexed addressing
– With fixed offset

8
Pre-indexed Addressing Mode with Fixed Offset

• STR Rd, [Rm, #k]


• LDR Rd, [Rm, #k]

LDR R5, [R2, #4] ; R5 = contents of location R2+4


9
Pre-indexed Address mode with Offset register

• LDR Rd, [Rm, Rn] • LDR Rd, [Rm, Rn,shift]


• STR Rs, [Rm, Rn] • STR Rs, [Rm, Rn,shift]

• LDR R5, [R2, R1] ; R5 = contents of loc. R2+R1


• LDR R6, [R2, R1, LSL #2] ; R6= [R2+(R1<<2)]
10
Look-up table
• Assuming R2 has the x value range of 0–6, the
program calculates 10 to the power of R2 and
stores the result in R3.

EXPORT __main
AREA LOOKUP_EXAMP_6_16, READONLY, CODE
__main
LDR R1, =LOOKUP ; point to LOOKUP
LDR R3, [R1, R2, LSL #2] ; R3 = entry of lookup table index by R2

HERE B HERE ; stay here forever

LOOKUP DCD 1, 10, 100, 1000, 10000, 100000, 1000000


END

11
Pre-indexed Addressing mode with write-
back and fixed offset
• LDR Rd, [Rm, k]!
• STR Rd, [Rm, k]!

12
Post-indexed Addressing mode
• LDR Rd, [Rm], #k
• STR Rd, [Rm], #k

13
LDR and ADR Pseudo-
instructions and PC
Relative addressing

14
PC Relative addressing
• LDR Rd, [PC, #k]

15
LDR Pseudo-instruction

EXPORT __main
AREA EXAMPLE, READONLY, CODE
__main
LDR R0, =0x12345678
LDR R1, =0x86427531
ADD R2, R0, R1
H1 B H1
END

16
ADR Pseudo-instruction
• ADR Rn, Label
– ADD Rn, PC, #offset

17
ADR Pseudo-instruction Example
EXPORT __main
AREA LOOKUP_EXAMPLE, READONLY, CODE
__main
ADR R2, OUR_FIXED_DATA ; R2 points to OUR_FIXED_DATA
LDRB R0, [R2] ; load R0 with the contents
; of memory pointed to by R2
ADD R1, R1, R0 ; add R0 to R1
HERE B HERE ; stay here forever
OUR_FIXED_DATA
DCB 0x55, 0x33, 1, 2, 3, 4, 5, 6
END

18
Bit-addressable
Memory

19
SRAM bit-addressable Memory

Bit alias address = Bit alias base address + Byte offset × 32 + Bit number × 4

20
Peripheral bit-addressable region

21

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