3.36 Using the style of drawing in Figure 3.

66, draw a picture of a PLA programmed to implement

VDD VDD
x1 x2 x3

f1 f2
3.44 Consider the function f (x1, x2, x3) = x1.x2 + x1 x3 + x2 .x3 . Show a circuit using 5 two-input
lookup-tables (LUTs) to implement this expression. As shown in Figure 3.39, give the truth table
implemented in each LUT. You do not need to show the wires in the FPGA.
Solution:
f = x1.x2 + x1 x3 + x2 .x3
x1 x2 f = x .x
1 1 2
x1 x3 f 2 = x1.x3 x2 x3 f 3 = x2 .x3
0 0 0 0 0 0 0 0 0
0 1 0 0 1 0 0 1 0
1 0 1 1 0 0 1 0 1
1 1 0 1 1 1 1 1 0

f1 f2 f 4 = f1 + f 2 = x1 x2 + x1.x3 1 1 1
0 0 0
0 1 1
f4 f3 f = f 4 + f 3 = x1 x2 + x1.x3 + x2 .x3
1 0 1
0 0 0 1 1 1
0 1 1
1 0 1

x1 0
0 f1 = x1.x2
1
x2 0 0
f4 = f1 + f2 = x1.x2 + x1.x3
1
1
x1 0 1
0
0
f = f3 + f 4 = x1.x2 + x
1
0 f 2 = x1.x3
x3 1
1 1

x2 0
f3 = x2 .x3
0
1
x3
0

3.45 Consider the function f (x1, x2, x3) =∑m(2, 3, 4, 6, 7). Show how it can be realized using
two two-input LUTs. As shown in Figure 3.39, give the truth table implemented in each
LUT. You do not need to show the wires in the FPGA.3.45
Solution:

f ( x1, x2 , x3 ) = ∑m(2,3,4,6,7) =x1.x2.x3 + x1.x2.x3 + x1.x2.x3 + x1.x2.x3 + x1.x2.x3

f = x1.x2 .x3 + x1.x2 .x3 + x1.x2 .x3 + x1.x2 .x3 + x1.x2 .x3 + x1.x2 .x3
f = x1.x2 ( x3 + x3 ) + x1.x3 ( x2 + x2 ) + x1.x2 ( x3 + x3 )
f = x1.x2 .1 + x1.x3 .1 + x1.x2 .1
f = x1.x2 + x1.x2 + x1.x3
( )
f = x1 + x1 .x2 + x1.x3
f = x2 + x1.x3
x1 x3 f1 = x1.x3 f1 x2 f = f1 + x2 = x1.x3 + x2
0 0 0 0 0 0
0 1 0 0 1 1
1 0 1 1 0 1
1 1 0 1 1 1

x1

0
0

f1

0
1 1
0
f = f1 + x2

x3

1
1

x2

3.49 Assume that a gate array contains the type of logic cell depicted in Figure P3.9. The inputs
in1, . . . , in7 can be connected to either 1 or 0, or to any logic signal.
(a) Show how the logic cell can be used to realize f = x1x2 + x3.
(b) Show how the logic cell can be used to realize f = x1x3 + x2x3.
Solution:
(a)
f = x1.x2 + x3 = x1.x2 .x3 + 1.x3
two inputs

f = x1.x2 + x3 = x1.x2 . x3 + 1.x3

Control signal
Again
 two inputs

x1.x2 = x2 .x1 + 0.x1

Control signal

x1

x2 X1.X2

f = x1.x2 + x3 = x1.x2 .x3 + 1.x3

1
1
1
x3

(b)
f = x1.x3 + x2 .x3 = ( x1 + x2 ).x3 + 0.x3
two inputs

f = x1.x3 + x2 . x3 = ( x1 + x2 ).x3 + 0. x3

Control signal
Again
 two inputs

x1 + x2 = x2 .x1 + 1.x1

Control signal

x1

x2 X1+X2

f = x1.x3 + x2 .x3 = ( x1 + x2 ).x3 + 0.x3

0
0
0
x3

3.50 Assume that a gate array exists in which the logic cell used is a three-input NAND gate. The
Inputs to each NAND gate can be connected to either 1 or 0, or to any logic signal. Show how the
following logic functions can be realized in the gate array. (Hint: use DeMorgan’s theorem.)
(a) f = x1 .x 2 + x3 (b) f = x 1 x 2 x 4 + x 2 x 3 x 4 + x 1
Solution:
(a)
f = x1 .x 2 + x3
f = x1 .x 2 + x3 = x1 .x 2 ..x3 = P.Q
f = x1 .x 2 ..x3
Here P is output of a 3 input NAND gate with inouts: 1, x1, x2
And Q is output of a 3 input NAND gate with inouts: 1, 1, x3
x1 x1.x2
x2
1

f = x3 + x1.x2
x3 x3
1
1 1
(b)
f = x 1x 2 x 4 + x 2 x 3 x 4 + x1
f = x 1 x 2 x 4 + x 2 x 3 x 4 + x 1 = x 1 x 2 x 4 . x 2 x 3 x 4 .x 1 = P.Q.x1
f = P.Q.x1

x1 P = x1.x2 .x4
x2
x4

Q = x1.x2 .x4 f = P.Q.x1

x4 x4
1
1
3.54 What logic gate is realized by the circuit in Figure P3.10? Does this circuit suffer from any
major drawbacks?
Solution:
The circuit in Figure P3.10 is a two-input XOR gate. Since NMOS transistors are used
only to pass logic 0 and PMOS transistors are used only to pass logic 1, the circuit does
not suffer from any major drawbacks.
3.55 What logic gate is realized by the circuit in Figure P3.11? Does this circuit suffer from any
major drawbacks?

Solution: The circuit in Figure P3.11 is a two-input XOR gate. The circuit has two major
drawbacks.
1. when both the inputs are 0, the PMOS transistor must drive f to 0, resulting in f=Vt
volts.
2. when Vx1=1and Vx2=0, the NMOS transistor must drive the output high, resulting
f=VDD-Vt