Scribd
Upload
35 views

Computer System Architecture Chapter 1 Part 5

The document describes a computer instruction set and control unit architecture. It includes 1) arithmetic, logical and shift instructions, 2) instructions to move data between memory and registers, 3) program control instructions, and 4) input/output instructions. It then discusses hardwired versus microprogrammed control units, describing their relative advantages and disadvantages. Pipeline processing is also introduced as a technique to improve processor throughput.

Uploaded by

Vansh Rana
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
35 views

Computer System Architecture Chapter 1 Part 5

The document describes a computer instruction set and control unit architecture. It includes 1) arithmetic, logical and shift instructions, 2) instructions to move data between memory and registers, 3) program control instructions, and 4) input/output instructions. It then discusses hardwired versus microprogrammed control units, describing their relative advantages and disadvantages. Pipeline processing is also introduced as a technique to improve processor throughput.

Uploaded by

Vansh Rana
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 8

Coznputer Jnstetions

Memary Refecence J-1OPCODE ADRRESsJ


AND AND meroty wordto AC
ADD 4XXX AD memyy word to AC
LDA 2XX AxXX Load me mer y wotd to C
STA 3 XXX Store contert ot HC to memoy
BUN Bramch Unton diionally
BSA S XXX 8anch and Save retutn address
ISZ 6 XXX EXXX Jncrement and Sipf zeco

Keg'ster Retezence RElaREF


CLA 7800 Clear AC
CLE 7400 Cear E
CMA 7200 Complement AC
CME 7100 Complement E
CIL 7080 Circular shit AC (let)
CIR Cicular shit Ac (right)
S PA 7010 Saip if positve AC
SNA 7o 08 SRip it negatue AC
SZA SRip if 1e0 AC
S ZE Too2 Skip i Lero E
HLT 7001 Halt
JNC 70 20 Increment .

[ToCHO]
JNP F&00 Jnput chaca cter to Ac
OUT Dutput Charactez fom Ac
SHI
S Ho F100
Fo8 Jntet n
JoF FoHo Jnterrupt eff.
Jhslu ion Set (ompletancss
1. Acithnetc, logial mnd Shit perions.
2. Jnstuctans to moveitotmaton to aond tam
memory and processor Teg'stes,
3. Progom Conttol instzudios toConatios
gethez taith
lnstu ctors that chech status

4. Jrput and Output instructons.


HARuiREN ONTRJL
The control logic s implemeted Loth g,
fub-hyps, decodes, and sther digital cizzus.
Hyantage : Opmized to produre fist mode
of operatione
Disaluntage: Regutesthechangcs in the ieing
vsious Compone
f the destqn is medhed changed
YCAOPROG RAMMED (oN TAOL
e Any requitad changs modihcstios
can be dona by updating he nictoprodn:
D eontol mema y.
Harduired Contol Uni E Micrprogtarmed Gttol Unt
Hardited cotrol unit gener ates Microprogeammed contral uni
the canteal signals need ed genecates he contralsignas
tor the pt«ess or Using logic Mith the help ot nt czo -instotos
cac uts. stored in control me mory.

Harduited control yntt is faskr This is slouer tan te ather


when compared to microqtagtawnal as micro instructians are used
Control Unit as the required tor generating signak hee.
Contal slanals are qenerated
Lith he hep of hacd wates.
Dificutt to modify aa the Easy to modify as the noifidta
Contzal siqnals that need to heed to be cone only at he
be generaBed are hatawized. instrucHon level.

Mo re costiee as cverything less costilr than haed uized


has to be realizeJ n terms Control s anly mico instuctens
of logic gae are sed tor generahng
control signals.
Jtcanst handle compler instochas } Can handle comple
as the c'ut design tor it instuctors.
becomes complex.
Only linited uiler ot instroctan Control signala tor many
are se ioue to the instwdens can be generded.
haxduare inmplevnentation.
sed in RISC Usec CISC.
CoNTROE
11-0
other
Inputs

|765 43 2 1 0

I
Conbi
Ts gats
2 J0

deroder

4-bi+ Treenent (1NR)


Scquene Clear (caR
(oonter
(Sc) Clock

AR PC
JRAMAR], PCe-PCt1
I-JRLS)
JR (0-11)
Dy, ..., D, Dode JR(12-I9,
Executon Flou Chaz
Start
SC+-0

ARPC

TR -MA]

Deccde JR(2-4)

-6 (aicect)

Citoyte Eserote
Rratrrrt Noh

Enerute
PipaiNiNG
His a techmique of decomposing a sequential proceas
into suboperations, special cleie
wih cach Tubprocess being executed in a all
egment that operates concuzenty wih otther spats.
H can be visualized s a collectan of processing
ments through luhtdh binary vacmation flaus.
Seg
partial procesig dictated
Each segment pecfarmsk parttonad.
by the way the' task
The resul abtaied teom he compuBatien in esch Sgm
is tcansteced to the Ment segment in the ppel'ne.

KIhe overlapping ot CompuBatioyn ik mate posble


re¡ister lwith each segment in
the pipeline.

Four-segment pipdne
eed) to
orProcess
, non-pipeline or
pipeline usg when
pcocess to
time same takes ituming 4ss
t
n)(Rin-1 far
ptocessor pipeline tofen
by Tie t
processornon-pipeline tahen
by Tine Atetber ti
pipelne segments
in Number
of R:
tasRs Number
ot m:
(Rm-1)tp
S
busSySTEM
A Common bus aystem r seven CPU registers
is shoum belowi

R3

R5
RS

der der Kbus

9uttut
3
SELA SEL3SFLO OPR

You might also like