ECE 428 Programmable ASIC Design

Timing Issues in FPGA Synchronous

Circuit Design

Haibo Wang
ECE Department
Southern Illinois University
Carbondale, IL 62901

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 FPGA Design Flow

Schematic HDL
Design Entry
capture coding

Function Simulation

Synthesis,
Implementation Technology mapping
placement and routing

Timing Verification

Download

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 Introduction to Synchronous Circuits
‰ What are synchronous circuits?
— In synchronous circuits, latching data in to memory elements (D
flip-flops) are synchronized by a number of clocks.

Comb. Comb.
DFF logic DFF logic DFF

CLK

‰ Why synchronous design?

— Well developed design methodologies
— Easy to design, debug, and testing
— Currently, most ASICs are synchronous circuits

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 D Flip-Flop Timing Parameters

D Q

CLK

CLK

tS setup time tH hold time

tclkÆQ clock to Q propagation delay

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 Critical Path in Combinational Circuits

Critical path

‰ Critical Path: The signal path that has the longest propagation delay

— Assume that each gate has the same delay d

— The delay of the critical path in the above circuit is 3•d

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 Determine Maximum Clock Frequency

Comb. Comb.
DFF Logic 1 DFF Logic 2 DFF

clk

‰ The delays of the critical paths in comb. logic 1 and comb. Logic 2 are
d1 and d2, respectively. In addition, d1>d2

Minimum clock period T = tCLKÆQ + d1 + tS

T
tCLKÆQ d1 tS

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 Slow Combinational Logic
‰ Clock period is selected. The propagation delay of Comb. Logic 2
is too large

Comb. Comb.
DFF Logic 1 DFF Logic 2 DFF

clk

T
tCLKÆQ d1 tS

Set-up time violation

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 Too Fast Combinational Logic
‰ Clock period is selected. The propagation delay of Comb. Logic 2
is too small

Comb. Comb.
DFF Logic 1 DFF Logic 2 DFF

clk

Thold Timing to guarantee correct data latched in DFF

Old Data New Data

Old Data New Data

d1
tCLKÆQ Hold time violation
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 Clock Skew
‰ Due to interconnect delay, the same clock signal may switch at different
time depending on the distance from the clock source. This effect is called
clock skew.
Comb. Comb.
DFF Logic 1 DFF Logic 2 DFF

3ns clk1 1ns clk2 2ns

Propagation delay
CLK
caused by interconnect

clk1 clk1

clk2
clk2
tCLKÆQ d1 tS
tCLKÆQ d1 tS
Setup time
Signal propagation Signal propagation violation
Without clock skew With clock skew
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 Clock Skew

Comb. Comb.
DFF Logic 1 DFF Logic 2 DFF

1ns clk1 5ns clk2 2ns

Propagation delay
CLK
caused by interconnect

clk1 clk1

clk2
clk2

thold thold

With clock skew

tCLKÆQ dl
tCLKÆQ dl

Without clock skew Hold time violation

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 Techniques to Reduce Clock Skew
‰ Use global buffers to distribute clock signals to minimize clock skew.

— Modern FPGAs normally contain dedicated buffers (global buffers) to distribute

clock signals around FPGA chips.
— The global buffers are connected through specially balanced routing resources
to minimize clock skew.
— Use symbol BUFG to indicate the use of global buffers in schematic entry.
Most synthesis tools can automatically use global buffers for clock signals
— In latest FPGAs, more sophisticated circuit techniques, such as Phase-Locked
Loop (PLL), are used to minimize clock skew .

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Timing Constraints in Synchronous Circuits
Shortest path tds

DFF DFF

Longest path tdl

clock
tsk

‰ To avoid setup time violation

tclk − >Q + t dl + t setup ≤ Tclk + t sk

‰ To avoid hold time violation
tclk − >Q + t ds ≥ t hold + t sk
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 Techniques to Avoid Timing Violations
‰ Insert delay elements on clock path to avoid setup time violations

Comb.
data DFF Logic DFF

clock

‰ Insert delay elements on data path to avoid hold time violations

Comb.
data DFF Logic DFF

clock

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 Specifying Timing Constraints in ASIC Design
‰ Timing constraints are used to specify delay of circuit paths

‰ The end points of paths can be D flip-flops, Latches, Input or

Output pads, and Memories

Path between DFFS

Path from IPAD to DFF Path from DFF to OPAD

IPAD logic logic OPAD

FF FF

IPAD

logic OPAD
IPAD

Path from IPAD to OPAD

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 Period Constraint
‰ Period constraints specify delay of paths between synchronous
elements that are clocked by the same clock
— Period constraint is also called register-to-register delay
— Synchronous elements include D flip-flops, latches, and synchronous Rams
— In the following example, the period constraint specify delay of a path
between two D flip-flops

Path between DFFS

IPAD logic logic OPAD

FF FF

IPAD

logic OPAD
IPAD

The delay of the path tdl < T - tCLKÆQ - tS

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 Offset Constraint
‰ Offset constraints specify delays of paths:
— From input pads to synchronous elements. The constraints for this
type paths are called as offset in constraints. For the input paths,
external setup time and external hold time have to be considered

— From synchronous elements to output pads. The constraints for this

type paths are called as offset out constraints.

Offset In Constraints Offset Out Constraints

IPAD logic logic logic OPAD

FF FF

IPAD logic

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 External Setup Time

tS : DFF setup time

tDATA

IPAD logic logic logic OPAD

FF FF

IPAD logic

tCLK

‰ Worst case setup time for input occurs when input is DELAYED
relative to CLK. Means clock edge arrives early, requiring input
to be ready sooner.

External setup time = tS + tDATA(max) – tCLK(min)

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 External Hold Time
tH : DFF hold time
tDATA

IPAD logic logic logic OPAD

FF FF

IPAD logic

tCLK

‰ Worst case hold time for input occurs when CLK is DELAYED
relative to input. Means clock edge arrives late, requiring input
to hold its value longer.

External hold time = tH + tCLK(max) – tDATA(min)

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 Pad-to-Pad Time Constraint

IPAD logic logic OPAD

FF FF

IPAD

logic OPAD
IPAD
Pad-to-Pad time constraint

‰ It specifies delays for paths that are from input pads to

output pads

‰ Purely combinatorial delay paths do not contain any

synchronous elements

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 Specifying Time Constraints in Xilinx Tools
‰ Example circuit

clk

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Specifying Time Constraints in Xilinx Tools

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 Report from Static Timing Analysis
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
--------------------------------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic
| | | Levels
--------------------------------------------------------------------------------------------------------
TS_CLK = PERIOD TIMEGRP "CLK" 20 nS HI | 20.000ns | 3.568ns | 1
GH 50.000000 % | | |
--------------------------------------------------------------------------------------------------------
COMP "A" OFFSET = IN 10 nS BEFORE COMP " | 10.000ns | 1.788ns | 2
CLK" | | |
-------------------------------------------------------------------------------------------------------
* COMP "B" OFFSET = IN 1000 pS BEFORE COMP | 1.000ns | 1.334ns | 2
"CLK" | | |
------------------------------------------------------------------------------------------------------
COMP "O" OFFSET = OUT 10 nS AFTER COMP " | 10.000ns | 9.352ns | 1
CLK" | | |
-------------------------------------------------------------------------------------------------------

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 Flow for Achieving Timing Closure
Modify circuit or
HDL coding style
Schematic HDL
capture coding
Design Entry

•••
Increase P&R effort level

Implementation

Timing Verification

Yes Meet timing No

Done
Constraints? Are constraints realistic?

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 What Affect Circuit Timing Performance
™ Environmental factors

‰ Commercial Products are expected to work in the following environment

— Supply voltage varies 10%

— Temperature from 0 to 85 °C

‰ Fast Corner (circuits have small delay)

— Supply voltage: VDD + VDD•10%; Temperature: 0 °C

‰ Slow Corner (circuits have large delay)

— Supply voltage: VDD - VDD•10%; Temperature: 85 °C

‰ Perform timing analysis at fast corner to check hold time violations

and perform timing analysis at slow corner to check setup time
violations
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 What Else Affect Circuit Timing Performance
™ Process variations
‰ NFET (fast, slow, typical)
‰ PFET (fast, slow, typical)
‰ Interconnect (fast, slow, typical)

‰ Due to process variations and other factors, including

operating voltage, circuit design, etc, devices from the same
family can achieve different operating speeds:

Source: www.xilinx.com
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 Example on Calculating Timing Parameters
‰ Calculate timing parameters

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 Calculating Timing Parameters
‰ Maximum register to register delay
U2 Tc2q + U3 Tpd + U1 Tsu= 5 + 8 + 3 = 16 ns.

‰ External setup time

Tsu + A2D Tpd max - Clk Tpd min = 3 + (8 + 1) - 2 = 10 ns

‰ External hold time

Thd + Clk Tpd max - A2D Tpd min = 4 + 2 - (7 + 1) = -2 ns

‰ Clock to Out Delay

U8 Tpd + U2 Tc2q + U5 Tpd + U6 Tpd = 2 + 5 + 9 + 6 = 22 ns

‰ Pad to pad Delay

U7 Tpd + U5 Tpd + U6 Tpd = = 1 + 9 + 6 = 16 ns

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 Interface with Asynchronous Inputs
Q1 Q2
Asynchronous signal logic
FF FF
Synchronous
circuit
CLK

1
Asynchr. Signal Undefined region
0

CLK Metastable state

1
Q1
0

‰ If the asynchr. input is in undefined region when the DFF latches it, the DFF output
will be possibly in metastable state. The DFF output will eventually settle to logic 1
or 0. However, this process must complete with a certain period. Otherwise, it will
be a failure.
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 Potential Problems of Metastability
‰ Due to metastability, the same signal may be treated as having
different logic values in different part of the circuit

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 Metastability Analysis
‰ Mean Time Between Failure: MTBF

tr
eτ
MTBF =
T0 • f in • f clock

Where,
1. tr is metastability resolution time, maximum time the output can remain
metastable without causing synchronizer failure.
2. T0 and τ are constants that depend on the electrical characteristics
of the flip-flop.
3. fin is the frequency of the asynchronous input
4. fclock is the frequency of the sampling clock

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 Increasing MTBF
‰ Mean Time Between Failure: MTBF

D Q D Q Synchronous
circuit
Asynchronous
signal

CLK
Synchronizer

The use of synchronizer can significantly reduce Main-Time-Between-Failure (MTBF)

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 ASIC with Multiple Clock Domains
‰ A group of circuits that are clocked by the same signal is referred
to as a clock domain

Clock domain 1
FLOP FLOP FLOP
ADATA OUT1
D Q D Q D Q

CLK1

Clock domain 2
BUFG FLOP FLOP

D Q D Q OUT2
BUS [7..0]
CLK2

CDATA
= Combinatorial Logic
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Communication Between Different Clock Domains
‰ Methods for different clock domain communication

9 Using synchronizer
9 Using FIFO
9 Using handshaking protocols

Synchronizer

clk2

Clock domain 1 Clock domain 2

FIFO

Handshaking

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