DIGITAL ELECTRONICS

ECE 213
Unit-4 Introduction to Sequential Logic Circuit

Dr Suman Lata Tripathi

Professor, VLSI Design
School of Electronics and Electrical Engineering
Lovely Professional University, Punjab, India-144411
 Sequential circuit
• A combinational circuit produces an output based on input variables
only, but a sequential circuit produces an output based on current
input and previous output variables.
• It consists of a combinational circuit along with storage elements
connected to form a feedback path.
• Two main types of sequential circuits, and their classification is a
function of the timing of their signals.
• A synchronous sequential circuit is a system whose behaviour can be
defined from the knowledge of its signals at discrete instants of time.
• The behaviour of an asynchronous sequential circuit depends upon
the input signals at any instant of time and the order in which the
inputs change.
• A synchronous sequential circuit employs signals that affect the
storage elements at only discrete instants of time. Synchronization is
achieved by a timing device called a clock generator, which provides
a clock signal having the form of a periodic train of clock pulses .

Eg. Flip-flops, shift registers, counters etc.

 Combinational Vs Sequential Logic
Combinational Circuit Sequential Circuits

1) The outputs of the combinational circuit The outputs of the sequential circuits
depend only on the present inputs. depend on both present inputs and
present state(previous output).

2) The feedback path is not present in the The feedback path is present in the
combinational circuit. sequential circuits.
3) In combinational circuits, memory elements are In the sequential circuit, memory
not required. elements play an important role and
require.
4) The clock signal is not required for The clock signal is required for
combinational circuits. sequential circuits.
5) The combinational circuit is simple to design. It is not simple to design a sequential
circuit.
Sequential circuit
• Two main types of sequential circuits, and their classification is a function of the timing of their
signals.
• A synchronous sequential circuit is a system whose behaviour can be defined from the knowledge
of its signals at discrete instants of time.
• The behaviour of an asynchronous sequential circuit depends upon the input signals at any instant
of time and the order in which the inputs change.
• A synchronous sequential circuit employs signals that affect the storage elements at only discrete
instants of time. Synchronization is achieved by a timing device called a clock generator, which
provides a clock signal having the form of a periodic train of clock pulses .

Eg. Flip-flops, shift registers, counters etc.

Storage Elements
• A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input signal to switch states.
• Storage elements that operate with signal levels (rather than signal transitions) are referred to as
latches
• those controlled by a clock transition are flip-flops .

• Eg. lateches and flip-flops

 Latches are sensitive to
a) Clock logic level
b) Clock transition
c) Clock edge
d) Both b and c

Sequential circuit in digital electronics includes

a) Logic gates
b) Registers
c) clock
d) All of the above
SR(Set-Reset) latch • SR latch with NOR gate
• SR latch with NAND gate
SR latch with enable

1
0
Level sensitive
Enable signal

EN S R Q Q’
Truth Table
0 x x NC NC
1 0 0 NC NC
1 0 1 0 1
1 1 0 1 0
1 1 1 Invalid Invalid
SR Flip flop

CLK S R Q Q’
x x NC NC
0 0 NC NC
0 1 0 1
1 0 1 0
1 1 intermediate intermediate

Q(t+1)=S+R’Q(t)
D Latch
• D-latch with NAND gate
• Drawbacks of clocked R-S flip-flop are overcome in D (delay) flip-flop.
• The transfer of data from the input to the output is delayed, the
flip-flop is named delay (D) flip-flop.
D- flip flop
CLK D Q Q’
x NC NC
0 0 1
1 1 0
Keyword
• Latches and Flipflop
• Synchronous and asynchronous sequential circuit
• Combinational and Sequential circuit

Q.1 A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
J-K flip flop
• The functioning of J-K flop-flop is identical to that of the R-S flip-flop
in RESET, SET, and no change conditions of operation.
• The difference is that the J-K flip-flop has no invalid state as does the
R-S flip-flop.
• J-K flip-flop is a very versatile device
• It has wide application in digital devices such as counters, registers,
arithmetic logic units, and other digital systems.
J-K flip-flop

Truth table

CLK J K Qn+1 Actio J K Q Qn+1

n 0 0 0 0
x x Qn NC 0 0 1 1

0 0 Qn NC 0 1 0 0
0 1 1 0
0 1 0 Reset
1 0 0 1
1 0 1 Set
1 0 1 1
1 1 Qn’ Toggle
1 1 0 1
1 1 1 0
MCQ
Q1. On a J-K flip-flop, when is the flip-flop in a hold condition?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Q2. In J-K FF when j=k=1, and current sate Q=1 what will be next output state
a) 0
b) 1
c) x
d) z
 T – Flip-Flop
This flip-flop is basically a J-K flip-flop.
This is also called Trigger or Toggle
flip-flop.
This has only a single data input(T), a
clock input and two outputs Q and Q′.

Q(t+1)= TQ’(t)+T’Q(t)

clk T Qn+1 Output Output T Output Input (T) Output

(Qn) (Qn+1) (Qn) (Qn+1)
x Qn
0 0 0 0 0 0
0 Qn
0 1 1 0 1 1
1 Qn’
1 0 1 1 0 1
a) Truth Table 1 1 0 1 1 0
b)Excitation table
c) Characteristics table
 MCQ
In T-flipflop, if input value 1 then next output state Q+ will be
a) 0
b) 1
c) Q’
d) Q
Excitation Table
It predicts about the flip-flop input values depending on the present and next
state
00
01

10 11
00 10

01
11
MCQ
Q. For Q(n)=0 and Q(n+1)=0, then the values for S,R will be
a) 0,1
b) 1,0
c) 0,X
d) X,0
Characteristic Table, Characteristic Equation
and Excitation Table
MCQ
Q. The correct Boolean expression of characteristic equation of J-K flip
flop is
a) JQ+K’Q’
b) JQ’+K’Q
c) (J+K)Q
d) (J+K)Q’
Race around condition in J-K flip Flop
• Race around condition in J-K flip flop:
In j—k flip flop when both j and k inputs are high and when clock pulse width is greater than the
prorogation delay of flip flop. In this situation flip ideally toggled only once but toggles more than
once. This condition is called race around condition. To prevent this either prorogation delay time
should greater than pulse width or use master slave flip flop.
• Or uncertainty in determining output state of flip flop due toggling when J=K=1 and clock high for
too long period> Propagation delay
• Master -slave flip flop stops continuous toggling by slave filp -flop with clk=0 that shows the state
of no change.
Master-slave J-K flip-flop

The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration.
One flip-flop acts as the “Master” circuit, which triggers on the leading edge of the clock
pulse while the other acts as the “Slave” circuit, which triggers on the falling edge of the
clock pulse.
This results in the two sections, the master section and the slave section being enabled
during opposite half-cycles of the clock signal.
MCQ
Q. Race around condition in J-K flip flop appear when
a) Clock period is higher than propagation delay
b) Clock period is lower than propagation delay
c) Clock period is equal to propagation delay
d) None of the above
Contd.
• The input signals J and K are connected to the gated “master” SR flip flop which “locks” the input
condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip
flop is the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle.

• The outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the clock
input goes “LOW” to logic level “0”.

• When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional
changes to its inputs are ignored. The gated “slave” flip flop now responds to the state of its inputs
passed over by the “master” section
Interview Questions
• Race around condition
• Truth table, Characteristic Table and Excitation table
• Characteristic equation
Conversion of J-K in to S-R flip flop
Conversion of D flip-flop in J-K flip flop
for D
Conversion of J-K in T flip flop

For J For K
Conversion of S-R into D
MCQ
Q. In SR to D FF conversion, the required input values for SR for D=1,
Qn=0 & Q(n+1)=1
a) 0,0
b) 0,1
c) 1,0
d) 1,1
Conversion of S-R into J-K flip flop
• SR into JK

S=JQp’
MCQ
• For Qn=1 and Q(n+1)=0, the J-K input will be
a) 0,0
b) 0,1
c) X,1
d) 1,X