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Design of Reconfigurable Direct Digital Synthesizer Using FPGA SoC

The document outlines a project to design a reconfigurable direct digital synthesizer (DDS) using an FPGA system on chip (SoC). The main activities include designing the DDS datapath architecture and RTL description using Verilog or high-level synthesis, integrating the DDS intellectual property (IP) core with a Zynq SoC, and performing hardware-software co-design and co-simulation. Upon completion, students will understand FPGA SoC design flows, gain expertise in Verilog/HLS design, and learn hardware-software co-design of embedded applications. Milestones include DDS datapath design, IP integration and interface with the Zynq SoC, and software and analog front-

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Huzaifa Yasir
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37 views3 pages

Design of Reconfigurable Direct Digital Synthesizer Using FPGA SoC

The document outlines a project to design a reconfigurable direct digital synthesizer (DDS) using an FPGA system on chip (SoC). The main activities include designing the DDS datapath architecture and RTL description using Verilog or high-level synthesis, integrating the DDS intellectual property (IP) core with a Zynq SoC, and performing hardware-software co-design and co-simulation. Upon completion, students will understand FPGA SoC design flows, gain expertise in Verilog/HLS design, and learn hardware-software co-design of embedded applications. Milestones include DDS datapath design, IP integration and interface with the Zynq SoC, and software and analog front-

Uploaded by

Huzaifa Yasir
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Design of Reconfigurable Direct Digital

Synthesizer using FPGA SoC


Project Supervisor
Dr. Muhammad Awais
Project Co-Supervisors
Name1/ Name2
Desig.1/ Desig.2
Background and Motivation
Direct digital synthesis (DDS) is a method for generating radio frequency waveforms using all
digital techniques. In contrast to the phase lock loop based oscillators which are designed using
analog components, the DDS is based on digital components. DDS technique is rapidly gaining
acceptance for solving frequency- (or waveform) generation requirements in both
communications and industrial applications because single-chip IC devices can generate
programmable analog output waveforms simply and with high resolution and accuracy. In this
project we shall exploit the inherent capabilities of Field Programmable Gate Arrays (FPGAs) to
design a complete system on chip solution of a flexible direct digital synthesizer. The main
activities of projects include design of datapath architecture of DDS core, its RTL description
using HDL (Verilog or High Level Synthesis), integration of DDS IP core with Zynq System on
Chip and hardware-software co-design (co-simulation).

Objectives
After completion of this project the students shall be able to;
• Understand the complete design flow of a system on chip design of and embedded
application of a practical complexity.
• Get expertise in RTL (Verilog/HLS) design of an application from software defined radio
domain.
• Learn how to perform hardware-software co-design of an embedded application
Societal Impact and SDGs
• SDG. 9, Industry and Innovation. Investigate a flexible design of a core component of a
communication system using an advanced FPGA based design flow.

Milestones with Priority


Sr. Milestone Priority Estimated
# time
1 Understand the working 1 1
and architecture of a DDS
months
2 Datapath design and RTL 1 2 months
coding using Verilog/HLS

3 Synthesis of design and 1 1 month


simulation

4 IP export and connecting 1 1-2


the IO interface with the IP
core months
5 IP integration with Zynq 2 1 months
SoC

6 Software design and 2 1 month


analog front end design
Team Composition with Justification
• Student-1 (Electro/Comp) → design the datapath and RTL coding
• Student-2 (Electro/Comp/Telecom) → design the datapath and RTL
coding. Both students shall jointly perform the hardware-software
co-simulation and integration

Development Tools
1) Matlab ( For generating the digital samples of analog waveform)

2) Xilinx-AMD Vivado Design suite

3) Xilinx-AMD SDK

4) Zynq / Pynq FPGA Board.

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