Introduction to P4 Programming

CS5229 Advanced Computer Networks

TA: Khooi Xin Zhe
Why Data Plane Programmability?

2
 Recap: Switch/ Router Architectures

Routing Information
Base (RIB) OSPF, BGP, … Control-plane CPU
Forwarding
Information Base (FIB)
Control plane
Runtime API
IPv4 Match-action/ Lookup Tables
Switching ASIC
packets
Data plane

…
Broadcom Cisco Intel Juniper 3
Tomahawk5 Silicon One Tofino2 Trio6
Source: https://sdn.systemsapproach.org/intro.html 4
 Bottom-up Design

Switch OS
Network Demands

?
“This is how I know to process packets”
(i.e. the ASIC datasheet makes the rules)
Run-time API
Driver

Fixed-function ASIC

Inflexible data plane, slows down development!

5
 Top-down Design

Switch OS
Network Demands

Feedback

Run-time API
Driver

P4
“This is how I want the network to
behave and how to switch packets…”
(the user / controller makes the rules)

P4 Programmable Device

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Reconfigurable Match-action Tables (RMT)

7
 Benefits of Data Plane Programmability
• New Features – Add new protocols
• Reduce complexity – Remove unused protocols
• Efficient use of resources – flexible use of tables
• Greater visibility – New diagnostic techniques, telemetry, etc.
• SW style development – rapid design cycle, fast innovation, fix data
plane bugs in the field
• You keep your own ideas

Think programming rather than protocols…

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 Innovations Enabled by Data Plane Programmability
• Fine-grained RDMA Load Balancing – ConWeave[1]
• In-band Network Telemetry – INT[2]
• In-Network Caching – NetCache[3]
• In-Network Aggregation for Distributed ML [4]
• Masking Corrupted Fibre Optic Links[5]
• Byzantine Fault Tolerance Acceleration - NeoBFT[6]
• 5G FrontHaul Network Slicing - FSA[7]
• (Very) Precise Time Synchronisation - DPTP[8]
• … and much more!
[1] CH Song, et al., "Network Load Balancing with In-network Reordering Support for RDMA", ACM SIGCOMM, 2023.
[2] C Kim, et al. "In-band network telemetry via programmable data planes.” ACM SIGCOMM. 2015.
[3] J Xin, et al. “NetCache: Balancing Key-Value Stores with Fast In-Network Caching.” ACM SOSP. 2017.
[4] A Sapio, et al. "Scaling Distributed Machine Learning with In-Network Aggregation." USENIX NSDI, 2021.
[5] J Raj, et. al., "Masking Corruption Packet Losses in Datacenter Networks with Link-local Retransmission”, ACM SIGCOMM, 2023.
[6] G Sun, et. al., "NeoBFT: Accelerating Byzantine Fault Tolerance Using Authenticated In-Network Ordering”, ACM SIGCOMM, 2023.
[7] B Nishant, et. al., "FSA: Fronthaul Slicing Architecture for 5G using dataplane programmable switches”, ACM MOBICOM, 2021.
[8] PG Kannan et. al., “Precise Time-synchronization in the Data-Plane using Programmable Switching ASICs”, ACM SOSR, 2019.
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10
Questions?

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Introduction to P4

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 Language evolution

● P4: Programming Protocol-Independent Packet Processors

○ Pat Bosshart, Dan Daly, Glen Gibb, Martin Izzard, Nick McKeown, Jennifer
Rexford, Cole Schlesinger, Dan Talayco, Amin Vahdat, George Varghese, David
Walker ACM SIGCOMM Computer Communications Review (CCR). Volume 44,
Issue #3 (July 2014)
● P4_14
○ Original version of the language
○ Assumed specific devices capabilities
○ Good only for a subset of programmable switch/ targets
● P4_16
○ More mature and stable language definition
○ Does not assume device capabilities, which instead are defined by target
manufacturer via external libraries/ architecture definition
○ Good for many targets, e.g., switches/ NICs, whether programmable or
fixed-function

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P4_16 Specification

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 Available Software Tools

• Compilers for various back-ends

• Intel Tofino ASIC, DPDK, eBPF, Xilinx FPGA
(open-source and proprietary)
• Multiple control-plane implementations
• SAI, OpenFlow, P4Runtime
• Software Simulators/ Models
• Testing tools (Packet Test Framework)
• Sample P4 programs
• Tutorials

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 P4 Approach

Term Explanation

P4 Target An embodiment of a specific hardware implementation

Provides an interface to program a target via some set of P4-programmable components,

P4 Architecture externs, fixed components

Community-Developed Vendor-supplied

P416 P416 Core Extern Architecture

Language Library
Libraries Definition

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Mapping a simple logical pipeline on PISA

17
P4 programs and architectures

18
 Example Architectures and Targets
V1Model/ PISA Architecture
Software
TM
Switch
Tofino Native Architecture*
(P4_14)

Portable Switch Architecture (PSA)

TM
Software
Switch
Tofino Native Architecture*

Portable NIC Architecture (PNA)

SmartNICs (IPUs, DPUs…) 19

 P4 Language Elements

State machine,
Parsers bitfield
extraction

Tables, Actions,
Controls control flow
statements

Basic operations
Expressions and operators

Bistrings, headers,
Data Types structures, arrays

Architecture Programmable blocks

Description and their interfaces

Support for specialized

Extern Libraries components

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 Programming a P4 Target

User supplied

Control Plane

RUNTIME
P4 Program P4 Compiler Add/remove Extern Packet-in/out
table entries control

CPU port
P4 Architecture Target-specific Extern
configuration Load Tables Data Plane
Model objects
binary

Target
Vendor supplied
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 Protocol-Independent Switch (PISA)/ V1Model
Architecture
Programmer defines the
tables and the exact Programmer declares
Programmer declares the processing algorithm how the output packet
headers that should be will look on the wire
recognized and their order in
the packet

Programmable Match-Action Pipeline

Programmable Programmable
Parser Deparser

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 P4 Program Template (V1Model)
#include <core.p4> /* EGRESS PROCESSING */
#include <v1model.p4> control MyEgress(inout headers hdr,
/* HEADERS */ inout metadata meta,
struct metadata { ... } inout standard_metadata_t std_meta) {
struct headers { ...
ethernet_t ethernet; }
ipv4_t ipv4; /* CHECKSUM UPDATE */
} control MyComputeChecksum(inout headers hdr,
/* PARSER */ inout metadata meta) {
parser MyParser(packet_in packet, ...
out headers hdr, }
inout metadata meta, /* DEPARSER */
inout standard_metadata_t smeta) { control MyDeparser(inout headers hdr,
... inout metadata meta) {
} ...
/* CHECKSUM VERIFICATION */ }
control MyVerifyChecksum(in headers hdr, /* SWITCH */
inout metadata meta) { V1Switch(
... MyParser(),
} MyVerifyChecksum(),
/* INGRESS PROCESSING */ MyIngress(),
control MyIngress(inout headers hdr, MyEgress(),
inout metadata meta, MyComputeChecksum(),
inout standard_metadata_t std_meta) { MyDeparser()
... ) main; 23
}
 V1Model Standard Metadata
struct standard_metadata_t {
bit<9> ingress_port; • ingress_port - the port on which
bit<9> egress_spec;
bit<9> egress_port; the packet arrived
bit<32> clone_spec;
bit<32> instance_type; • egress_spec - the port to which
bit<1> drop;
bit<16> recirculate_port; the packet should be sent to
bit<32> packet_length;
bit<32> enq_timestamp; • egress_port - the port that the
bit<19> enq_qdepth;
bit<32> deq_timedelta; packet will be sent out of (read
bit<19> deq_qdepth;
bit<48> ingress_global_timestamp; only in egress pipeline)
bit<32> lf_field_list;
bit<16> mcast_grp;
bit<1> resubmit_flag;
bit<16> egress_rid;
bit<1> checksum_error;
}

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 Simple P4 Program Example
#include <core.p4>
#include <v1model.p4> control MyEgress(inout headers hdr,
struct metadata {} inout metadata meta,
struct headers {} inout standard_metadata_t standard_metadata) {
apply { }
parser MyParser(packet_in packet, }
out headers hdr,
inout metadata meta, control MyComputeChecksum(inout headers hdr, inout metadata
inout standard_metadata_t standard_metadata) { meta) {
apply { }
state start { transition accept; } }
}
control MyDeparser(packet_out packet, in headers hdr) {
control MyVerifyChecksum(inout headers hdr, inout metadata apply { }
meta) { apply { } } }

control MyIngress(inout headers hdr, V1Switch(

inout metadata meta, MyParser(),
inout standard_metadata_t standard_metadata) { MyVerifyChecksum(),
apply { MyIngress(),
if (standard_metadata.ingress_port == 1) { MyEgress(),
standard_metadata.egress_spec = 2; MyComputeChecksum(),
} else if (standard_metadata.ingress_port == 2) { MyDeparser()
standard_metadata.egress_spec = 1; ) main;
}
}
} 25
Questions?

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Defining and (De-)Parsing Headers

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 P4 Types (Basic and Header Types)

Basic Types
• bit<n>: Unsigned integer (bitstring) of size n
typedef bit<48> macAddr_t; • bit is the same as bit<1>
• int<n>: Signed integer of size n (>=2)
header ethernet_t {
macAddr_t dstAddr; • varbit<n>: Variable-length bitstring
macAddr_t srcAddr;
bit<16> etherType; Header Types: Ordered collection of members
}
• Can contain bit<n>, int<n>, and varbit<n>
• Byte-aligned
• Can be valid or invalid
• Provides several operations to test and set validity bit:
isValid(), setValid(), and setInvalid()

typedef: Alternative name for a type

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Example: IPv4 Header

typedef bit<32> ip4Addr_t;

header ipv4_t {
bit<4> version;
bit<4> ihl;
bit<8> diffserv;
bit<16> totalLen;
bit<16> identification;
bit<3> flags;
bit<13> fragOffset;
bit<8> ttl;
bit<8> protocol;
bit<16> hdrChecksum;
ip4Addr_t srcAddr;
ip4Addr_t dstAddr;
}

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 P4 Types (Other Types)
/* Architecture */
struct standard_metadata_t {
Other useful types
bit<9> ingress_port;
bit<9> egress_spec; • Struct: Unordered collection of members (with
bit<9> egress_port;
bit<32> clone_spec; no alignment restrictions)
bit<32> instance_type;
bit<1> drop; • Header Stack: array of headers
bit<16> recirculate_port;
bit<32> packet_length; • Header Union: one of several headers
...
}

/* User program */
struct metadata {
...
}
struct headers {
ethernet_t ethernet;
ipv4_t ipv4;
}
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 Programmable Parsers

• Parsers are functions that map packets into start

headers and metadata, written in a state
machine style
• Every parser has three predefined states
◦ start
◦ accept
◦ reject
• Other states may be defined by the
programmer
• In each state, execute zero or more
statements, and then transition to another
state (loops are OK)
accept reject

Intuition: Think of JSON Serialization!

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 V1Model Parser

MyParser
/* User Program */
parser MyParser(packet_in packet, packet_in hdr
out headers hdr,
inout metadata meta,
inout standard_metadata_t std_meta) {
meta meta
state start {
packet.extract(hdr.ethernet); The platform Initializes
transition accept; User Metadata to 0
}

}
standard_meta

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 “select” statement

P416 has a select statement that can be

state start { used to branch in a parser
transition parse_ethernet;
} Similar to case statements in C or Java, but
without “fall-through behavior”—i.e., break
state parse_ethernet { statements are not needed
packet.extract(hdr.ethernet);
transition select(hdr.ethernet.etherType) { In parsers it is often necessary to branch
0x800: parse_ipv4;
based on some of the bits just parsed
default: accept;
}
} For example, etherType determines the
format of the rest of the packet

Match patterns can either be literals or

simple computations such as masks.
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 Deparsing

• Assembles the headers back into a

/* User Program */ well-formed packet
control DeparserImpl(packet_out packet,
in headers hdr) {
apply { • emit(hdr): serializes header if it is valid
...
packet.emit(hdr.ethernet);
... • Advantages:
} • Makes deparsing explicit but decouples
} from parsing

Intuition: Think of JSON Deserialization!

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Questions?

35
(Stateless) Packet Processing

36
 P4 Control Blocks

• Similar to C functions (without loops)

• Can declare variables, create tables, instantiate externs, etc.

• Functionality specified by code in apply statement

• Represent all kinds of processing that are expressible as DAG:

◦ Match-Action Pipelines
◦ Deparsers
◦ Additional forms of packet processing (updating checksums)

• Interfaces with other blocks are governed by user- and architecture-specified

types (typically headers and metadata)

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 Example: Reflector (V1Model)

control MyIngress(inout headers hdr,

inout metadata meta, Desired Behavior:
inout standard_metadata_t std_meta) {
/* Declarations region */
• Swap source and
bit<48> tmp; destination MAC
apply {
addresses
/* Control Flow */ • Bounce the packet back
tmp = hdr.ethernet.dstAddr; out on the physical port
hdr.ethernet.dstAddr = hdr.ethernet.srcAddr;
hdr.ethernet.srcAddr = tmp;
that it came into the
std_meta.egress_spec = std_meta.ingress_port; switch on
}
}

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 Example: Simple Actions
control MyIngress(inout headers hdr,
inout metadata meta, • Very similar to C functions
inout standard_metadata_t std_meta) { • Can be declared inside a control or
globally
action swap_mac(inout bit<48> src,
• Parameters have type and direction
inout bit<48> dst) {
bit<48> tmp = src; • Variables can be instantiated inside
src = dst; • Many standard arithmetic and logical
dst = tmp; operations are supported
} ◦ +, -, *
◦ ~, &, |, ^, >>, <<
apply { ◦ ==, !=, >, >=, <, <=
swap_mac(hdr.ethernet.srcAddr, ◦ No division/modulo
hdr.ethernet.dstAddr); • Non-standard operations:
std_meta.egress_spec = std_meta.ingress_port; ◦ Bit-slicing: [m:l] (works as l-value too)
} ◦ Bit Concatenation: ++
}

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 P4 Match-action Tables
• The fundamental unit of a Match-Action Pipeline
◦ Specifies what data to match on and match kind
◦ Specifies a list of possible actions
◦ Optionally specifies a number of table properties
■ Size
■ Default action
■ Static entries
■ …
• Each table contains one or more entries (rules)
• An entry contains:
◦ A specific key to match on
◦ A single action that is executed when a packet matches the entry
◦ Action data (possibly empty)

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 Example: IPv4_LPM Table

• Data Plane (P4) Program

◦ Defines the format of the table
10.0.1.1 10.0.1.2 ■ Key Fields
■ Actions
■ Action Data
◦ Performs the lookup
◦ Executes the chosen action
• Control Plane (IP stack,
Key Action Action Data Routing protocols)
10.0.1.1/32 ipv4_forward dstAddr=00:00:00:00:01:01 ◦ Populates table entries with
port=1 specific information
10.0.1.2/32 drop ■ Based on the configuration
*` NoAction ■ Based on automatic discovery
■ Based on protocol calculations
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 IPv4_LPM Table

table ipv4_lpm {
key = {
hdr.ipv4.dstAddr: lpm;
}
actions = {
ipv4_forward;
drop;
NoAction;
}
size = 1024;
default_action = NoAction();
}

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 Defining Actions

/* core.p4 */ • Actions can have two different

(DataPlane)
Parameters

Directional
action NoAction() { types of parameters
} ◦ Directional (from the Data Plane)
◦ Directionless (from the Control
/* basic.p4 */ Plane)
action drop() { • Actions that are called directly:
mark_to_drop(); ◦ Only use directional parameters Action
} • Actions used in tables: Code

◦ Typically use directionless

/* basic.p4 */ parameters

(Action Data)
Directionless

Parameters
action ipv4_forward(macAddr_t dstAddr, ◦ May sometimes use directional
bit<9> port) { parameters too
...
}
Action
Execution
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 Applying Tables in Controls

control MyIngress(inout headers hdr,

inout metadata meta,
inout standard_metadata_t standard_metadata) {
action drop(){
…
}

table ipv4_lpm {
...
}
apply {
...
ipv4_lpm.apply();
...
}
} 44
Demo

45
Questions?

46
(Stateless) Packet Processing - cont.

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 Hashing (V1Model)

enum HashAlgorithm {
csum16,
xor16,
crc32, Computes the hash of data (using algo)
crc32_custom,
crc16,
modulo max and adds it to base
crc16_custom,
random,
identity
Uses type variables (like C++ templates /
} Java Generics) to allow hashing primitive
extern void hash<O, T, D, M>(
out O result,
to be used with many different types.
in HashAlgorithm algo,
in T base,
in D data,
in M max);

bit<10> variable_to_output;
hash (variable_to_output, HashAlgorithm.crc32, 0,
{hdr.ipv4.src_addr, … }, 1024);

48
// here we have the hash value ready
ECMP as a Use Case

49
 Mirroring (V1Model)

Mirrors a copy of a packet for further

processing
… Primitives supported are:
clone(CloneType.I2E, 0);
CloneType.I2E
…
CloneType.E2E

50
 Multicast (V1Model)

Replicates multiple copies of the packets,

used for multicast/ broadcast

… Group members are configured through

the control plane to the Traffic Manager
standard_metadata.mcast_grp = GROUP_NUM;
…

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Stateful Packet Processing

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 What is “Stateful Packet Processing”?

● Packet processing decisions made on a particular packet is dependent on

states set by previous packets
● Examples:
○ Heavy-hitter detection
○ DDoS defense
○ L4 Firewall
○ NAT forwarding
○ Flowlet switching
○ …

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Registers in V1 Model

Note: TYPO, order of the

arguments is wrong for “read”

54
 Registers (V1Model)
Registers are used maintain states in the data plane

Similar to arrays in programming languages like C/C++, Java etc.

#define NUM_ENTRIES 1024

#define BIT_WIDTH 32
…
register<bit<BIT_WIDTH>>(1024) my_register; // register definition
…
bit<32> index = hash(...);
bit<32> value;
my_register.read(value, index); // register read action
…
value = value + 1;
…
my_register.write(index, value); // register write action

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 Example: Stateful Firewall
● Assume a network admin:
○ Allows connections to be initiated only from/ within an enterprise/home network
○ Blocks incoming connection requests from outside

● Typically used in stateful firewalls

External
Network Alice Bob
Server

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 Example: Stateful Firewall

Host Conn. State

Alice ESTABLISHED
OPEN
… …

2. SYN(Alice->Server)
1. SYN-ACK(Server->Alice)
External
Network Alice Bob
Serve
r

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 Example: Stateful Firewall

Host Conn. State

Alice ESTABLISHED
Seems like Bob did not … …
initiate the connection!

4. SYN(Server->Bob)
External
Network Alice Bob
Serve
r
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Bloom Filters
Wikipedia:
“A Bloom filter is a space-efficient probabilistic data structure, conceived by
Burton Howard Bloom in 1970, that is used to test whether an element is
a member of a set.”

Image source: https://www.kdnuggets.com/2016/08/gentle-introduction-bloom-filter.html

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Slides from: https://courses.cs.washington.edu/courses/cse312/20au/files/slides/10-23-annotated.pdf

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Meters in V1 Model Architecture

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Counters in V1 Model Architecture

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 Counters (V1Model)
Counters can be updated from the P4 program, but can only be read from the
control plane.

#define NUM_ENTRIES 1024

#define BIT_WIDTH 32
…
counter(NUM_ENTRIES, CounterType.packets) my_pkt_counts;
…
bit<32> index = hash(...);
…
my_pkt_counts.count((bit<32>) index);
…

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Using the V1 Model Counters

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Questions?

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Interested to working with us?

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Quiz 3

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Question 1:

68
Question 2:

69
Question 3:

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Question 4:

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Question 5:

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Question 6:

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 References
1. ONF P4 Tutorial: https://opennetworking.org/wp-content/uploads/2020/12/P4_tutorial_01_basics.gslide.pdf
2. ONF ONS Tutorial:
https://events19.linuxfoundation.org/wp-content/uploads/2017/12/Tutorial-P4-and-P4Runtime-Technical-Introduction-
and-Use-Cases-for-Service-Providers-Carmelo-Cascone-Open-Networking-Foundation.pdf
3. Standford CS344 Lecture 2: https://cs344-stanford.github.io/lectures/Lecture-2-P4-tutorial.pdf
4. P4 Introduction: https://conferences.sigcomm.org/sigcomm/2018/files/slides/hda/paper_2.2.pdf
5. ETH Zurich Adv Topics in Communication Networks: https://polybox.ethz.ch/index.php/s/dP7zuZH5Y9amcGG

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 NetCache: Balancing Key-Value
Stores with Fast In-Network Caching
Xin Jin1, Xiaozhou Li2, Haoyu Zhang3, Robert Soule2,4,
Jeongkeun Lee2, Nate Foster2,5, Changhoon Kim2, Ion Stoica6

1
John Hopkins University, 2Barefoot Networks, 3Princeton University,
4
Università della Svizzera italiana, 5Cornell University, 6UC Berkeley

Slides adapted from: https://opennetworking.org/wp-content/uploads/2020/12/p4-ws-2017-netcache.pdf

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 Goal: Fast and cost-efficient rack-scale KV stores
❑ Store, retrieve, manage key-value objects
▪ Critical building block for large-scale cloud services

▪ Need to meet aggressive latency and throughput objectives efficiently

❑ Target workloads
▪ Small objects
▪ Read intensive
▪ Highly skewed and dynamic key popularity

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 Key challenge:
Highly skewed and rapidly changing workloads

10% of items account for ~60-90% of queries1

Long tail
distribution

[1] Atikoglu et al., Workload Analysis of a Large-scale Key-value Store. 2012. ACM SIGMETRICS.

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 Key challenge:
Highly skewed and rapidly changing workloads

Q: How to provide effective dynamic load balancing?

78
 Opportunity:
Fast, small cache can ensure load balancing

Cache O(N log N) hottest items1

N = # of servers
Cache absorbs hottest queries E.g., 10,000 hot objects for
100 servers with 100B items

Balanced load
[1] Fan et al., Small Cache, Big Effect: Provable Load Balancing for Randomly Partitioned Cluster Services. 2011. ACM SOCC.
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 Opportunity:
Fast, small cache can ensure load balancing

I need to be able
absorb and handle all
the load for the cache
items!
Cache absorbs hottest queries
Requirement: cache throughput ≥ backend aggregate throughput

Balanced load

80
NetCache: Towards billions QPS KV store racks

Cache needs to provide the aggregate throughput of the storage layer

storage layer cache layer

cache
In-network
In-memory
O(1) BQPS
Each: O(10) MQPS
Total: O(1) BQPS Small on-chip memory? 10s of MB only.
Only cache O(N log N) small items!

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 NetCache Rack-scale architecture

Network Cache
Management Management

PCIE
Run-time API

Clients Network Key Value Query

Functions Store Statistics

Top of the rack switch Storage servers

❑ Switch Data Plane

▪ Key-value store to serve queries for cached keys
▪ Query statistics to enable efficient cache updates
❑ Switch Control Plane
▪ Insert hot items into the cache and evict less popular items
▪ Manage memory allocation for on-chip key-value store 82
 Data Plane Query Handling

Read 1
Query Hit Cache Update Stats
2
(cache hit) Client
Server

Read Query 1 2
(cache Miss Cache Update Stats
miss) 4 3
Client
Server

1 2
Write
Query Invalidate Cache Stats
4 3
Client Server
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The “boring life” of a NetCache switch

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Backup Slides

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 Control Plane

(DataPlane)
Parameters

Directional
Headers and Metadata
Lookup Key

Hit
Key Action ID Action Data
Action

ID
Action ID
Code

Selector
Hit/Miss

(Action Data)
Directionless

Parameters
Data

Headers and Headers and

Metadata
Default Default
Action Metadata
(Input) Action ID Action Data
Execution (Output)

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Recap

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Slides from: https://courses.cs.washington.edu/courses/cse312/20au/files/slides/10-23-annotated.pdf

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