Jagannath International Management School

Vasant Kunj, New Delhi-110070

(Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Recognized u/s 2(f) by UGC & Accredited with ‘A+’ Grade by NAAC
Participant of UNGC New York and ISO 9001:2015 Quality Certified

Programme: BCA Semester: III

Course: Computer Organization and Architecture Paper Code: BCA-203
Academic Session: August 2023 – Dec 2023

TABLE OF CONTENTS (TOC)

S. No. Contents Page No.

e.g.(1.1 – 1.5)
1. Syllabus

2. Course Delivery & Assessment Plan

3. Assignments

4. Mid Term Papers

5. Unit-wise Question Bank

6. End Term Question Papers

(Last Five Years)
7. Additional Reading Material

8. Case Studies (if applicable)

 Jagannath International Management School
Vasant Kunj, New Delhi-110070
(Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Recognized u/s 2(f) by UGC & Accredited with ‘A+’ Grade by NAAC
Participant of UNGC New York and ISO 9001:2015 Quality Certified

Programme: BCA Semester: III

Course: Computer Organization and Architecture Paper Code: BCA-203
Academic Session: August 2023 – Dec 2023

SYLLABUS

UNIT – I

No. of Hours: 11 Chapter/Book Reference: TB2[Chapter-2, 4], RB1 [Chapter-5, 6]

Boolean Algebra and Logic: Basics Laws of Boolean Algebra, Logic Gates, Simplifications of Boolean
equations using K-maps SOP and POS, Don’t Care condition.

Arithmetic Circuits: Adder, Subtractor, Parallel binary adder/Subtractor.

UNIT – II

No. of Hours: 11 Chapter/Book Reference: TB2 [Chapter-5, 6], RB1[Chapter-6,7]

Combinational Circuits: Multiplexers, De-Multiplexers, Decoders, Encoders.

Flip-flops: S-R, D, J-K, T, Clocked Flip-flop, Race around condition, Master slave Flip-Flop,
Realisation of one flip-flop using other flip-flop, Applications of flip flop: Latch, Registers, Counters
(elementary treatment to be given).

UNIT – III

No. of Hours: 11 Chapter/Book Reference: TB1[Chapter-5, 9], RB3[Chapter-11]

Data Transfer Operations: Register Transfer, Bus and Memory Transfer, Registers and micro-
operations. Basic Computer Organizations and Design: Instruction Codes, Computer Registers,
Instruction Cycle, General Register Organization, Stack Organization, Instruction Formats, Addressing
Modes

UNIT – IV

No. of Hours: 11 Chapter/Book Reference: TB1[Chapter-12, 13], RB3[Chapter-7]

Input-Output Organization: Peripheral Devices, Input-Output Interfaces, Asynchronous Data Transfer,
Modes of Transfer, Priority Interrupt, Direct Memory Access (DMA)
Memory Organization: Main Memory, Auxiliary Memory, Associative Memory, Cache Memory,
Virtual Memory.

TEXT BOOKS
[TB1]. Morris Mano, Computer System Architecture, 3rd Edition, Prentice-Hall of India Private
Limited, 1999.
[TB2] Moris Mano, “Digital Logic and Computer Design”, PHI Publications, 2002
REFERENCES:
[RB1]. R. P. Jain, “Modern Digital Electronics”, TMH, 3rd Edition, 2003.
[RB2]. WIliam Stallings, Computer Organization and Architecture, 4th Edition, Prentice Hall
of India Private Limited, 2001
[RB3]. Subrata Ghosal,” Computer Architecture and Organization” , Pearson 2011
[RB4]. Malvino, “Digital Computer Electronics: An Introduction to Microcomputers”, McGraw Hill
 Jagannath International Management School
Vasant Kunj, New Delhi-110070
(Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Recognized u/s 2(f) by UGC & Accredited with ‘A+’ Grade by NAAC
Participant of UNGC New York and ISO 9001:2015 Quality Certified

Programme: BCA Semester: III

Course: Computer Organization and Architecture Paper Code: BCA-203
Academic Session: August 2023 – Dec 2023

COURSE DELIVERY & ASSESSMENT PLAN

LEARNING OBJECTIVES:

In this course, the learners will be able to develop expertise related to the following:

1. To study the various logic gates and design principles of different digital electronic circuits

2. To design different combinational and sequential circuits.

3. Identify the functional units of the processor and the factors affecting the performance of a
computer

4. To learn about the Input –Output organization of a typical computer

PRE-REQUISITES: Physics

Course Delivery & Assessment Plan

Course Title Computer Organization and Design
Core or Elective Core
Program and Batch BCA (Batch: 2022-25)
Semester & Academic Year 3rd and August 2023 – Dec 2023
Credits 4
Discipline/Area IT
Provide details, if this course is a Prerequisite None
for any course/specialization
Name of the Faculty Member/Course Ms. Snehlata
Instructor

Contact Details of the Faculty Member Email-Id: [email protected]

Mobile: 9599267269

Contact Details of Support Staff [email protected]

 Consultation Day/s & Time Monday: 02:00PM to 03:00PM
Wednesday: 02:00PM to 03:00PM

Introduction to the Course:

Computer Organization and Architecture is a core subject and cover topics such as Boolean algebra, k-
maps, arithmetic circuits, flip flops and counters. Data transfer operations, input-output organization
and memory organization will also be covered.

Program Outcomes (PO):

It is envisioned that the graduates Description
passing out BCA degree, will
achieve the following objectives
and will be able to Programme
Objectives (POs)
PO1 Understand the fundamental concepts of Computers, Software
hardware and peripheral devices and evolution of computer
technologies.
PO2 Familiarized with Business environment and Information
Technology and its Applications in different domains.
PO3 Gain knowledge to identify, explain and apply functional
programming and object-oriented programming techniques and use
of databases to develop computer programs.
PO4 Analyze, design, implement and evaluate computerized solutions to
real life problems, using appropriate computing methods including
web applications.
PO5 Understand the front end and backend of software applications.
PO6 Gain expertise in at least one emerging technology.
PO7 Acquire knowledge about computer networks, network devices and
their configuration protocols, security concepts at various level etc.
PO8 Apply techniques of software validation and reliability analysis to
the development of computer programs.
PO9 Acquire Technical, Communication and management Skills to
convey or present information, applications, instructions, policies,
procedures, decisions, documentations etc. verbally as well as in
writing.
PO10 Recognize the various issues related to society, environment, health
and vivid cultures and understand the responsibilities to contribute in
providing the solutions.
PO11 Acquire technical skills to lead a productive life in the society as a
professional or as an entrepreneur.

Course Objectives (CO):

CO1: Able to understand the fundamentals of digital principles and able to design digital circuits by
simplifying the Boolean functions.

CO2: Implement the combinational and sequential circuits for the given specifications.

CO3: Able to trace the execution sequence of an instruction through the processor.
CO4: Demonstrate computer architecture concepts related to design of modern processors, memories
and I/Os.

CO5: Demonstrate the ability to classify the addressing modes, instructions set.

Course Program Outcomes Assessment

Objectives (COs) (POs) *BT Level Item
On successful This course helps you This learning
completion of the to develop the outcome will be
course, students following Program Bloom ‘s assessed in the
should Outcomes: Taxonomy following items
be able
to:
CO1 PO1, PO7, PO11 BTL2, BTL3, BTL5 A1, A2, A3, A4

CO2 PO1, PO4, PO7, PO11 BTL3, BTL6, A1, A2, A3, A4
BTL1
CO3 PO1, PO7, PO11 BTL1, BTL2 A1, A2, A3, A4

CO4 PO1, PO4, PO7, PO11 BTL2, BTL4 A1, A2 A4

CO5 PO1, PO4, PO7, PO11 BTL2, BTL5 A1, A2, A4

Evaluation:
The students will be continuously assessed during the course on the following basis:-

1st Mid-Term Examination : 15 Marks

Internal Assessment (Presentation Assignments) : 5 Marks
Attendance : 5 Marks
End Term Examinations : 75 Marks
Total Marks : 100 Marks

Assessment Assessment Weightage Nature Week of POs to be

Item Task Assessment Assessed
A1 Class 5% Individual/ Week 4 PO1, PO4, PO5,
Participation Group PO6, PO8
(Discussion,
Guest Lectures,
Regularity)
A2 Quiz/ 5% Individual Week 4, PO1, PO4, PO5,
Assignment/ Week 4 PO6, PO8
Presentation
A3 Class Test 15% Individual Week-8 PO1, PO4, PO5,

A4 End-term exam 75% Individual After Week- PO1, PO4, PO5,

17 PO6, PO8
 Description of Assessments:
 A1: Class Participation (Discussion, Guest Lectures, Regularity) (5%): The participation
of the students in the class discussion, attending Guest Lectures and regularity in class shall
be evaluated out of 5 marks.
 A2: Quiz/Assignment/Presentation (5%): During the semester, participation in Quiz/
Assignment/Presentation shall be evaluated out of 5 marks.
 A3: Class Test (15%): There will be a class Test of 15 marks on the completion of week 7.
 A4: End-Term Exam (75%): End term examination will be conducted by the university and
shall be evaluated out of 75 marks.

Teaching Pedagogy:
Computer Organization and Architecture is a core subject and PowerPoint presentation & white board
are used while teaching. Videos are also used to make teaching more effective.

Methodology:
 The pedagogy will be lectures, Power Point presentations and exercises.
 Audio visual aids will be used extensively during the course.

Teaching Pedagogy

Class white board Power-

50% point
Presenta-
tion
40%

You Tube Videos

10%

SESSION PLAN

Unit Topic and Sub Topics Learning Outcome References COs Covered

Week-1
I Boolean Algebra and
Logic: Basics Laws of
Boolean Algebra, To learn about basics of CO1
Boolean algebra along
I Logic Gates with laws and logic gates
[T1] [T2][R1] CO1
[R2]
I CO1
Simplifications of Boolean
 equations

Week-2
I using K-maps SOP
CO1
[T1] [T2][R1]
I and POS [R2]
To learn about the CO1
designing of k-maps
I Don’t Care condition using POS and SOP
CO1

Week-3
I Arithmetic Circuits:
Adder CO2
To learn about
implementation and [T1] [T2][R1]
I Subtractor CO2
designing of various [R2]
circuits used for
I Parallel binary adder arithmetic operations CO2

Week-4
I Parallel binary Subtractor. To learn about arithmetic
and combinational circuit [T1] [T2][R1] CO2
designing [R3]

II Combinational Circuits:
Multiplexers CO2

II De-Multiplexers,
CO2

Week-5
II Decoders To learn about
combinational and CO2
sequential circuit
II Encoders designing
[T1] [T2][R1] CO2
[R3]
II Flip-flops: S-R,
CO2

Week-6
II D, J-K To learn about sequential CO2
circuit designing

II T Flip Flop [T1] [T2][R1] CO2

[R3]
II Clocked Flip-flop CO2

Week-8
II Race around condition To learn about sequential CO2
circuit designing

II Master slave Flip-Flop CO2

[T1] [T2][R1]
II Realisation of one flip-flop CO2
[R3]
using other flip-flop

Week-9
II Applications of flip flop: To learn about sequential CO2
Latch (Latch) circuit designing along
with counters
II Registers CO2
[T1][T2][R1]

II Counters CO2

Week-10
III Data Transfer operations To learn about various
RTL types of computer CO2
registers [T1][T2][R1]

III Bus and memory transfer CO3, CO5

III Registers & mircoperations CO3, CO5

Week-11
III Basic Computer To understand the CO3, CO5
Organizations and Design: instruction cycle along
Instruction Codes with implementation of [T1][T2][R1]
III stack CO3, CO5

Instruction Cycle
III General Register CO3, CO5
Organization
Week-12

III Stack Organization CO5

To understand about
III Instruction Formats addressing modes along [T1][T2][R1] CO5
with pipelining
III Addressing Modes CO5

Week-13

IV Input-Output To learn about different CO4

Organization: Peripheral peripheral devices and
Devices their interfaces [T1] [T2][R3]

IV Input-Output Interfaces CO4

IV Asynchronous Data CO4

Transfer

Week-14
IV Modes of Transfer To understand the CO4
concept interrupts and
IV Priority Interrupt direct memory access [T1] [T2][R3] CO4

IV Direct Memory Access CO4

(DMA)

Week-15
IV priority interrupt. To understand the CO4
concept interrupts and [T1] [T2][R3]
IV Memory Organization: memory access CO4
Main Memory

Week-16
IV Auxiliary Memory CO4
To study about different
types of memory
IV Associative Memory CO4
[T1] [T2][R3]
IV Cache Memory, Virtual CO4
Memory.

TEXT BOOKS
[TB1]. Morris Mano, Computer System Architecture, 3rd Edition, Prentice-Hall of India Private
Limited, 1999.
[TB2] Moris Mano, “Digital Logic and Computer Design”, PHI Publications, 2002

REFERENCES:
[RB1]. R. P. Jain, “Modern Digital Electronics”, TMH, 3rd Edition, 2003.
[RB2]. WIliam Stallings, Computer Organization and Architecture, 4th Edition, Prentice Hall
of India Private Limited, 2001
[RB3]. Subrata Ghosal,” Computer Architecture and Organization” , Pearson 2011
[RB4]. Malvino, “Digital Computer Electronics: An Introduction to Microcomputers”, McGraw Hill

e-journals
1. International Journal of Computer Engineering in Research Trends
Journals
1. International Journal of IT, BVICAM, Vol 11, No 2, June 2019
Magazines

1. DATAQUEST: New It For New Normal

2. PCQUEST
Websites
1. https://www.webopedia.com
2. https://www.encyclopedia.com/science-and-technology/

Ethics:
All graded assignments are intended to determine your individual skills, abilities, understanding
and knowledge. If you are having difficulty with your work, it is important to seek help from
your course instructor rather than be tempted to use unfair means to gain marks. Cheating can
be of different forms, although any form of cheating is strictly forbidden. These are, but not
limited to:
 Submitting other people's work as your own - either with or without their knowledge.
 Impersonation - taking an assessment on behalf of or pretending to be another student or
allowing another person to take an assessment on your behalf or pretend to be you.
 Plagiarism - taking or using another person's thoughts, writings or inventions as your own.
To avoid plagiarism, you must make sure that quotations, from whatever source, are
clearly identified and attributed at the point where they occur in the text of your work by
using one of the standard conventions for referencing. It is not enough just to list sources
in a reference at the end of your project or dissertation if you do not acknowledge the
actual quotations in the text. Neither is it acceptable to change some of the words or the
order of sentences if, by failing to acknowledge the source properly, you give the
impression that it is your own work.
 Duplication - submitting work for assessment that is the same as, or broadly similar to,
work submitted earlier for academic credit, without acknowledgement of the previous
submission.
 All general queries are to be addressed to [email protected]
Support for Differently Abled Persons:
JIMS endeavours to make all its courses accessible to students. The Internal Committee for
Differently Abled Persons has identified conditions that could hinder a student’s overall well-
being. These include physical and mobility related difficulties, visual impairment, hearing
impairment, mental health conditions and intellectual/learning difficulties e.g., dyslexia and
dyscalculia. Students with any known disability needing academic and other support are required
to register with the Internal Committee for Differently Abled Persons.

Students who need support may register any time during the semester up until a month before the
end semester exam begins. Those students who wish to continue receiving support from the
previous semester, must re-register within the first month of a semester. Last minute registrations
and support might not be possible as sufficient time is required to make the arrangements for
support.
The committee maintains strict confidentiality about the identity of the student and the nature of
their disability and the same is requested from faculty members and staff as well. The committee
takes a strong stance against in-class and out-of-class references made about a student’s
disability without their consent and disrespectful comments referring to a student’s disability.

All general queries are to be addressed to [email protected]

 Jagannath International Management School
Vasant Kunj, New Delhi-110070
(Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Recognized u/s 2(f) by UGC & Accredited with ‘A+’ Grade by NAAC
Participant of UNGC New York and ISO 9001:2015 Quality Certified

Programme: BCA Semester: III

Course: Computer Organization and Architecture Paper Code: BCA-203
Academic Session: August 2023 – Dec 2023
LESSON PLAN

Unit Topic and Sub Topics Learning Outcome References COs Syllabus
Covered Coverage
%
I Boolean Algebra and 2%
Logic: Basics Laws of
Boolean Algebra, To learn about basics of CO1
Boolean algebra along
I Logic Gates with laws and logic gates 2%
[T1] [T2] CO1
[R1][R2]
I 2%
Simplifications of Boolean
CO1
equations

I using K-maps SOP 4%

CO1
[T1] [T2]
I and POS [R1][R2] 2%
To learn about the CO1
designing of k-maps
I Don’t Care condition using POS and SOP 2%
CO1

I Arithmetic Circuits: 2%
Adder CO2
To learn about
implementation and [T1] [T2]
I Subtractor CO2 2%
designing of various [R1][R2]
I Parallel binary adder circuits used for CO2 2%
arithmetic operations

I Parallel binary Subtractor. To learn about arithmetic 2%

and combinational circuit [T1] [T2] CO2
designing [R1][R3]

II Combinational Circuits: 2%
Multiplexers CO2

II De-Multiplexers, 2%
CO2

II Decoders To learn about 2%

combinational and CO2
sequential circuit
II Encoders designing 2%
[T1] [T2] CO2
[R1][R3]
II Flip-flops: S-R, 2%
CO2

II D, J-K To learn about sequential CO2 2%

circuit designing

II T Flip Flop [T1] [T2] CO2 2%

[R1][R3]

II Clocked Flip-flop CO2 2%

II Race around condition To learn about sequential CO2 2%

circuit designing

II Master slave Flip-Flop CO2 2%

[T1] [T2]
II Realisation of one flip-flop CO2 4%
[R1][R3]
using other flip-flop

II Applications of flip flop: To learn about sequential CO2 2%

Latch, registers, circuit designing along
with counters

II Counters [T1][T2][R1] CO2 2%

III Data Transfer Operations: CO2 2%

Register Transfer
III Bus and Memory Transfer, To learn about various 2%
types of computer CO2
registers [T1][T2][R1]

III Registers and micro- CO3, 2%

operations. CO5

III Basic Computer CO3, 2%

Organizations and CO5
Design: Instruction Codes

III Computer Registers To understand the CO3, 2%

instruction cycle along CO5
III Instruction Cycle with implementation of [T1][T2][R1] CO3, 2%
stack CO5
III General Register CO3, 2%
Organization CO5

III Stack Organization CO5 2%

To understand about
III Instruction Formats addressing modes along [T1][T2][R1] CO5 4%
with pipelining

III Addressing Modes CO5 4%

IV Input-Output To learn about different CO4 2%

Organization: Peripheral peripheral devices and
Devices their interfaces [T1] [T2]
[R3]
IV Input-Output Interfaces CO4 2%

IV Asynchronous Data CO4 2%

Transfer

IV Modes of Transfer To understand the CO4 2%

concept interrupts and
IV Priority Interrupt direct memory access [T1] [T2] CO4 2%
[R3]

IV Direct Memory Access CO4 4%

(DMA)

IV priority interrupt. To understand the CO4 2%

concept interrupts and [T1] [T2]
IV Memory Organization: memory access [R3] CO4 2%
Main Memory
IV Auxiliary Memory CO4 2%
To study about different
types of memory
IV Associative Memory CO4 2%
[T1] [T2]
IV Cache Memory, Virtual [R3] CO4 4%
Memory.

TEXT BOOKS
[TB1]. Morris Mano, Computer System Architecture, 3rd Edition, Prentice-Hall of India Private
Limited, 1999.
[TB2] Moris Mano, “Digital Logic and Computer Design”, PHI Publications, 2002

REFERENCES:
[RB1]. R. P. Jain, “Modern Digital Electronics”, TMH, 3rd Edition, 2003.
[RB2]. WIliam Stallings, Computer Organization and Architecture, 4th Edition, Prentice Hall
of India Private Limited, 2001
[RB3]. Subrata Ghosal,” Computer Architecture and Organization” , Pearson 2011
[RB4]. Malvino, “Digital Computer Electronics: An Introduction to Microcomputers”, McGraw Hill

e-journals
1. International Journal of Computer Engineering in Research Trends

Journals
1. International Journal of IT, BVICAM, Vol 11, No 2, June 2019
Magazines

3. DATAQUEST: New It For New Normal

4. PCQUEST
Websites
3. https://www.webopedia.com
4. https://www.encyclopedia.com/science-and-technology/
 Jagannath International Management School
Vasant Kunj, New Delhi-110070
(Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Recognized u/s 2(f) by UGC & Accredited with ‘A+’ Grade by NAAC
Participant of UNGC New York and ISO 9001:2015 Quality Certified

Programme: BCA Semester: III

Course: Computer Organization and Architecture Paper Code: BCA-203
Academic Session: August 2023 – Dec 2023

ASSIGNMENT – 1

Q1. Explain the various Boolean algebra laws.

Q2. Design a 4-bit parallel binary adder.
Q3. Discuss the difference between multiplexer and de-multiplexer.
Q4. Explain the various logic gates and their truth table.

RUBRICS ASSIGNMENT – 1

1 Mark 2 Marks 3 Marks 4 Marks 5 Marks

Question 1 Define 4 types Define with examples
Define 1 type Define 2 types Define 3 types

Question 2 Definition
Definition + Key points
Definition + Detailed Discussion
Definition + KeyDefinition
points + Short
+ Detailed
Discussion
Discussion of key points

Question 3 Definition
Definition + Key points
Definition + Detailed Discussion
Definition + KeyDefinition
points + Short
+ Detailed
Discussion
Discussion of key points

Question 4 Define 4 types Define with examples

Define 1 type Define 2 types Define 3 types
 Jagannath International Management School
Vasant Kunj, New Delhi-110070
(Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Recognized u/s 2(f) by UGC & Accredited with ‘A+’ Grade by NAAC
Participant of UNGC New York and ISO 9001:2015 Quality Certified

Programme: BCA Semester: III

Course: Computer Organization and Architecture Paper Code: BCA-203
Academic Session: August 2023 – Dec 2023

ASSIGNMENT – 2
Q1. What do you understand by stack organization? Explain stack operations.
Q2. Explain DMA along with detailed transfer diagram.
Q3. Explain the various types of addressing modes.
Q4. Explain the general register organization.

RUBRICS ASSIGNMENT – 2

1 Mark 2 Marks 3 Marks 4 Marks 5 Marks

Question 1 Definition Definition Definition Definition and Definition and 2
and one and 2 2 operations operations with
operation operations with example example and diagram
Question 2 Definition
Definition + Key points
Definition + Detailed Discussion
Definition + KeyDefinition
points + Short
+ Detailed
Discussion
Discussion of key points

Question 3 Define 4 types Define with examples

Define 1 type Define 2 types Define 3 types

Question 4 Explain with detailed

Define 1 type Define 2 types Define 3 types Explain with example
example
 Jagannath International Management School
Vasant Kunj, New Delhi-110070
(Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Recognized u/s 2(f) by UGC & Accredited with ‘A+’ Grade by NAAC
Participant of UNGC New York and ISO 9001:2015 Quality Certified

Programme: BCA Semester: III

Course: Computer Organization and Architecture Paper Code: BCA-203
Academic Session: August 2023 – Dec 2023

QUESTION BANK
UNIT 1

1. Define the term Computer Architecture.

2. Define Multiprocessing.
3. What is meant by instruction?
4. What is Bus? Draw the single bus structure.
5. Define Pipeline processing.
6. Draw the basic functional units of a computer.
7. Briefly explain Primary storage and secondary storage.
8. What is register?
9. Define RAM.
10. Give short notes on system software.
11. Write down the operation of control unit?
12. Define Memory address register.
13. What is stack & queue?
14. Define Addressing modes.

UNIT 2
1. What is an instruction cycle and write the phases of Instruction cycle?
2. With a neat flowchart, explain how the control unit determines the instruction after decoding an
instruction.
3. Write the basic instruction formats for IO, Register and Memory Reference instructions.
4. With a neat schematic, explain the steps involved in fetch and decode phases using register
transfer instructions.
5. Elaborate the steps involved in execution of Memory-Reference instructions with its timing
signals.
6. Using the register transfer notations, explain the Memory-Reference instructions with examples.
7. Illustrate the basic requirements for Input and Output communication using a terminal unit such
as keyboard and printer.
8. Tabulate the Input-Output Instructions using register transfer notations?
 9. Write about Interrupt and its types?
10. Illustrate the phases of Interrupt Cycle with a neat flowchart.

UNIT 3

1. Why RTL is preferred for describing internal organization of digital computers.

2. Illustrate the register transfer mechanism for P: R2 R1 with necessary diagrams.
3. Design Bus system for Four-bit register using 4x1 Mux.
4. Implement Bus line for an 8-bit register using three state-buffers.
5. List out the Register transfer notations for Arithmetic Micro Operations.
6. Design and implement 4-bit Arithmetic unit which performs ADD, ADD with carry, SUB, Sub
with borrow, Increment and decrement operations.
7. Tabulate the logical and shift micro operations with its RTL notations.
8. Implement 4-bit Binary Adder-Subtractor and Binary Incrementor.
9. Explain the logical micro operations which manipulates individual bits of word in register with
examples.
10. Implement a 4-bit combinational circuit shifter using Multiplexer.

UNIT 4

1. Discuss the Memory Hierarchy in computer system with regard to Speed, Size and Cost?
2. Explain about main memory and its types.

3. Write about Auxiliary memory devices.

4. Explain the mechanism involved in Magnetic Disks and Magnetic Tapes.
5. Write a suitable practical scenario for Content Addressable memory?
6. Brief out the hardware organization of Associative memory with diagrams.
7. What is Locality of Reference and explain about Cache memory in detail.
8. Illustrate the mapping process involved in transformation of data from main to Cache memory.
9. What is virtual memory?
10. Explain the relation between address space and memory space in a virtual memory system along
with its memory table for mapping?
11. Explain Virtual address Mapping using Pages with necessary examples.
12. List out the importance of interfacing.