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Cell-Aware Test

Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · September 2014
DOI: 10.1109/TCAD.2014.2323216

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1396 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014

Cell-Aware Test
Friedrich Hapke, Member, IEEE, Wilfried Redemund, Member, IEEE, Andreas Glowatz, Member, IEEE, Janusz
Rajski, Fellow, IEEE, Michael Reese, Member, IEEE, Marek Hustava, Martin Keim, Member, IEEE,
Juergen Schloeffel, Member, IEEE, and Anja Fast

Abstract—This paper describes the new cell-aware test (CAT) the past few years, and we found that many defects that
approach, which enables a transistor-level and defect-based escape testing are in fact defects within the standard library
ATPG on full CMOS-based designs to significantly reduce the cells. Many of those cell-internal defects remain undetected
defect rate of manufactured ICs, including FinFET technologies.
We present results from a defect-oriented CAT fault model gener- when using traditional ATPG tools and the above men-
ation for 1,940 standard library cells, as well as the application of tioned well-known fault models. Also, the pattern fault model,
CAT to several industrial designs. We present high volume pro- which was introduced about 10 years ago, addresses the
duction test results from a 32 nm notebook processor and from problem only partially. Successful attempts of fault mod-
a 350 nm automotive design, including the achieved defect rate eling approaches and analog simulations based on SPICE
reduction in defective-parts-per-million. We also present CAT
diagnosis and physical failure analysis results from one failing netlists containing just transistors and no parasitic objects,
part and give an outlook for using the functionality for quickly but already considering the physical layout [13], have been
ramping up the yield in advanced technology nodes. done using inductive fault or contamination analysis, also
Index Terms—Automatic test pattern generation, cell-aware for standard library cells [14], [15]. Basic approaches to
test, defect-based test, defective parts, design for testability, fail- model physical defects on transistor level by means of SPICE
ure analysis, FinFET test, logic testing, test data compression, simulations without considering parasitic objects [12], [16],
transistor-level test. or on logic level [17], have shown how low-level defect
information can be used to achieve better and high efficient
I. I NTRODUCTION fault models. Transistor-level ATPG solutions have been per-
formed [18], [19], but these quickly turn inept when applied to
HYSICAL defects like shorts, opens, and transistor
P defects may occur during the fabrication process of semi-
conductor devices. To detect such defects, fault models have
multimillion transistor designs. Our research over the past five
years resulted in the new cell-aware test (CAT) fault model.
This fault model is based on a post-layout transistor-level
been proposed and used for the generation of test patterns.
netlist including parasitic objects, resulting into a defect-based
The most well-known fault models include stuck-at (SA) [1],
ATPG approach, which can be applied to large, state-of-the-art
bridge [2]–[4], transition (TR), [5], [6], N-detect [7], gate-
designs. An introduction to the CAT methodology was pub-
exhaustive (GE) [8], and embedded-multi-detect (EMD) [9],
lished in [20]. We compared CAT and GE patterns in [21].
as well as timing-aware [10], and layout-aware [11] fault
CAT has proven to be effective in detecting cell-internal
models on interconnect lines. Furthermore, the fault models
defects, as demonstrated through high-volume production
stuck-short and stuck-open have been addressed by transis-
test results presented in [22]–[27]. In these cases, state-
tor switch level simulation [12]. Notwithstanding the great
of-the-art fault models were shown to be insufficient; only
successes of those fault models, customers report that they
CAT achieved the demanded low defective-parts-per-million
increasingly receive too many defective parts from their sup-
(DPPM) rates.
pliers. Hence, they demand higher quality tests during the
In this paper, we will give a complete overview of the CAT
production process. We have investigated this problem for
method in Section III. In Section IV, we present CAT view
Manuscript received October 24, 2013; revised February 12, 2014 and April generation results from a library with 1,940 cells. In Section V,
16, 2014; accepted April 23, 2014. Date of current version August 18, 2014. we outline the CAT application to various industrial designs
This paper was recommended by Associate Editor X. Wen. with detailed information about the pattern count, the overall
F. Hapke, W. Redemund, A. Glowatz, J. Schloeffel, and A.
Fast are with Mentor Graphics Development (Deutschland) GmbH, coverage gain, as well as which cell types from the standard
Hamburg 21079, Germany (e-mail: [email protected]; cell library contribute most to the defect rate reduction. In
[email protected]; [email protected]; Section VI, we present high-volume production test results
[email protected]; [email protected]).
J. Rajski and M. Keim are with Mentor Graphics Corporation, from a 32 nm notebook processor after testing 800,000 parts.
Wilsonville, OR 97070, USA (e-mail: [email protected]; Production test results from 1,000,000 parts of a 350 nm auto-
[email protected]). motive design are shown in Section VII. In Section VIII, we
M. Reese is with AMD Inc., Austin, TX 78735, USA (e-mail:
[email protected]). give an overview of the diagnosis flow based on the CAT
M. Hustava is with ON Semiconductor, 619 00 Brno, Czech Republic (e- method, including physical failure analysis (PFA) results from
mail: [email protected]). one selected 32 nm part. The advantages of the CAT method-
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. ology over traditional fault models for FinFET technologies
Digital Object Identifier 10.1109/TCAD.2014.2323216 are described in Section IX.
0278-0070  c 2014. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/
redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information
HAPKE et al.: CELL-AWARE TEST 1397

TABLE I
M ULTIPLEXER T EST PATTERN AT C ELL I NPUTS

Fig. 2. Well-known design flow.

Fig. 1. Cell-aware test library view generation.

II. M OTIVATION
IC manufacturers are required to deliver well-tested ICs to
their customers with a certain maximum defect rate. Customers
are performing incoming application-related acceptance tests, Fig. 3. Defect extraction from cell layout.
which often uncover a higher defect rate than permissible. A
detailed analysis published in [28] has shown that the majority
of test escapes have their root-cause in insufficiently detect- The flow as shown in Fig. 1 is a combination of traditional
ing cell-internal defects. For this analysis, over one million functions/tools and new functions and algorithms that were
parts were tested with traditional SA patterns, experimentally developed for this CAT methodology. The flow starts with
followed by EMD patterns. It was determined that numerous layout extraction, followed by an analog fault simulation, and
parts that were failing EMD patterns but not SA patterns were fault model synthesis to create the CAT library models.
failing due to one missing cell input condition at a simple mul- The second major part is the well-known design flow (see
tiplexer with two data inputs. The missing cell input condition Fig. 2) where we use our CAT ATPG instead of a traditional
was D0 = 0, D1 = 0, and S = 0, as shown in Table I. Knowing ATPG.
that traditional ATPG tools are using gate-level primitives, it Our CAT ATPG is a defect-based ATPG that uses the
became obvious that the ATPG was not required to generate technology-dependent and transistor-level-based CAT view to
the 000 condition, which was necessary to detect the identi- generate high-quality test patterns to significantly reduce the
fied silicon defect. Further, this pattern never occurred after defect level of delivered ICs. The CAT ATPG is able to gener-
random fill of the unspecified bits. ate patterns for very large multimillion gate designs. Current
Table I summarizes the required multiplexer cell input pat- results achieved by this new CAT methodology show a signif-
tern to detect all SA port faults, the actual applied pattern icant increase of the defect coverage and as such a significant
during the SA production test, as well as the experimental reduction of the defect rate measured in DPPM as presented
test pattern with the added test highlighted in the shaded table in Sections VI and VII.
cells. After performing an analog fault simulation for that mul-
tiplexer, we found that one bridging fault required exactly the
A. Layout Extraction
000 condition, and that no other cell input condition would test
that particular bridge defect. Similar situations also exist for The first part of the flow in Fig. 1 is the layout extraction
open defects that require sequential cell input conditions; this step, which reads the layout data (file F1) of the individual
was addressed in [28] as well. These findings motivated us to library cell and creates a SPICE transistor netlist in detailed
research and subsequently develop a new fault model which standard parasitic format (DSPF) including parasitic elements
is based on actual cell layouts that can be created fully auto- like resistors and capacitors which is stored in file F2. As
matically, and that forces the ATPG tool to deterministically an example, let’s consider a 3-to-1 multiplexer cell from a
generate a set of cell input combinations which detect all cell- 65 nm library. The corresponding layout with some defects
internal defects. This methodology is named cell-aware-test. highlighted is shown in Fig. 3.

III. C ELL -AWARE T EST M ETHODOLOGY B. Analog Fault Simulation

The CAT methodology consists of two major parts. The The second part of the CAT view generation flow as
first part (see Fig. 1) is the technology-dependent CAT view shown in Fig. 1 is analog fault simulation, which starts with
generation flow, which is a one-time task that is performed the extraction of considered defects from the DSPF SPICE
once for each technology library. netlist. The resulting considered defects are stored in the
1398 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014

Fig. 4. Extracted transistor netlist and inserted defects.

cell-dependent defects file (file F3 in Fig. 1). The defects con- Fig. 5. Analog simulation environment.
sidered are single hard defects, not parametric variations from
IC processing, and they occur at sites where there are SPICE The next step is to perform an exhaustive analog simulation
netlist components, both intentional and parasitic. The CAT for each of the extracted defects to determine the complete set
methodology differentiates the following six defect types. of cell input combinations that detect the defect. The resulting
1) Open: Any cell-internal open defect, such as an open in defect matrix for the particular library cell, which summarizes
poly, metal, diffusion, or vias. In the extracted SPICE the detection results for each defect, is contained in file F4 as
netlist, these defects are matched to existing resistor ele- shown in Fig. 1.
ments by increasing their resistance values. Different The analog simulator environment that is used during the
open resistor values are considered as necessary. analog fault simulation step for a cell with three data inputs,
2) Bridge: Any cell-internal bridge defect such as bridges one cell output, and the two power pins VDD, and VSS is
between adjacent objects in the same layer or differ- shown in Fig. 5. Always one single defect is inserted at a
ent layers. In the extracted SPICE netlist, these defects time.
are matched to existing capacitor elements by inserting The performed simulations are analog transient analysis
resistors in parallel with them. Different bridge resistor simulations, which determine the voltage at the cell output
values are considered as necessary. at a calculated strobe time. Both a static (one time frame) and
3) Tleak: Any cell-internal transistor defect that will switch a delay (two time frame) analog simulation is performed.
a transistor partially on with a certain resistive value. A defect is considered detected if, for example, the cell’s
Different leakage resistor values are considered as nec- output voltage deviates from the defect-free voltage by more
essary. than 60% of the supply voltage for at least one input combina-
4) Tdrive: Any cell-internal defect that will switch a tran- tion. The deviation threshold, however, can be specified by the
sistor partially off with a certain resistive value. Different user. All analog simulations, including the creation of the stim-
drive strength resistor values are considered as neces- uli, are fully automated by the CAT library view generation
sary. tool.
5) PortBridge: A bridge between a port (e.g., D1) and VSS, For the static analysis, exhaustive one time frame stimuli
VDD, or any other port of the cell. Different bridge are analyzed. For the delay analysis, robust two time frame
resistor values are considered as necessary. stimuli are analyzed by default, but also exhaustive two time
6) PortOpen: A disconnected port (e.g., D1), to analyze the frame stimuli can be analyzed on user request.
effect of cell-external disconnects to cell ports. Different
open resistor values are considered as necessary. C. Cell-Aware Fault Model Synthesis
SA and TR faults at the cell ports are contained in the CAT The goal of this step is to identify and store the cell input
defect lists for each cell as well, and as such the defects that conditions that are useful in detecting the defects inside each
CAT considers are a superset of SA and TR fault sites, since cell. This third part of the CAT view generation flow as shown
both DC and transient analog simulations are performed. in Fig. 1 is called the CAT synthesis, which optimizes the
Also note that CAT covers all bridges between cell ports, newly created exhaustive defect matrix in order to generate
even when they occur external to the cell. But CAT does not the corresponding CAT library view that is stored in the CAT
consider cell-external bridges to other cell instances in the view file (file F5 in Fig. 1). For each detected cell-internal
design. This means, layout-aware bridges on interconnect lines defect, the CAT view file contains one or more alternative
should still be considered for high quality test as it is done in test conditions for detecting the corresponding defect. This
the experiment as presented in Section VII. ensures that the subsequent CAT ATPG still has the freedom
A schematic representation of how and where such defects to choose between all alternative test conditions for detecting a
are inserted into the DSPF SPICE netlist is shown partially in certain cell-internal defect, while maintaining a very compact
Fig. 4. test pattern set for a complete design.
HAPKE et al.: CELL-AWARE TEST 1399

Fig. 6. Normal ATPG process.

Fig. 8. CAT defect coverage graph.

assign an additional cell input, which is in this case D2, in

order to detect the bridging defect B1. As described earlier, a
traditional SA ATPG would only be forced to assign one data
input. In other words, in contrast to previous approaches, the
CAT ATPG deterministically applies the conditions to detect
all detectable intracell defects. Traditional ATPGs, however,
may detect them only by chance.
Fig. 7. CAT ATPG for an intracell bridge defect.
To guarantee a very compact set of test patterns, the CAT
ATPG algorithm makes use of all possible conditions given
D. Transistor-Level Defect-Based ATPG by the CAT view for detecting a certain defect.
As shown in Fig. 2, the CAT ATPG is part of the well-
known design flow which uses the gate-level netlist from the IV. L IBRARY V IEW G ENERATION R ESULTS
logic synthesis without any transistor netlist and without any For creating the CAT views for a complete library (including
layout data, but adds the CAT views that have been cre- both, combinational and sequential cells), the CAT flow as
ated up-front by using the transistor level netlist including all described in Section III is executed for each standard library
parasitic elements, extracted from the cells layout, as shown cell. In this paper, we present results from 1,940 cells from
in Fig. 1. a 65 nm technology. Other technologies do show very similar
The major difference between the CAT ATPG and tradi- results. Two important graphs are the defect coverage graph
tional SA and TR pattern generation is the modeling of the and the pattern graph which are explained in the following
fault. We can demonstrate those differences using an example sub-sections.
of a 3-to-1 multiplexer that is instantiated somewhere in the
design.
Fig. 6 shows how the SA ATPG will generate a test for A. CAT Defect Coverage Graph
detecting a port fault; in this case, a SA 0 fault at the cell The CAT defect coverage graph presents coverage results
input D0. with respect to each library cell in isolation without instan-
In a traditional SA ATPG engine, the fault position (initial tiating the cell in a design. The graph in Fig. 8 shows the
fault injection) and the condition for the fault excitation is deficiency of traditional SA and TR patterns for detecting
predefined for every ATPG primitive. In this example the SA detectable layout-based cell-internal defects.
ATPG would justify D0 = 1, S0 = 0, and S1 = 0. The other The horizontal axis represents the library cells numbered
inputs (D1 and D2) are not required. The generation process from 1 to 1,940. The vertical axis represents three defect
of the CAT ATPG for the same multiplexer is shown in Fig. 7. coverage rates in percent as follows: the blue line is the
In this case, an intracell bridge is assumed between two nets defect coverage rate for detectable bridges, opens, and transis-
A and B as indicated in the layout. tor defects that is achieved with state-of-the-art SA patterns.
The initial fault injection of a CAT defect is always at the The red line is the defect coverage rate for detectable bridges,
cell output port. The condition for the fault excitation and its opens, and transistor defects that is achieved with state-of-the-
propagation to the cell outputs is fully disconnected from any art TR patterns. The green line is the defect coverage rate of
predefined ATPG primitive. It strictly applies the necessary CAT static and CAT delay patterns (which is always, by def-
conditions at the input ports of the library cell as defined by inition, at 100%, because only detectable cell-internal defects
the corresponding CAT model. are considered). CAT static patterns are using one-cycle test
Considering the bridge B1 in the above example, the nec- conditions, and CAT delay patterns are using two-cycle condi-
essary assignments at the cell inputs are D0 = 1, D2 = 0, tions at the cell inputs. CAT static tests are typically performed
S0 = 0, and S1 = 0. That means the CAT ATPG is forced to at slow-speed, CAT delay tests typically as at-speed tests. The
1400 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014

Fig. 10. Industrial design evaluation.

Fig. 9. CAT pattern graph on standard cell level. TABLE II

D ESIGN DATA /R ESULTS OF I NDUSTRIAL D ESIGNS

graph shows that defect coverage of SA patterns is less than

100% for about 50% of the cells, and some cells reach defect
coverage of only 46%. The situation is worse for TR patterns,
where about 80% of the cells do not reach 100% defect cov-
erage, and about 200 cells have defect coverage of less than
50%, while some cells reach just 20%.

B. CAT Pattern Graph

The CAT pattern graph in Fig. 9 presents results with respect
to the number of test patterns generated on each library cell
in isolation without instantiating the cell in a design.
Again, the horizontal axis represents the individual library cell-internal defects. This results in the defect coverage DCSA
cells. The vertical axis represents the number of patterns for and DCTR . The third step in the evaluation flow in Fig. 10
each cell. The cells are sorted from left to right in descending is the generation of CAT patterns to reach the maximum
order of their traditional pattern count. The blue line is the sum achievable defect coverage.
of essential SA and TR patterns for each cell, and the green DCCA1 is the defect coverage achieved with CAT static pat-
line is the sum of essential CAT static and CAT delay patterns. tern, and DCCA2 is the defect coverage achieved with CAT
Complex cells like multiplexers with four (MUX4) and three delay pattern. For all three ATPG runs, the same random fill
data inputs (MUX3), scan flip-flops (SFF), and AND - OR (AO) strategy was used, and a single detection was requested. In
type cells with up to six inputs, all cluster on the left hand addition to the comparison of the defect coverage, we also
side of the graph. compared the number of CAT test patterns with the number
The peak in the graph at the x-axis position around 1200 of SA and TR patterns.
is from full-adder (FA) type cells with three inputs, and the The selected industrial designs are implemented in a 65,
peak at the x-axis position around 1500 is from XOR gates 55, 32, and 28 nm technology. The design data is shown in
with three inputs. Simple logic gates (AND, NAND, OR, NOR) Table II.
with 2–4 inputs are shown as corresponding GATE cell types. As an example, design #10 has 5.6 million gates, 458 k flip
The graph in Fig. 9 shows that traditional SA and TR pat- flops, and 1020 internal scan chains, resulting in 22.4 million
terns are insufficient to detect all dectable cell-internal bridges, SA faults and 92.6 million CA defects. All but two of the
opens, and transistor defects. Nearly all cells require more pat- designs use on-chip test compression; the two designs without
terns to detect all cell-internal defects and the CAT ATPG is test compression are #2 and #6.
forced to generate those essential patterns. Looking at the faults and defects columns in Table II, it
can be seen that the number of CAT defects is in all cases
significantly higher than the number of SA faults. On average,
V. E VALUATION W ITH I NDUSTRIAL D ESIGNS
there are about four times more CAT defects than there are
To evaluate the effectiveness and the quality of CAT pat- SA faults.
terns, we executed the evaluation flow as shown in Fig. 10
on 10 industrial multimillion gate designs. The design data is A. CAT Static Defect Coverage Gain
given in Table II.
Fig. 11 shows the achieved defect coverage gain in percent
The evaluation flow starts with the generation of state-of-
[%] that is achieved with CAT static patterns over the defect
the-art SA and TR patterns, which give test coverage TCSA
coverage that is achieved with SA patterns. The static defect
and TCTR . The second step in the flow is the fault grading
coverage gain is defined as
of SA and TR patterns with respect to the CAT fault model
considering all traditional SA and TR cell port faults and the DCgain = DCCA1 − DCSA .
HAPKE et al.: CELL-AWARE TEST 1401

TABLE III
N UMBER OF T EST PATTERNS R ELATED TO D EFECT C OVERAGE G AIN

Fig. 11. CAT static defect coverage gain over SA.

this experiment we did in total four different CAT ATPG runs.
For the first run, we limited the number of CAT patterns to
be exactly the same number as there are SA and TR patterns.
For the second and third run, we limited the amount of CAT
patterns to 25% more and 50% more, respectively, than there
are SA and TR patterns. For the fourth run, we removed any
pattern count limitation and generated as many patterns as
needed for the detection of all cell-internal defects as well as
for the detection of the traditional cell port faults.
As can be seen in Table III, in the column titled “+ 0%
pattern,” a significant defect coverage gain of about 2.5% on
average, can already be achieved without any pattern or test-
time increase when using CAT patterns instead of using SA
and TR patterns. The average defect coverage gain increases
Fig. 12. CAT delay defect coverage gain over TR. up to 5% (1% static and 4% delay) when more CAT patterns
are applied. For the maximum defect coverage, the average
Fig. 11 illustrates that the average defect coverage gain CAT static pattern increase is about 49% over SA pattern.
achieved by CAT static patterns compared to SA patterns is The comparison of TR and CAT delay patterns resulted into
almost 1%. As explained before, the increase in defect cov- an average pattern increase of about 70%.
erage is because the CAT ATPG targets cell-internal defects Overall we can state that CA patterns are significantly better
explicitly, but traditional ATPG misses these faults both by than SA and TR pattern. Even without any pattern or test time
failing to target them and by failing to cover them by chance. increase a significant defect coverage gain is achieved by CAT
patterns.
B. CAT Delay Defect Coverage Gain
The defect coverage gain is even higher for the CAT delay D. CAT Static Defect Coverage Gain Per Cell Type
patterns, where an average defect coverage gain of over 4% is To further investigate which cell types contribute most to the
achieved compared to TR patterns, as shown in Fig. 12. The CAT defect coverage gain, we created coverage gain data not
delay defect coverage gain is defined as just for the complete design, but separately for each standard
cell type as used in the evaluated designs. The results are
DCgain = DCCA2 − DCTR . shown in Figs. 13–15.
The high-volume production test results (shown in Fig. 21) Fig. 13 shows the defect coverage gain achieved with CAT
confirm these evaluation results; i.e., there are at least four static patterns on average over the selected designs, by cell type.
times more CAT delay detections than there are CAT static The blue line shows the absolute CAT coverage gain in percent
detections. [%] in relation to the total number of chip defects for each cell
type, and the red line shows the relative coverage gain in relation
to the number of defects of the corresponding cell type.
C. Comparison of SA, TR, and CAT Patterns The graph shows that the SFF cell type contributes most
In Table III, we show the number of additional CAT patterns to the absolute CAT static coverage gain. This means the
and their corresponding defect coverage gain in relation to the SFF cells contribute, on average, with about 0.38% additional
control set of SA and TR patterns. So, Table III shows the detected defects in total per design, and with about 1.2% rel-
defect coverage gain that is achieved for 0% pattern increase, ative coverage gain in relation to the number of defects of
for 25%, 50%, and the maximum additional pattern that are the SFF cell type. The second most contributing cell type is a
needed to get the highest defect coverage gain. This means for MUX4, followed by the AO, and OR-AND (OA) cell types.
1402 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014

Fig. 15. CAT-only detected defects per cell type.

Fig. 13. CAT static defect coverage gain per cell type.

Fig. 14. CAT delay defect coverage gain per cell type.

The simple logic gates (AND, NAND, OR, NOR gates from 2 Fig. 16. Layout of the AO cells.
to 4 inputs) are summarized as GATES cell type. The rela-
tive coverage gain of the MUX4 cell type of about 1.6% is
higher than the 1.2% from the SFF cell type, but the overall Fig. 15 shows that the OA cell type contributes most to the
impact of MUX4 is smaller, because there are fewer instances additional detected defects, with 1.08%. The MUX4 cell type
of MUX4 cells than SFF cells. Because of that, the SFF cells contributes 1.07% defects, the AO cell type also adds 1.07%
contribute most to the coverage gain for all 10 designs. The defects, and the simple logic GATES cell type contributes with
half-adder (HA), FA, and XOR3 cells contribute least to the 0.90% defects.
overall coverage gain because there are very few instances of
those cells in the selected designs. G. Cell-Aware Detections in AO Cells

E. CAT Delay Defect Coverage Gain Per Cell Type To further investigate the large CAT-only detected defects
within AO and OA cell types, we selected an AO cell with
An overview of the defect coverage gain by cell type for four inputs. The traditional (sum of SA + TR) test pattern
CAT delay patterns is given in Fig. 14. count for this cell is 10, but CAT requires 23 patterns. Fig. 16
The blue line shows the absolute CAT coverage gain in per- shows the layout of this AO cell and one of the defects (named
cent [%] for each cell type, and the red line shows the relative D30) that is not guaranteed to be detected with traditional test
coverage gain. The graph shows that the OA cell type achieves patterns.
the highest absolute coverage gain of 1%. The second most Fig. 16 shows the bridge defect D30 (irregular shaped red
contributing cell type, with also nearly 1% absolute coverage objects) on metal1 between the cell input “B” and a cell-
gain, is the AO cell type, the simple logic (GATES) are now internal net “3.” This bridge defect can occur in two different
third. The MUX4 cell type is now on the fourth position with physical locations.
about 0.8% absolute gain, although its relative gain is the high- Fig. 17 shows the same bridge defect D30 between the cell
est with about 10%. Again, the FA, HA, and XOR3 cell types input “B” and the cell-internal net “3,” mapped back to the
contribute least to the overall coverage gain because there are transistor schematic. There is only one test pattern in the total
very few instances of those cell types in the selected designs. of the 16 possible input patterns that guarantees the detection
of this bridge defect. This input pattern is A = 1, B = 0, C
F. Total CAT-Only Detected Defects Per Cell Type = 0, and D = 0. A traditional SA ATPG is not required to
The total percentage of CAT-only detected defects per cell generate this input combination. The CAT ATPG however, is
type from both the CAT static and CAT delay patterns is shown forced deterministically to generate this pattern that will detect
in Fig. 15. the bridge defect D30.
HAPKE et al.: CELL-AWARE TEST 1403

Fig. 19. AMD 32 nm notebook processor.

Fig. 17. Transistor schematic of the AO cell.

Fig. 20. Production test flow 32 nm notebook processor.

so the required states are assigned to the D and the TI inputs

of SFF cells.
In many cases, there are also more complex SFF cells that
Fig. 18. Undetected defects in SFF cells.
do not just have a simple multiplexer for D and TI, but also
include much more logic like AO functions, hold functions,
H. Cell-Aware Detections in SFF Cells set and reset functions, etc.
The CAT ATPG will always be forced to make the necessary
As shown previously in Fig. 13, SFF cells also contribute assignments at all required flip-flop inputs. In addition, there
significantly to CAT-only static detected defects. are typically many more SFF instances than instances from
Fig. 18 shows a few basic SFFs connected to each other to other cell types, which also is a root-cause for the signifi-
form a scan-chain. Their data input (D) and their output (Q) cant contribution of the SFF cells to CAT-only static detected
are connected to a cloud of combinational logic. In typical defects.
configurations like this, there are usually some cell-internal
defects within the SFFs that are not detected by the chain
test and SA/TR tests. This is because the chain test does not VI. P RODUCTION T EST OF A 32 NM D ESIGN
consider states at the D inputs, and traditional ATPG tools will To investigate the effectiveness of CAT patterns in relation
assign the needed states at the D inputs of the SFF cells, but to SA and TR patterns, as used in the normal production test,
the tool is not required to also assign the needed state at the we partnered with Advanced Micro Devices (AMD) to exe-
test input (TI) of the SFF. cute an experiment with a four-core AMD 32 nm notebook
To further investigate the CAT-only detected defects in the processor, see Fig. 19.
SFF cells types, we analyzed the cell input patterns that are In this experiment, CAT patterns were added to the test
applied during the SA and TR tests. We noticed that in many program and the test flow was changed to log unique fails of
cases all possible input combinations for D and TI are present the CAT patterns as shown in Fig. 20.
in the huge pattern set. But often when the required input com- The production test consists of a TR-N-det5, with an
bination was applied, the clock was gated, preventing capture. N-detection limit of five, and a static SA top-off test. The
Due to low-power requirements, there are often multiple stages TR and CAT delay patterns were applied at-speed and the SA
of clock gating for nearly all flip-flops. In these cases where static and CAT static patterns were applied by a slow-speed
the enable condition is complex, the capture happens in only test. All experimental CAT patterns were in data-collection
very few patterns. mode, otherwise known as “continue on fail”. The experimen-
The CAT ATPG tool is forced to enable the clock gates tal tests were applied to all die where all four cores passed
when generating patterns to test all cell-internal defects, and the existing ATE production test suite of wafer sort patterns.
1404 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014

Fig. 21. PPM reduction AMD 32 nm notebook processor.

After testing 800,000 ICs, the fail and PPM reduction results
were summarized, as shown in Fig. 21. Fig. 22. ON semiconductor 350 nm automotive design.
This data shows that the CAT static patterns detect a total of
231 defects that state-of-the-art traditional SA patterns do not
detect. The CAT delay patterns detect a total of 609 defects
that state-of-the-art traditional TR patterns do not detect. These
fail counts can be easily transformed into PPM rates, i.e., the
CAT static patterns are reducing the defect rate by 292 PPM
and the CAT delay patterns by 771 PPM. The Venn diagram
also shows the overlap of 141 detected defects between the two
tests. In total, the CAT patterns are reducing the PPM rates
for this 32 nm design by 885 PPM. Later performed paramet-
ric tests and final tests including functional tests, carried out Fig. 23. Production test flow 350 nm automotive design.
at different voltage and temperature levels, confirmed 66% of
the CAT-only fails. Additional 16% have been confirmed by
expensive system level tests (SLT). That means a total of 82% responsible for processing of the ADC bit stream generated by
of the CAT-only failing parts have been confirmed to be defec- the analog front-end. The design also includes complex DFT
tive or too slow. Just 18% of those parts made it through the logic to achieve the top-class analog and digital testability.
SLT, and are to be further analyzed. This data confirms that To investigate the effectiveness of the CAT patterns in rela-
CATs performed at wafer test detect real defects that otherwise tion to the normal production test patterns, we added the
are only detected with very expensive SLTs. experimental CAT patterns to the test program and changed
The test costs related to the analyzed fault models have a the test flow to log unique fails of the CAT patterns as shown
direct relation to the number of patterns generated for the fault in Fig. 23.
models. The additional test costs for the CAT patterns for this The production test consists of an IddQ test, followed by
design are about 43% of the existing structural production tests a SA static and layout-aware interconnect bridge test, and a
costs. single detect TR test. The experimental patterns applied after
These production test results were collected during 2012, the normal production tests consist of a CAT static as well as
and since then AMD has tested other designs in 32 and 28 nm a CAT delay test. As before, the TR and CAT delay tests were
technology in production with CAT patterns. The defect rate applied at-speed, all other tests at slow-speed. All experimental
reduction is consistently high as shown in Fig. 21, at about patterns were in data-collection mode. The production patterns
900 PPM for the 32 nm products and even higher for the 28 have been executed in “stop on fail” mode. This means that
nm products at about 1500 PPM. any fail detected by the CAT patterns completely passed the
In addition, various CAT-only failing parts have been ana- normal production tests.
lyzed by PFA to prove that the CAT-only fails are real physical The additional test costs for the CAT test patterns were 59%
defects. For further details see Section VIII. in total, which was mainly consumed by the 1135 CAT delay
patterns, while the normal production test pattern had in total
VII. P RODUCTION T EST OF A 350 NM D ESIGN 2019 patterns.
For evaluating the effectiveness of CAT patterns on a 350 After enhancing the production test program as shown
nm technology, we worked with ON semiconductor to execute in Fig. 23, we applied the normal production patterns and
an experiment for an automotive design. experimental CAT patterns during wafer sort for the 350 nm
The design shown in Fig. 22 integrates high-performance, automotive designs. Fig. 24 summarizes the reject count and
power-efficient analog, and digital parts. The analog circuits their projection to the measured DPPM rate after testing
implement the LIN physical layer and analog front-end inter- 1,000,000 ICs.
face to the external sensor. The digital circuits implement the This data shows that the CAT patterns detected a total of
LIN data link layer, LIN application layer, and DSP logic 114 rejected parts that traditional SA, bridge, and TR patterns
HAPKE et al.: CELL-AWARE TEST 1405

Fig. 24. Measured PPM reduction 350 nm design.

do not detect, resulting in a measured defect rate reduction of Fig. 25. Cell-aware diagnosis experiment steps.
114 PPM.
The CAT static patterns detected a total of nine parts. These
reject counts can be directly correlated with measured PPM
rates i.e., the CAT static patterns resulted in a measured defect
rate reduction of 9 PPM.
The CAT delay patterns detect a total of 105 parts result-
ing in a measured defect rate reduction of 105 PPM. The
Venn diagram also shows the overlap between the two tests
which was zero in this experiment. The reason for this is
mainly related to the fact that defects that can be detected
by CAT static tests are not targeted again by CAT delay
patterns.
The validation of the test results (retesting of the rejected
parts using the standard and CAT flow) confirmed that all 114
Fig. 26. SPICE schematic with layout properties.
rejects are permanent fails. The nine parts that failed the CAT
static patterns were confirmed to be hard defects failing under
all test conditions. The other 105 parts that failed the CAT
delay patterns proved to be parametric outliers.
For ON Semiconductor CAT provides a method to screen
delay defects in the digital circuits without relying on over-
constraining the design during synthesis and over-screening on
ATE. This will allow further optimization of power dissipation
and the digital area of the design. Based on this result, ON
Semiconductor concluded that the CAT method detects various Fig. 27. SPICE netlist with physical properties.
otherwise undetected defects (mainly parametrical defects) and
does improve overall test quality.
an exhaustive set of stimuli. For diagnosis, we only need to
VIII. C ELL -AWARE D IAGNOSIS simulate the subset of stimuli that was actually used in the
Based on the CAT method, we have also performed cell- test pattern set of the cell instance that was called out to be
aware (CA) diagnosis. One important component for achieving suspect.
CA diagnosis is a SPICE netlist that includes physical prop- Step 3 performs CA defect scoring. It calculates the prob-
erties like X, Y coordinates and layer information for each ability that a specific defect is the root cause of the faulty
cell-internal defect. The complete CA diagnosis experimental behavior.
flow is shown in Fig. 25. Step 4 creates a layout marker file such that a GDS viewer
Step 1 extracts a SPICE transistor-level netlist in DSPF, can be used to highlight the defects.
which includes all transistors, all parasitic elements (resis-
tors and capacitors), and all layout properties such as layer
information and X, Y coordinates. A. Step1: Layout Extraction With Physical Properties
Step 2 performs an analog diagnosis fault simulation for To enable a CA diagnosis, the layout in GDS format of a
all extracted defects. The stimuli used for this analog diagno- standard cell is used to extract a DSPF SPICE netlist, which
sis fault simulation are just the failing and passing cell input now includes process layer information and the X, Y coordi-
conditions that have been retrieved from the traditional gate- nates of each extracted resistor and transistor. A partial SPICE
level-based electrical diagnosis run. This step deviates from schematic is shown in Fig. 26.
the analog simulations as shown in Fig. 1; where we simulate A fraction of the related SPICE netlist is shown in Fig. 27.
1406 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014

Fig. 27 shows that the layout extraction tools produce a

DSPF netlist in which all resistors and transistors have phys-
ical properties. However, the layout extraction tools do not
provide physical properties for capacitors, so CA diagnosis
calculates those on its own based on the physical properties
of the resistors and transistors.

B. Step 2: Analog Diagnosis Fault Simulation

Fig. 28. Logic diagram at suspect defect location.
To calculate the defect behaviors of all extracted potential
CA defects, we performed an analog diagnosis fault simulation TABLE IV
using the extracted DSPF SPICE netlist. For this, we fault- C ELL -AWARE D EFECT S CORING TABLE
simulated all extracted defects for all failing and passing cell
input patterns obtained from the usual electrical diagnosis step.
The considered CA defects are the same as used during
the CAT library view generation as explained previously in
Section III-B. These defects include opens, bridges, transistor
leakage (tleak), transistor drive-strength (tdrive), port bridges,
and port opens.
The output of this analog fault simulation step is a defect
matrix containing all defect behaviors for each potential defect.
Like a traditional fault dictionary the defect matrix has as
many rows as there are stimuli that have been simulated (these
are the failing and passing cell input stimuli), and as many
columns as there are defects. This matrix contains the infor-
mation if a certain defect can be detected, and if so, which
stimuli will detect it. E. Cell-Aware Diagnosis Result
The CA diagnosis method as described in the previous four
C. Step 3: Cell-Aware Defect Scoring sub-sections has been applied to various failing parts from the
The third step of the CA diagnosis is to compute a defect AMD 32 nm processor.
scoring. The input for this step is the defect matrix as created The traditional layout-aware diagnosis results for one of
by the analog diagnosis fault simulation. In addition, we used those failing parts had just two potential failing instances.
the physical properties of each defect. Consider the follow- One was an XNOR gate with two inputs and the other was
ing simplified formula, which compares the simulated defect a NAND gate with four inputs. Both candidates are connected
behavior with the actual defect behavior: to each other and lay on an observation path to a SFF, see
Fig. 28.
S = AF/RF × 100%. The results from the CA defect scoring table for the NAND4
gate are shown in Table IV.
S is the score in percentages, AF is the match of the actual Column 1 in Table IV is a defect identification number.
failing pattern with the required failing pattern, and RF is the Score is a measure of the defect probability as calculated by
number of required failing patterns which detect the defect the equation detailed in Section VIII-C. The defect-type col-
to 100%. The actual formula that we used also considers the umn lists the CA type of defect. The Net1 and Net2 columns
physical properties, e.g., for bridges, the distance of the objects are the cell-internal net names in the transistor schematic. The
and the length of the bridging area. The result of this scoring Layer column contains the process layer (e.g., M01 = metal1,
process is a list containing all CA defects sorted from highest DIFF = diffusion, VIA = contact from metal1 to metal2). The
score to lowest, as shown in Table IV. X, Y column contains a rectangle identification (R) number
and the X, Y coordinates (center) of the rectangle. A graph-
ical representation of the CA diagnosis result from Table IV
D. Step 4: Defect Highlighting is highlighted in Fig. 29.
The fourth step of the CA diagnosis is to create a lay- The potential defective areas as calculated by the CA diag-
out marker file such that a graphical highlighting of the CA nosis experimental flow are all related to the C input of
diagnosis results can be done. For this, the scored defect list, the NAND4 cell and related to the area from the C input
created during the third step of the flow, is used as one of the to the right to its connected p-transistors named MP2. The
inputs. In addition, the physical properties for each defect are red outlined rectangles at “C” are potential open defects. The
used as well. The marker file is then used as input for modern shaded rectangles above and below “C” are potential BR areas.
GDS viewers to highlight the scored CA defect in the original These highlighted defects together with their layer and X, Y
cell layout. coordinates have been used to ease and guide the PFA process.
HAPKE et al.: CELL-AWARE TEST 1407

Fig. 31. 3-D FinFET transistor.

Fig. 29. Cell-aware PFA guidance.

Fig. 30. (a) FIB section for STEM analysis. (b) STEM picture of cross
section. Fig. 32. FinFET leakage and drive-strength defects.

F. Physical Failure Analysis transistors the analog fault simulation introduces transistor
To further prove the effectiveness and correct detection of defects per fin, so that transistor drive-strength and leakage
physical defects by CAT patterns and to prove the effectiveness defects can be analyzed accurately per fin.
of the CA diagnosis, the selected part was put through the PFA Because of the 3-D nature of a FinFET transistor as shown
process. As a consequence of the destructive nature of PFA, we in Fig. 31, each fin of the 3-D transistors can have defects
utilized a multistep approach. This process begins with a fault- on its own, which will result either in reduced drive strength
isolation technique known as laser voltage probing (LVP) [29]. because one or more fins are not operating as they should, or
In LVP, the silicon is exposed to an infra-red laser. The tool in leakage current within one or more fins of the transistor.
generates waveforms by studying the interaction of laser that The leakage defects are analyzed by CAT by inserting and
is modulated by the electric field in the space-charge regions simulating different leaking resistors from drain to source as
of the transistor. shown in Fig. 32, indicated by the red resistors.
Physical de-processing based on the fault isolation was con- Drive-strength defects are analyzed by simulating different
ducted and no physical anomaly was observed on any metal resistor values for the drain and source resistors as shown in
layers down to metal1. Nano probing [30] was then performed Fig. 32, indicated by the green resistors R1 and R2.
on each suspected transistor in the NAND4 cell which identi- The black falling edge in Fig. 32 represents a fault-free cell
fied the pMOS transistor receiving the C input signal as being output waveform. Depending on the severity of a leakage or
non-responsive to the gate voltage. drive strength defect, a larger delay will be observed at the
Finally, a focused ion beam (FIB) [31] cross section was cell output (see the green falling edges), and in addition the
performed to collect a lamella for scanning tunneling electron final settled state may not reach the required low or high state
microscopy (STEM) analysis [32]. The gate and the pMOS in case of a leakage defect (see the red falling edges).
source contact within the lamella is shown in Fig. 30(a). Simulating drive strength and leakage defects accurately per
The STEM analysis in Fig. 30(b) clearly indicated a bro- fin ensures that the CAT ATPG is forced to generate all needed
ken poly in the region between the nMOS and pMOS. The cell input conditions to fully test the drive-strength and leakage
physical gate contact lies closer to the active of the nMOS; defects for FinFET technologies.
so controlling the nMOS gate was still possible. However, the
connection to the pMOS poly gate was broken. This proves X. F UTURE W ORK
that CAT correctly detected a real physical cell-internal defect. In the past years, we concentrated our research and devel-
It confirms the correct prediction of CA diagnostics defect opment effort on methods and tools to ensure that CAT will
scoring which was the third-highest scoring candidate. detect otherwise undetected defects. We have now proven,
through high-volume production test results from over 50 mil-
IX. F IN FET T ECHNOLOGIES lion parts in 28, 32, and 350 nm automotive technologies, that
The CAT methodology fully supports FinFET technologies. CAT uniquely detects otherwise undetected defects; the defect
The CAT view generation process for FinFET technologies is rate measured in DPPM is reduced significantly. We will con-
in principle the same as for other technologies. For FinFET centrate our future research and development work on further
1408 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014

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“Embedded multi-detect ATPG and its effect on the detection of Friedrich Hapke (M’08) received the Diploma in
unmodeled defects,” in Proc. IEEE ITC, Santa Clara, CA, USA, 2007. electrical engineering from the University of Applied
[10] L. Xijiang et al., “Timing-aware ATPG for high quality at-speed test- Sciences, Hamburg, Germany.
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pp. 139–146. Mentor Graphics Silicon Test Solution Division.
[11] S. K. Goel, K. Chakrabarty, M. Yilmaz, K. Peng, and M. Tehranipoor, His primary focus is in research and development
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in Proc. 19th ATS, Shanghai, China, 2010, pp. 307–312. oriented cell-aware testing, IEEE P1687, logic BIST,
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pp. 414–421. tion in general for deep-submicron technologies.
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realistic multiple bridging and break faults,” in Proc. EDAC, Brighton, management positions at NXP and Philips Semiconductors. He has authored
U.K., 1995, pp. 184–189. and co-authored several publications and holds over 20 patents in the area
[14] F. J. Ferguson and J. Shen, “Extraction and simulation of realistic CMOS of design for test. His recent publications have been on the topic of defect-
faults using inductive fault analysis,” in Proc. ITC, Washington, DC, oriented cell-aware testing at the International Symposium on VLSI Design
USA, 1998, pp. 475–484. Automation and Test, 2011, in Taiwan, at the Design Automation and Test in
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libraries using inductive contamination analysis (ICA),” in Proc. VLSI in Annecy, France, at the International Test Conference, 2012, in Anaheim,
VTS, Princeton, NJ, USA, 1996, pp. 405–413. CA, USA, at the European Test Symposium 2013, in Avignon, France, and at
[16] R. C. Aitken, “Finding defects with fault models,” in Proc. ITC, the International Symposium for Testing and Failure Analysis, 2013, in San
Washington, DC, USA, 1995, pp. 498–505. Jose, CA, USA.
HAPKE et al.: CELL-AWARE TEST 1409

Wilfried Redemund (M’10) received the Diploma Marek Hustava received the Diploma in computer
in technical informatics from the University of science from the Slovak University of Technology
Applied Sciences, Hamburg, Germany, in 1986. in Bratislava, Bratislava, Slovakia, in 2002.
He is a Principal Engineer and a Software He is a Principal Digital Engineer and a Digital
Architect with Mentor Graphics Silicon Test prod- Group Leader with ON Semiconductor Design
ucts. Prior to joining Mentor Graphics, he was an Center, Brno, Czech Republic. He has researched for
independent consultant in the DFT and test area. several years in the design of complex automotive
He has co-authored several professional publications mix-signal ICs, and is responsible for digital design
about cell-aware test methods and holds the U.S. methodology including the DFT methodology.
patent in the same area.

Andreas Glowatz (M’03) received the Diploma

in electronics and computer science from the
University of Applied Sciences, Hamburg, Germany, Martin Keim (M’06) received the Ph.D. degree in
in 1988. informatics from the Albert-Ludwigs University of
He is a Principal Engineer and a Software Freiburg, Freiburg im Breisgau, Germany.
Architect with Mentor Graphics Development, He joined the Silicon Test Solutions Group of
Hamburg, Germany. He has over 25 years of expe- Mentor Graphics, Wilsonville, OR, USA, in 2001,
rience in research and development of DFT tools, where he is currently an Engineering Manager of
mainly focused on ATPG, test compression, and the memory built-in self-test team. He is an active
cell-aware test. He holds several patents and has member of the IEEE P1687 Working Group and was
co-authored several publications in this area. an Editor of the sixth edition of the Microelectronics
Failure Analysis Desk Reference Manual, responsi-
ble for the test and diagnosis chapters. He also holds
several national and international patents and has authored several technical
publications.
Dr. Keim has researched for several years on the organizing committee of
Janusz Rajski (A’87-SM’10-F’11) received the the International Symposium for Testing and Failure Analysis, for which he
Ph.D. degree in electrical engineering from the will be the General Chair in 2016.
Poznań University of Technology, Poznań, Poland,
in 1982.
He is a Chief Scientist and the Director of
Engineering with the Silicon Test Solutions Division
at Mentor Graphics, Wilsonville, OR, USA. He has
published over 220 research papers in these areas
and is a co-inventor of 81 U.S. and 27 interna-
tional patents. He is also the Principal Inventor
of Embedded Deterministic Test (EDT) technology Juergen Schloeffel (M’04) received the Diploma
used in the first commercial test compression product TestKompress. He has in physics from the University of Goettingen,
co-authored the book Arithmetic Built-In Self-Test for Embedded Systems pub- Goettingen, Germany.
lished by Prentice Hall, in 1997. He is a Program Manager in the area of EDA and
Dr. Rajski was the co-recipient of the 1993 Best Paper Award for the paper DFT with Mentor Graphics Development, Hamburg,
on logic synthesis published in the IEEE T RANSACTIONS ON C OMPUTER - Germany. His current research interests include
A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS, co-recipient of advanced testing techniques, IJTAG, design automa-
the 1995 and 1998 Best Paper Awards at the IEEE VLSI Test Symposium, tion for DSM technologies, and 3-D test. He is
co-recipient of the 1999 and 2003 Honorable Mention Awards at the IEEE a member of VDE, and a Board Member of the
International Test Conference, as well as the co-recipient of the 2006 IEEE German ITG Working Group for test and reliability.
Circuits and Systems Society Donald O. Pederson Outstanding Paper Award He holds several patents and has authored and co-
recognizing the paper on EDT published in the IEEE T RANSACTIONS ON authored over 60 conference papers and journals. He has served on program
C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS. He committees of several conferences and workshops.
has served on the technical program committees of various conferences, and
has also served as a Program Chair of the IEEE International Test Conference.

Michael Reese (M’01) received the B.S. degree in Anja Fast initially completed an apprenticeship
chemical engineering from the University of Texas as a Hotel Manageress in Hamburg, Germany
at Austin, Austin, TX, USA, and the M.S. degree in 1992. She is now a Technical Assistant with
in electrical engineering from Walden University, Mentor Graphics Development, Hamburg, Germany.
Minneapolis, MN, USA. Before joining Mentor Graphics in 2012, she was
He is a Senior Member of Technical Staff with self-employed with Technical Documentation and
Advanced Micro Devices, Austin, TX, USA, with worked as an Independent Consultant for Mentor
over 25 years of industry experience, where he spent Graphics in the area of DFT. She has co-authored
half of his time in semiconductor manufacturing and several professional publications about cell-aware
the balance in semiconductor design focused on the test methods.
design for test. His current research interests include
scan compression hardware for AMDs CPU core team. He has also been
published several times on the emerging technology known as cell-aware
ATPG.

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