Computer-based project in VLSI Design

Design Specification

Computer-Based Project in VLSI Design

Design Specification

Co 3/7

As outlined in an earlier section, the target design is a complete digital system-on-achip for a frequency synthesiser. A fuller explanation of frequency synthesis methods is given later, and there may be opportunities for some designers to incorporate more elaborate features, provided the basic operating principles have been understood. The basic design contains the following elements: A single 2-input NOR gate is provided for introductory experiments. A ring oscillator module, which provides a master clock. A counter module. This element comprises a binary counter which counts clock pulses input via the clock terminal. A basic design requires a 6-bit counter. A comparator module, which compares the outputs of the counter with a preprogrammed number, applied by means of a set of input pins on the chip, and generates an output when these match. Additional logic to respond to the comparators output and reset the counter; a further element is included so the output waveform is symmetric.

There is considerable scope for individual creativity within the above specification, but each element is dealt with in more detail below. You can read about the architecture of frequency synthesisers later in this chapter. The first stage of development involves creating a representation of the entire system using a hardware description language (HDL) to explore and verify its operation. Figure 1 presents a block diagram showing the organisation of the main elements. Comparator

Control Ring oscillator

Counter

Figure 1 Block Diagram of complete top_level system-on-a-chip

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Design Specification

Ring Oscillator
A key element of this project is the ring oscillator, ring_oscillator, whose development is intended to highlight all the various activities involved in integrated circuit design. During the project you will construct a definition in a hardware description language for it. You will develop a schematic representation of its constituent gates and a graphical symbol; you will have a chance to predict its performance using digital and analogue simulation techniques. You will design and verify the mask layout for the 2 input NOR gate used in its construction, and finally, you will use the ring_oscillator module as a signal source in a programmable divider design which includes counters and other sequential logic devices. The following section describes the specification to which we shall work for the ring_oscillator part of the design. Ring Oscillator Specification The simple theory of the ring oscillator is given in the Design of Logic Gates in CMOS pamphlet, and the relation between gate delay and oscillation frequency is derived. The initial design for ring_oscillator will use the NOR2 part whose detailed specification is provided by Mietec; the salient details are given overleaf. We shall aim to produce a ring oscillator with a single Enable input ENB, and two outputs OUT1 and OUT2 taken direct from the ring_oscillator module, with a stated oscillation frequency and phase difference between them. In order to specify the basic characteristics of the ring oscillator portion of the design, we shall use the criteria detailed opposite. A single instance of the NOR2 gate is also shown in the block diagram in Figure 1. This gate is entirely separate from the ring oscillator and all other parts of the design. It is included to provide a straightforward means of introducing some of the major concepts related to schematic design and simulation. Later on we shall develop our own NOR2 gate at the most detailed level possible, using individual MOS transistors. The result will be a gate which is broadly similar to the Mietec part, but whose delay characteristics will likely be quite different. With a little reflection and research, and with not too much effort you should be able to design a part which works significantly faster than the original library part, and you should be able to identify ways of making the design more compact (and hence cheaper).

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Ring Oscillator Specification

Worst-case operating frequency ~6 MHz, based on Mietec NOR2 part with Vdd = 5 volts and nominal loading capacitances (see overleaf for specification). Input ENB = 1 Input ENB = 0 Oscillator disabled Oscillator enabled

Typical input/output waveforms

Worst-case timing specifications (see waveforms) Parameter T t1 t2 Description Oscillation period Delay from ENB to OUT1 Delay from OUT1 to OUT2 Lower limit Upper limit (ns) (ns) 120 12 30 160 18 50

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ELECTRICAL CHARACTERISTICS

CAPACITANCES INPUT A,B CAPACITANCE 0.104 UNIT pF

TYPICAL PROPAGATION DELAYS (T = 27 Celsius, Vdd = 5V, Cload = 0.2 pF)

OUTPUT A,B to Y Rising Falling

INTRINSIC DELAY 2.7 2.8

UNIT nS nS

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Design Specification

Digital sub-systems
In addition to the ring oscillator core, we shall design and explore various additional digital sub-systems. The theme chosen for this years project is a frequency synthesiser, a key building block in communications systems and other applications. Design of an entire frequency synthesiser is beyond the scope of a short project like this, unfortunately, so we shall confine ourselves to developing the digital parts only. As for the ring oscillator, we shall initially investigate and verify the design using HDL. We shall then consider its implementation. Unlike the ring oscillator, which we shall design and model at the most detailed level possible (creating it from individual MOS transistors), the frequency synthesiser design will wherever possible take advantage of pre-defined library components. These will include: A digital counter constructed from components taken from the Mietec library (combinational gates and D-type bistables). The counters Clock input may be driven by one of the ring oscillator outputs, and the outputs are used to supply clock waveforms needed in other parts of the design. This will emphasise the value of the hierarchical approach to design. A programmable divider, which will be developed to fulfil the requirements for the frequency synthesiser case study being targeted in this project. There is a degree of individual choice available in the specification of this part. The programmable divider can itself be divided into two parts: a counter, and a comparator to allow detection of when the counter enters a pre-programmed state. Additional counters will also be needed to meet the specification. The ring oscillator already described fulfils the role of a variable voltagecontrolled oscillator (VCO). Other elements not being designed here include: a phase-sensitive detector (PSD) In most frequency synthesisers, this is a critically designed analogue multiplier whose detailed design alone would take more time than available for the entire project! It is possible to implement a PSD using an XOR gate, however, and groups making good progress and wishing to push the limits are free to experiment with this idea. a master oscillator. Such a device is normally implemented using an off-chip circuit including a high-stability quartz crystal, typically operating at 1MHz or 10 MHz. Where necessary, we will be able to use simulated signals for this purpose. a low pass filter another critical element normally calling for off-chip components, and an elaborate and time-consuming design procedure.

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Design Specification

Frequency synthesisers
A frequency synthesiser is an electronic system for generating any of a range of frequencies from a single fixed-frequency timebase or oscillator. They are found in many modern communications devices, including radio receivers, mobile telephones, Bluetooth accessories, radiotelephones, walkie-talkies, CB radios, satellite receivers, GPS systems, etc. A typical application is illustrated below, where it is seen that a frequency synthesiser is used as a Local Oscillator in a two-way radio system, providing channel selection by digital control. However, the list of possible applications extends far beyond communications.

A communications application for a frequency synthesiser

Evolution
Prior to widespread use of synthesisers, radio and television receivers relied on manual tuning of a local oscillator, usually by means of a variable capacitor. The availability of varactor diodes, in which a reverse biased p-n junction exhibits a capacitance dependent upon the applied bias, made it possible to miniaturise such systems. However, variations in temperature and aging of components caused frequency drift. Automatic frequency control (AFC) solved some of the drift problem, but manual retuning was stilll often necessary. Since transmitter frequencies are well known and very stable, an accurate means of generating fixed, stable frequencies in the receiver was desirable to solve the problem. A simple and effective solutions employs the use of many stable resonators or oscillators for each tuning frequency. Quartz crystals offer good stability and have often been used for this purpose. However, this approach is practical when only a handful of frequencies are required. It quickly becomes costly and impractical in applications where many frequency channels are required. For example, the FM radio band in many countries supports 100 individual frequencies from about 88 MHz to 108 MHz. Cable television can support even more frequencies or channels over a much wider band. A large number of crystals increases cost and requires more space. Many coherent and incoherent techniques have been devised over the years. Some approaches include phase locked loops, double mix, triple mix, harmonic, double mix divide, and direct digital synthesis (DDS). The choice of approach depends on a number of factors, including cost, complexity, frequency-step size, switching rate, phase noise, and permissible spurious output levels.
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Coherent techniques generate frequencies derived from a single, stable master oscillator. In most applications, the use of a crystal oscillator is widespread, but other forms of resonator and frequency source can be used. Incoherent techniques derive frequencies from a set of several stable oscillators, typically through frequency multiplication, division, and summing/differencing (mixing). The vast majority of synthesizers in commercial applications use coherent techniques because they offer much greater flexibility and can readily be implemented as integrated circuits to give a compact, low-cost solution. Synthesisers used in commercial radio receivers are almost invariably based on phaselocked loops or PLLs. Many types of frequency synthesiser are available as integrated circuits, reducing cost and size. High end receivers and electronic test equipment use more sophisticated techniques still, often in combination.

Principle of PLL synthesisers

The block diagram below shows the basic elements and arrangement of a PLL-based frequency synthesiser. A phase-locked loop does for frequency what the Automatic Gain Control does for stabilisation of voltage or power output in a radio receiver. It compares the frequencies of two signals and produces an error signal which is proportional to the difference between the input frequencies. The error signal is used to drive a voltagecontrolled oscillator (VCO) which generates the required output frequency. The output signal is fed through a frequency divider where it is divided down in a known ratio, and fed as one input (the comparison frequency) to a phase-comparator, which compares the phase of the divided signal with the fixed comparison frequency from the master oscillator. The phase-comparator output, in effect an error signal, is passed through a carefully designed low-pass filter, and fed back to the input of the system to control the operating frequency of the VCO. This arrangement constitutes a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the error.

Classic phase-locked-loop (PLL) frequency synthesiser

Thus the output becomes locked to the frequency at the other input. This input is derived from a crystal oscillator or similar, which is very stable in frequency, and referred to as the reference frequency. Phase-locked loops have many applications both in communications and other branches of electronics; for example:
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Frequency synthesisers for digitally-tuned radio receivers and transmitters Demodulation of both FM and AM signals Recovery of small signals that otherwise would be lost in noise (lock-in amplifier) Recovery of clock timing information from a data stream such as from a disk drive Clock multipliers in microprocessors that allow internal processor elements to run faster than external connections, while maintaining precise timing relationships DTMF decoders, modems, and other tone decoders, for remote control and telecommunications

The key to the ability of a frequency synthesiser to generate multiple frequencies is the divider (N) placed between the output and the phase comparator. This usually takes the form of a digital counter, with the VCO output signal acting as a clock. The counter is preset to some initial count value, and counts down at each cycle of the clock signal. When it reaches zero, the counter output changes state and the count value is reloaded. The figure below illustrates the waveforms expected in a simple case with the divider N set to 4.

Waveforms with M set to 4 This circuit is straightforward to implement using bistable devices (e.g. J-K or D-type flip-flops), and because it is digital in nature, is very easy to interface to other digital components or a microprocessor. This allows the frequency generated by the synthesiser to be easily controlled by a digital system.

Example
Suppose the reference signal is fixed at 1 MHz, and the fixed divider R is set to divide by 10; its output frequency is thus 100 kHz. Assume also that the divider N can be preset to any value between 1 and 100. The error signal produced by the comparator will only be zero when the output of the divider is also 100 kHz. For this to be the case, the VCO must run at a frequency which is 100 kHz the divider count value, N, or f r N R . Thus it will produce an output of 100 kHz for a count of 1, 200 kHz for a count of 2, 1 MHz for a count of 10 and so on. Note that only whole multiples of the comparison frequency (which is the divided reference frequency) can be obtained.

Practical considerations
In practice this type of frequency synthesiser cannot operate over a very wide range of frequencies, because practical comparators have a relatively limited bandwidth and may also suffer from aliasing problems. This would lead to false locking situations, or an inability to lock at all. Furthermore, it is hard to make a high frequency VCO that operates over a very wide range. However, in most systems where a synthesiser is used, we do not seek a huge range, but rather a finite number of channels over some defined range, such as a number of radio channels in a specific band.
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Design Specification

Many radio applications require frequencies higher than can be directly input to the digital counter N. To overcome this, the entire counter could be contructed using very high-speed logic such as Emitter-Coupled Logic (ECL), or more commonly, using a fast initial division stage called a prescaler which reduces the frequency to a manageable level. Since the prescaler is part of the overall division ratio, a fixed prescaler can cause problems designing a system with narrow channel spacings which are often essential in radio communication or broadcast applications. This difficulty can be overcome using a dual-modulus prescaler, discussed below. Further practical aspects concern the amount of time taken for the system to switch from channel to channel, the time to achieve lock when first switched on, and how much noise random fluctuations in the amplitude, frequency or phase - there is in the output. All of these are a function of the loop filter of the system, which is a lowpass filter placed between the output of the frequency comparator and the input of the VCO. Typically, the output of a frequency comparator is in the form of short error pulses, but the input to the VCO must be a smooth, noise-free DC voltage. Any noise on this signal naturally causes unwanted frequency modulation of the VCO. Heavy filtering will reduce this effect, but will lead to a VCO which is unacceptably slow to respond to changes, causing drift and slow response time ; on the other hand, insufficient filtering will produce noise and other problems with harmonics. Thus the design of the filter is crucial to the performance of the system and is, in fact, the main challenge facing the designer of such a system.

A more versatile approach to frequency division

The use of a prescaler in a frequency synthesiser can alleviate many of the problems of frequency selection mentioned. A Prescaler is an electronic divider circuit used in high-frequency synthesiser designs to overcome the problem of generating signals at frequencies too high to be passed directly through the feedback loop of the system. A basic frequency synthesiser as described above generates an output frequency f o , given by the reference frequency f r multiplied by the division ratio N/R such that : fo = fr N R Since N is an integer, the output frequency is necessarily restricted to whole multiples of the divided reference frequency f r R . Typically, these will be the channels for which the radio equipment is designed for, so f r and R will usually be equal chosen so that f r R is equal to the channel spacing. For example, for narrow-band radiotelephones, a channel spacing of 12.5 kHz is typical. This is achieved by an appropriate choice of the master oscillator frequency, and the divider R, for example 1MHz and 80, respectively. Suppose that the divider N is only able to operate at a maximum clock frequency of 10 MHz, but the output f o is required to be in the range of hundreds of MHz range. If we were to interpose a fixed prescaler with a value, M, of say, 40, we may now lower the output frequency easily into the operating range of the divider N. However, this has introduced an additional factor of 40 into the equation, so the output frequency is now: f o = 40 N f r R

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If the comparison frequency f r R were to remain at 12.5 kHz, we would obtain channels at a spacing of 40 12.5 kHz or 500 kHz, in effect only every 40th channel. Alternatively, if we were to reduce f r by a further factor of 40 to compensate, using an additional divider, the comparison frequency would become 312.5 Hz, which is much too low to allow satisfactory filtering and lock performance characteristics. It would also mean greater complexity in the programming of the divider, as only those ratios giving true channels must be selected, not those increments of 1/40th of a channel that become available with the extra divider stage

An enhanced frequency synthesiser

It is relatively straightforward to incorporate a prescaler in an enhanced form of frequency synthesiser. A dual-modulus counter is one which is designed such that it can divide by one of two different factors, usually M and M+1 for example, 2 and 3; 8 and 9, etc. The division factor actually applied is determined by means of a control input.

Frequency synthesiser with integer dual-modulus prescaler In the enhanced design the main divider is split into two parts, the primary part N, and an additional divider A, which has a lower count range than N. Both parts of the main divider are clocked from the output of the dual-modulus prescaler, but only the output of the N divider is fed back to the comparator. This arrangement is sometimes known as a pulse-swallow architecture. Initially, the prescaler is set to divide by M + 1 . Both N and A count down until A reaches zero, at which point the prescaler is switched to give a division ratio of M. At this point, the divider N has completed A counts. Counting continues until N reaches zero, which represents a further N A counts. At this point the cycle repeats. Thus:

f o = f r (M(N A) + A(M + 1 )) R which reduces to f o = f r ( MN + A) R Hence, while the output frequency f o is still related to f r by a factor which depends on MN/R, a further term A is now added. Only the dual-modulus prescaler needs to be constructed from high-speed parts; and the output frequency channel spacing remains the same as the comparison frequency f r R .
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The diagram below shows the elements and arrangement of a frequency synthesiser with dual-modulus prescaler. A and N can be computed from the following formulae, which relates them to the required division ratio V: f o = f r RV A = V mod M N = V div M V = ( MN + A) For this arrangement to work satisfactorily, A must be strictly less than M, as well as being less than or equal to N. These restrictions on the value of A imply that not every imaginable division ratio V is in fact possible unless the counter settings are carefully chosen. For example, V may not fall below M ( M 1) ; and with some choices for M, N and A, certain channels will be unavailable.
It is possible to take this idea still further and develop from it a design that is capable of achieving outputs at frequencies that are fractional multiples of the comparison frequency. This may be achieved by passing the VCO signal through the (N+1) counter for a part of the counting period, and through the N counter for the remainder. In this way an average division ratio of somewhere between N and N+1 is obtained, and hence there is a fractional relationship between the input and output frequencies. This can be achieved with only relatively minor changes to the integer pulse-swallow architecture described, and represents a significant improvement to the basic design, as it means that frequency synthesisers can be used to generate accurately specified, closely-spaced channels at very high operating frequencies in the GHz region. This is beyond the scope of the project, however.

A demanding real-life application

Modern communication protocols tend to allocate closely located channels at very high frequencies. This poses difficult challenges for the system designer. For example, the Bluetooth short-range wireless protocol allocates 79 channels between 2.402 GHz to 2.480 GHz resulting in a channel spacing of 1MHz. The phase noise (and other distortions from the local oscillator used) must be low enough not to cause interference with transmissions on adjacent channels. However, a stand-alone oscillator with sufficiently high stability would not be tunable over a 79 MHz band. Moreover, quartz crystals, regarded as essential in applications where frequency must be accurately determined, do not have resonance frequencies as high as 2.4 GHz. The frequency synthesiser architecture allows these challenges to be met, and integrated solutions are now readily available with chip costs of only a pound or so.

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Notes on other circuit elements

The Phase Comparator As seen, a key element in a frequency synthesizer phase-locked loop is the phase comparator. This compares the phase of the divided VCO to that of the divided reference signal. There are several types of phase detector.

The simplest is an exclusive OR gate, which maintains a 90 phase difference, but it is limited in its effectiveness unless the inputs are already at nearly the same frequency. A more complex approach uses a simple state machine to determine which of the two signals has a zero-crossing earlier or more often. This brings the PLL into lock even when it is off frequency. This type is known as a phase-frequency detector. An analogue four-quadrant multiplier, also known as a mixer, can be used as a phase detector. Multiplying the VCO and comparison signals generates an output consisting of a low-frequency signal whose amplitude is related to the phase difference, or phase error, between the VCO and the comparison, plus a second (unwanted) signal at twice the oscillator frequency that can be eliminated by means of a low-pass filter.

Design Choices
In the pursuit of this project you will need to make a number of design choices at different stages. A detailed specification has been given for the performance of the ring oscillator design, and one of the themes of this project is the interplay between the details of layout and the performance that can be achieved. This will be investigated in Lab 7, and in the laboratory experiment organised to accompany this project. However, we want to leave you with greater freedom of choice in the development of the digital part of the design. From the foregoing it is clear that there must be several viable approaches to the design of a programmable divider suitable for use in a synthesiser. Rather than specify these in minute detail, we will present an outline specification for the required operating frequency, and allow you to investigate the options and make the necessary design choices. You are of course welcome to discuss these options with a Demonstrator; you should be able to establish their feasibility at an early stage using functional simulation (Lab Guide 2), and it will be possible to adapt them (after discussion with a demonstrator). For example, you might conclude that a different Master Oscillator frequency will suit the needs of your project better than the one proposed. If your design might need additional inputs or outputs to/from the chip, you should also discuss this with a Demonstrator You are expected to include in your First Interim Report as detailed a specification as possible of the target design your group has converged upon.

Frequency Synthesiser Specification

Design Parameter Number of discrete channel frequencies Nominal frequency of operation Channel frequency spacing Master Oscillator reference frequency Dual modulus counter (if required)
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Specification 40 minimum 5 5.5 MHz 10 kHz 1 MHz 2, 3

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