Ministry of Electronics & Information Technology

Government of India

Aurangabad.

Department of Electronics Engineering

LABORATORY MANUAL
For

VLSI DESIGN
DEPM

Name: _____________________________________
Class: ________ Branch: ______ Roll No: ______

University Exam /
Seat No.

Academic year
20xx-20xx
Ministry of Electronics & Information Technology
Government of India

Aurangabad.
Department of Electronics & Telecommunication
Engineering

This is to certify that Mr./Ms. .………………………………………………………………

Roll No. ………, of VIth/VIIth Semester of Diploma in Electronics has completed the

Term-work / Practical satisfactorily in VLSI DESIGN for the academic year …….
to …… as prescribed by MSBT.

Staff Incharge Head of the Department Executive Director

 PERTICULARS OF THE EXPERIMENTS PERFORMED
CONTENTS

Sr. Date Title of Experiments Conduction Viva Record Total Signature

(05) (05) (05) (15)
no of Staff
Group A

1 To write the HDL code for

Basic and universal logic
gate
2 To write the HDL code for
8:1 Multiplexer

3 To write the HDL code for

1:8 De-multiplexers
4 To write the HDL code for
3:8 Decoder.
5 To write the HDL code for
Shift Register.
6 To write the HDL code for
Adder.
a)Half Adder b) Full Adder
7 To write the HDL code for
ALU.
8 To write the HDL code for
Comparator Circuits.
9 To write the HDL code for
Flip Flops.
a)D – FF b) JK-FF c) T-FF
10 To write the HDL code for
sequential counter.
11 To write the HDL code for
BCD to 7 Segment Decoder.
 Experiment No. : 1

AIM:To design Basic and Universal Logic Gates using VHDL.

SOFTWARE USED: Xilinx Vivado 2017.

HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable
 PC

PROCEDURE:
1) Open Xilinx Vivado 2017 software to write a program for
Basic Gate
2) Declare input and output in entity.
3) Write VHDL code for Basic Gate in architecture.
4) Save the program and check the syntax.
5) Assign the package pins for input and output which is
mentioned in entity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

VLSI Lab Manual Page 1

THEORY:
A logic gate performs a logic operation one or more logic
imputs and produces a single logic output. The logic normally
performed is Boolean Logic and is most commonly found in
digital circuits. Logic gates are primarily found implemented
electronically using diodes or transistors.

AND GATE:

The AND gate is an electronic circuit that gives a high output (1) only
if all its inputs are high. A dot (.) is used to show the AND operation i.e.
A.B. Bear in mind that this dot is sometimes omitted i.e. AB

OR GATE:

The OR gate is an electronic circuit that gives a high output (1) if one or
more of its inputs are high. A plus (+) is used to show the OR operation.

NOT GATE:

he NOT gate is an electronic circuit that produces an inverted version of the

input at its output. It is also known as an inverter. If the input variable is A,
the inverted output is known as NOT A.This is also shown as A', or A with a
bar over the top, as shown at the outputs.

NAND GATE:

VLSI Lab Manual Page 2

This is a NOT-AND gate which is equal to an AND gate followed by a NOT
gate. The outputs of all NAND gates are high if any of the inputs are
low.The symbol is an AND gate with a small circle on the output. The small
circle represents inversion.

NOR GATE:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT

gate. The outputs of all NOR gates are low if any of the inputs are high.The
symbol is an OR gate with a small circle on the output. The small circle
represents inversion.

Ex-OR GATE:

The 'Exclusive-OR' gate is a circuit which will give a high output if either,
but not both, of its two inputs are high. An encircled plus sign ( ) is used
to show the EXOR operation.

Ex-NOR GATE:

The 'Exclusive-NOR' gate circuit does the opposite to the EXOR gate. It
will give a low output if either, but not both, of its two inputs are high. The
symbol is an EXOR gate with a small circle on the output. The small circle
represents inversion.
VLSI Lab Manual Page 3
PROGRAMS:

OR GATE

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity OrGate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end OrGate;

architecture Behavioral of OrGate is

begin
Y <= A OR B;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY or1_tb IS
END or1_tb;

ARCHITECTURE Behavioral OF or1_tb IS

COMPONENT OrGate
PORT(
A : IN std_logic;
B : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;
signal A : std_logic := '0';

VLSI Lab Manual Page 4

 signal B : std_logic := '0';
signal Y : std_logic;

BEGIN
uut: OrGate PORT MAP (
A => A,
B => B,
Y => Y
);

stim_proc: process
begin
wait for 100 ns;
A <= '0';
B <='0';
wait for 100 ns;
A <= '0';
B <='1';
wait for 100 ns;
A <= '1';
B <='0';
wait for 100 ns;
A <= '1';
B <='1';
wait for 100 ns;
wait;
end process;
end Behavioral;

AND GATE

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);

VLSI Lab Manual Page 5

end AndGate;

architecture Behavioral of AndGate is

begin
Y <= A AND B;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY and1_tb IS
END and1_tb;

ARCHITECTURE Behavioral OF and1_tb IS

COMPONENT AndGate
PORT(
A : IN std_logic;
B : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';
signal Y : std_logic;

BEGIN
uut: AndGate PORT MAP (
A => A,
B => B,
Y => Y
);
stim_proc: process
begin
wait for 100 ns;
A <= '0';
B <='0';
wait for 100 ns;
A <= '0';
B <='1';
wait for 100 ns;
VLSI Lab Manual Page 6
 A <= '1';
B <='0';
wait for 100 ns;
A <= '1';
B <= '1';
wait for 100 ns;
wait;
end process;
End Behavioral;

NOT GATE

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NotGate is
Port ( A : in STD_LOGIC;
Y : out STD_LOGIC);
end NotGate;

architecture Behavioral of NotGate is

begin
Y <= NOT A;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY not1_tb IS
END not1_tb;

ARCHITECTURE Behavioral OF not1_tb IS

COMPONENT NotGate
PORT(
A : IN std_logic;

VLSI Lab Manual Page 7

 Y : OUT std_logic
);
END COMPONENT;
signal A : std_logic := '0';
signal Y : std_logic;
BEGIN

uut: NotGate PORT MAP (

A => A,
Y => Y
);

stim_proc: process
begin
wait for 100 ns;
A <= '0';
wait for 100 ns;
A <= '1';
wait for 100 ns;
wait;
end process;
end Behavioral;

NAND GATE

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NandGate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end NandGate;

architecture Behavioral of NandGate is

begin
Y <= A NAND B;
end Behavioral;

VLSI Lab Manual Page 8

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY nand1_tb IS
END nand1_tb;

ARCHITECTURE Behavioral OF nand1_tb IS

COMPONENT NandGate
PORT(
A : IN std_logic;
B : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';
signal Y : std_logic;
BEGIN
uut: NandGate PORT MAP (
A => A,
B => B,
Y => Y
);
stim_proc: process
begin
wait for 100 ns;
A <= '0';
B <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
wait for 100 ns;
A <= '1';
B <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
wait for 100 ns;
wait;
end process;
VLSI Lab Manual Page 9
end Behavioral;

NOR GATE

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NorGate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end NorGate;

architecture Behavioral of NorGate is

begin
Y <= A NOR B;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY nor1_tb IS
END nor1_tb;

ARCHITECTURE Behavioral OF nor1_tb IS

COMPONENT NorGate
PORT(
A : IN std_logic;
B : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';
signal Y : std_logic;

VLSI Lab Manual Page 10

BEGIN
uut: NorGate PORT MAP (
A => A,
B => B,
Y => Y
);
stim_proc: process
begin
wait for 100 ns;
A <= '0';
B <='0';
wait for 100 ns;
A <= '0';
B <= '1';
wait for 100 ns;
A <= '1';
B <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
wait for 100 ns;
wait;
end process;
end Behavioral;

Ex-OR GATE

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity XorGate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end XorGate;

architecture Behavioral of XorGate is

begin

VLSI Lab Manual Page 11

Y <= A XOR B;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY xor1_tb IS
END xor1_tb;

ARCHITECTURE Behavioral OF xor1_tb IS

COMPONENT XorGate
PORT(
A : IN std_logic;
B : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Y : std_logic;
BEGIN
uut: XorGate PORT MAP (
A => A,
B => B,
Y => Y
);
stim_proc: process
begin
wait for 100 ns;
A <= '0';
B <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
wait for 100 ns;
A <= '1';
B <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
wait for 100 ns;
VLSI Lab Manual Page 12
 wait;
end process;
end Behavioral;

Ex-NOR GATE

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity XnorGate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end XnorGate;

architecture Behavioral of XnorGate is

begin
Y <= A XNOR B;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY xnor1_tb IS
END xnor1_tb;

ARCHITECTURE Behavioral OF xnor1_tb IS

COMPONENT XnorGate
PORT(
A : IN std_logic;
B : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';

VLSI Lab Manual Page 13

 signal Y : std_logic;
BEGIN
uut: XnorGate PORT MAP (
A => A,
B => B,
Y => Y
);
stim_proc: process
begin
wait for 100 ns;
A <= '0';
B <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
wait for 100 ns;
A <= '1';
B <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
wait for 100 ns;
wait;
end process;
end Behavioral;

Observation:
1) K- map whenever required
2) Truth table whenever required
3) RTC Schematic for all
4) Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

Simulation Result:

OR GATE

VLSI Lab Manual Page 14

Vivado Schematic Diagram:

Vivado Testbench:

AND GATE

Vivado Schematic Diagram:

VLSI Lab Manual Page 15

Vivado Testbench:

NOT GATE

Vivado Schematic Diagram:

VLSI Lab Manual Page 16

Vivado Testbench:

NAND GATE

Vivado Schematic Diagram:

VLSI Lab Manual Page 17

Vivado Testbench:

NOR GATE

Vivado Schematic Diagram:

VLSI Lab Manual Page 18

Vivado Testbench:

Ex-OR GATE

Vivado Schematic Diagram:

VLSI Lab Manual Page 19

Vivado Testbench:

Ex-NOR GATE

Vivado Schematic Diagram:

VLSI Lab Manual Page 20

Vivado Testbench:

Conclusion:Hence, we have analyzed Basic and Universal Logic

Gates using VHDL.

Experiment No. 2

AIM:To design Half Adder using VHDL.

VLSI Lab Manual Page 21

SOFTWARE USED: Xilinx Vivado 2017.

HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable
 PC

PROCEDURE:
1) Open Xilinx Vivado 2017 software to write a program for
Half Adder.
2) Declare input and output in entity.
3) Write VHDL code for Half Adder in architecture.
4) Save the program and check the syntax.
5) Assign the package pins for input and output which is
mentioned inentity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

THEORY:

Half Adder is a combinational logic circuit which is designed

by connecting one EX-OR gate and one AND gate. The half
adder circuit has two inputs: A and B, which add two input
digits and generates a carry and a sum.

VLSI Lab Manual Page 22

The output obtained from the EX-OR gate is the sum of the two
numbers while that obtained by AND gate is the carry. There
will be no forwarding of carry addition because there is no
logic gate to process that. Thus, this is called Half Adder
circuit.
Logical Expression :
Sum = A XOR B
Carry = A AND B

PROGRAM:

1) VHDL CODE

VLSI Lab Manual Page 23

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Half_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end Half_Adder;

architecture Behavioral of Half_Adder is

begin
Sum <= A XOR B;
Carry <= A AND B;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY halfaddertb IS
END halfaddertb;

ARCHITECTURE Behavioral OF halfaddertb IS

COMPONENT Half_Adder
PORT(
VLSI Lab Manual Page 24
 A : IN std_logic;
B : IN std_logic;
Sum : OUT std_logic;
Carry : OUT std_logic
);
END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';
signal Sum : std_logic;
signal Carry : std_logic;

BEGIN
uut: Half_Adder PORT MAP (
A => A,
B => B,
Sum => Sum,
Carry => Carry
);
process
begin
wait for 100 ns;
A <= '0';
B <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
VLSI Lab Manual Page 25
 wait for 100 ns;
A <= '1';
B <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
end process;
end Behavioral;

Observation:
1) K- map whenever required
2) Truth table whenever required
3) RTC Schematic for all
4) Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

SIMULATION RESULT:

Vivado Schematic Diagram

VLSI Lab Manual Page 26

Vivado Test Bench

CONCLUSION: Hence, we have analyzed Half Adder using

VHDL.

Experiment No.3

VLSI Lab Manual Page 27

AIM:To design Full Adder using VHDL.

SOFTWARE USED: Xilinx Vivado 2017.

HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable
 PC

PROCEDURE:
1) Open Xilinx Vivado 2017 software to write a program for
Full Adder.
2) Declare input and output in entity.
3) Write VHDL code for Full Adder in architecture.
4) Save the program and check the syntax.
5) Assign the package pins for input and output which is
mentioned inentity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

THEORY:

Full Adder is the circuit which consists of two EX-OR gates, two
AND gates and one OR gate. Full Adder is the adder which adds
three inputs and produces two outputs which consists of two
EX-OR gates, two AND gates and one OR gate. The first two
inputs are A and B and the third input is an input carry as C-IN.
VLSI Lab Manual Page 28
The output carry is designated as C-OUT and the normal output
is designated as S which is SUM.

Equation obtained by EX-OR gate is the sum of the binary digits.

While the output obtained by AND gate is the carry obtained by
addition.

Logical Expression :

VLSI Lab Manual Page 29

SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕
B)

PROGRAMS:

1) VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end Full_Adder;

architecture Behavioral of Full_Adder is

begin
Sum <= A XOR B XOR Cin;
Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);
end Behavioral;

2) VHDL TEST BENCH CODE

VLSI Lab Manual Page 30

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY fulladdertb IS
END fulladdertb;

ARCHITECTURE Behavioral OF fulladdertb IS

COMPONENT Full_Adder
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Cout : OUT std_logic;
Sum : OUT std_logic
);
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Cin : std_logic := '0';
signal Cout : std_logic;
signal Sum : std_logic;
BEGIN
uut: Full_Adder PORT MAP (
A => A,
B => B,
VLSI Lab Manual Page 31
 Cin => Cin,
Cout => Cout,
Sum => Sum
);
process
begin
wait for 100 ns;
A <= '0';
B <= '0';
Cin <= '0';
wait for 100 ns;
A <= '0';
B <= '0';
Cin <= '1';
wait for 100 ns;
A <= '0';
B <= '1';
Cin <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
Cin <= '1';
wait for 100 ns;
A <= '1';
B <= '0';
Cin <= '0';
wait for 100 ns;
VLSI Lab Manual Page 32
 A <= '1';
B <= '0';
Cin <= '1';
wait for 100 ns;
A <= '1';
B <= '1';
Cin <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
Cin <= '1';
end process;
end Behavioral;

Observation:
1) K- map whenever required
2) Truth table whenever required
3) RTC Schematic for all
4) Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

SIMULATION RESULT:

Vivado Schematic Diagram

VLSI Lab Manual Page 33

Vivado Test Bench

CONCLUSION: Hence, we have analyzed Half Adder using

VHDL.

Experiment No.4

AIM:To design Structural model of Half Adder and Full Adder

using VHDL.
VLSI Lab Manual Page 34
SOFTWARE USED: Xilinx Vivado 2017.

HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable
 PC

PROCEDURE:
1) Open Xilinx Vivado 2017 software to write a structural
program for Half Adder andFull Adder.
2) Declare input and output in entity.
3) Write VHDL code for Half Adder and Full Adder in
architecture.
4) Save the program and check the syntax.
5) Assign the package pins for input and output which is
mentioned inentity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

THEORY:

HALF ADDER

VLSI Lab Manual Page 35

Half Adder is a combinational logic circuit which is designed
by connecting one EX-OR gate and one AND gate. The half
adder circuit has two inputs: A and B, which add two input
digits and generates a carry and a sum.

The output obtained from the EX-OR gate is the sum of the two
numbers while that obtained by AND gate is the carry. There
will be no forwarding of carry addition because there is no
logic gate to process that. Thus, this is called Half Adder
circuit.
Logical Expression :
Sum = A XOR B
Carry = A AND B

FULL ADDER
VLSI Lab Manual Page 36
Full Adder is the circuit which consists of two EX-OR gates,
two AND gates and one OR gate. Full Adder is the adder which
adds three inputs and produces two outputs which consists of
two EX-OR gates, two AND gates and one OR gate. The first
two inputs are A and B and the third input is an input carry as
C-IN. The output carry is designated as C-OUT and the normal
output is designated as S which is SUM.

Equation obtained by EX-OR gate is the sum of the binary digits.

While the output obtained by AND gate is the carry obtained by
addition.

VLSI Lab Manual Page 37

Logical Expression :
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕
B)
PROGRAMS:

HALF ADDER

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity halfAdder is
Port ( A : in STD_LOGIC;

VLSI Lab Manual Page 38

 B : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end halfAdder;

architecture Behavioral of halfAdder is

component XOR1
port (I1, I2 : in std_logic;
O1 : out std_logic);
end component;
component AND1
port (I1, I2 : in std_logic;
O1 : out std_logic);
end component;
begin
X1 : XOR1 port map (A, B, Sum);
A1 : AND1 port map (A, B, Carry);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity XOR1 is
port(I1, I2 : in std_logic;
O1 : out std_logic);
end XOR1;
VLSI Lab Manual Page 39
architecture Behavioral of XOR1 is
begin
O1 <= I1 XOR I2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AND1 is
port (I1, I2 : in std_logic;
O1 : out std_logic);
end AND1;
architecture Behavioral of AND1 is
begin
O1 <= I1 AND I2;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity halfAdder_testbench is
end halfAdder_testbench;

architecture Behavioral of halfAdder_testbench is

VLSI Lab Manual Page 40
COMPONENT halfAdder
PORT(
A : IN std_logic;
B : IN std_logic;
Sum : OUT std_logic;
Carry : OUT std_logic
);
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Sum : std_logic;
signal Carry : std_logic;
BEGIN
uut: halfAdder PORT MAP (
A => A,
B => B,
Sum => Sum,
Carry => Carry
);
process
begin
wait for 100 ns;
A <= '0';
B <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
VLSI Lab Manual Page 41
 wait for 100 ns;
A <= '1';
B <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
end process;
end Behavioral;

FULL ADDER

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fullAdder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end fullAdder;

architecture Behavioral of fullAdder is

component HA
port (I1, I2 : in std_logic;
VLSI Lab Manual Page 42
 O1,O2 : out std_logic);
end component;
component OR2
port (I1, I2 : in std_logic;
O1 : out std_logic);
end component;
SIGNAL S1,C1,C2 :STD_LOGIC;
begin
HA1 : HA port map (A, B, S1, C1);
HA2 : HA port map (S1, Cin, Sum, C2);
A1 : OR2 port map (C2, C1, Cout);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HA is
port(I1, I2 : in std_logic;
O1,O2 : out std_logic);
end HA;
architecture Behavioral of HA is
begin
O1 <= I1 XOR I2;
O2 <= I1 AND I2;
end Behavioral;

VLSI Lab Manual Page 43

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity OR2 is
port (I1, I2 : in std_logic;
O1 : out std_logic);
end OR2;
architecture Behavioral of OR2 is
begin
O1 <= I1 OR I2;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fullAdder_testbench is
end fullAdder_testbench;
architecture Behavioral of fullAdder_testbench is
COMPONENT fullAdder
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Cout : OUT std_logic;
Sum : OUT std_logic
VLSI Lab Manual Page 44
 );
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Cin : std_logic := '0';
signal Cout : std_logic;
signal Sum : std_logic;
BEGIN
uut: fullAdder PORT MAP (
A => A,
B => B,
Cin => Cin,
Cout => Cout,
Sum => Sum
);
process
begin
wait for 100 ns;
A <= '0';
B <= '0';
Cin <= '0';
wait for 100 ns;
A <= '0';
B <= '0';
Cin <= '1';
wait for 100 ns;
A <= '0';
VLSI Lab Manual Page 45
 B <= '1';
Cin <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
Cin <= '1';
wait for 100 ns;
A <= '1';
B <= '0';
Cin <= '0';
wait for 100 ns;
A <= '1';
B <= '0';
Cin <= '1';
wait for 100 ns;
A <= '1';
B <= '1';
Cin <= '0';
wait for 100 ns;
A <= '1';
B <= '1';
Cin <= '1';
end process;
end Behavioral;

Observation:
1) K- map whenever required
VLSI Lab Manual Page 46
 2) Truth table whenever required
3) RTC Schematic for all
4) Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

SIMULATION RESULT:

HALF ADDER
VIVADO Schematic Diagram

VIVADO Test Bench

VLSI Lab Manual Page 47

FULL ADDER

VIVADO Schematic Diagram

VIVADO Test Bench

VLSI Lab Manual Page 48

CONCLUSION: Hence, we have analyzed the structural
modelling of Half Adder and Full Adder.

Experiment No.5

AIM:To design 4-bit Adder using VHDL.

SOFTWARE USED: Xilinx Vivado 2017.

HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable
 PC
VLSI Lab Manual Page 49
PROCEDURE:
1) Open Xilinx Vivado 2017 software to write aprogram for
4-bit Adder.
2) Declare input and output in entity.
3) Write VHDL code for 4-bit Adder in architecture.
4) Save the program and check the syntax.
5) Assign the package pins for input and output which is
mentioned inentity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

THEORY:

Lets consider two 4-bit binary numbers A and B as inputs to the

Digital Circuit for the operation with digits
A0 A1 A2 A3 for A
B0 B1 B2 B3 for B
The circuit consists of 4 full adders since we are performing
operation on 4-bit numbers. There is a control line K that holds a
binary value of either 0 or 1 which determines that the operation
being carried out is addition or subtraction.
As shown in the figure, the first full adder has control line
directly as its input(input carry C0), The input A0 (The least
significant bit of A) is directly input in the full adder. The third
input is the exor of B0 and K (S in fig But do not confuse it with

VLSI Lab Manual Page 50

Sum-S). The two outputs produced are Sum/Difference (S0) and
Carry (C1).
If the value of K (Control line) is 1, th output of
B0(exor)K=B0′(Complement B0). Thus the operation would be
A+(B0′). Now 2’s complement subtraction for two numbers A
and B is given by A+B’. This suggests that when K=1, the
operation being performed on the four bit numbers is
subtraction.

Similarly If the Value of K=0, B0 (exor) K=B0. The operation is

A+B which is simple binary addition. This suggests that When
K=0, the operation being performed on the four bit numbers is
addition.
Then C0 is serially passed to the second full adder as one of it’s
outputs.The sum/difference S0 is recorded as the least
significant bit of the sum/difference. A1, A2, A3 are direct
inputs to the second, third and fourth full adders.Then the third
input is the B1, B2, B3 EXORed with K to the second, third and
fourth full adder respectively. The carry C1, C2 are serially
passed to the successive full adder as one of the inputs. C3
VLSI Lab Manual Page 51
becomes the total carry to the sum/difference. S1, S2, S3 are
recorded to form the result with S0.
For an n-bit binary adder-subtractor, we use n number of full
adders.

PROGRAMS:

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder_4bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end adder_4bit;

architecture Behavioral of adder_4bit is

component fa is
port(
a,b,c:in std_logic;
co:out std_logic;
s:out std_logic
);
VLSI Lab Manual Page 52
end component;
signal C1,C2,C3:std_logic;
begin
fa1: fa port map(A(0),B(0),Cin,C1,Sum(0));
fa2: fa port map(A(1),B(1),C1,C2,Sum(1));
fa3: fa port map(A(2),B(2),C2,C3,Sum(2));
fa4: fa port map(A(3),B(3),C3,Cout,Sum(3));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fa is
port( a,b,c:in std_logic;
co:out std_logic;
s:out std_logic);
end fa;

architecture Behavioral of fa is
begin
s <= a xor b xor c;
co <= (a and b) or (c and (a or b));
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
VLSI Lab Manual Page 53
use IEEE.STD_LOGIC_1164.ALL;

entity adder_4bit_testbench is
-- Port ( );
end adder_4bit_testbench;

architecture Behavioral of adder_4bit_testbench is

COMPONENT adder_4bit
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
Sum : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;

signal A : std_logic_vector(3 downto 0) := (others => '0');

signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';

signal Sum : std_logic_vector(3 downto 0);

signal Cout : std_logic;

BEGIN
uut: adder_4bit PORT MAP (
A => A,
VLSI Lab Manual Page 54
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);
stim_proc: process
begin
A <= "0000"; B <= "0101"; -- 0 + 5 => 05 (0 0101)
WAIT FOR 100 ns;
A <= "0001"; B <= "0111"; -- 1 + 7 => 08 (0 1000)
WAIT FOR 100 ns;
A <= "0010"; B <= "1001"; -- 2 + 9 => 0B (0 1011)
WAIT FOR 100 ns;
A <= "0011"; B <= "1011"; -- 3 + B => 0E (0 1110)
WAIT FOR 100 ns;
A <= "0100"; B <= "1101"; -- 4 + D => 11 (1 0001)
WAIT FOR 100 ns;
A <= "0101"; B <= "1111"; -- 5 + F => 14 (1 0100)
WAIT FOR 100 ns;
A <= "0110"; B <= "0001"; -- 6 + 1 => 07 (0 0111)
WAIT FOR 100 ns;
A <= "0111"; B <= "0011"; -- 7 + 3 => 0A (0 1010)
WAIT FOR 100 ns;
A <= "1000"; B <= "0101"; -- 8 + 5 => 0D (0 1101)
WAIT FOR 100 ns;
A <= "1001"; B <= "0111"; -- 9 + 7 => 10 (1 0000)
WAIT FOR 100 ns;
VLSI Lab Manual Page 55
end process;
end Behavioral;

Observation:
1) K- map whenever required
2) Truth table whenever required
3) RTC Schematic for all
4) Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

SIMULATION RESULT:

VIVADO Schematic Diagram

VIVADO Test Bench

VLSI Lab Manual Page 56

CONCLUSION: Hence, we have analyzed 4-bit Adder using
VHDL.

Experiment No.6

AIM:To design Multiplexers 4:1 and 8:1 using VHDL.

SOFTWARE USED: Xilinx Vivado 2017.

HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable
 PC

VLSI Lab Manual Page 57

PROCEDURE:
1) Open Xilinx Vivado 2017 software to write aprogram for 4:1
and 8:1 Multiplexers.
2) Declare input and output in entity.
3) Write VHDL code for 4:1 and 8:1 Multiplexers in
4) Save the program and check the syntax.
architecture.
5) Assign the package pins for input and output which is
mentioned inentity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

THEORY:

Multiplexer is a combinational circuit that has maximum of

2n data inputs, ‘n’ selection lines and single output line. One of
these data inputs will be connected to the output based on the
values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible
combinations of zeros and ones. So, each combination will
select only one data input. Multiplexer is also called as Mux.

4:1 Multiplexer

4:1 Multiplexer has four data inputs I3, I2, I1 & I0, two
selection lines s1 & s0 and one output Y. The block
diagram of 4:1 Multiplexer is shown in the following figure.
One of these 4 inputs will be connected to the output based on
the combination of inputs present at these two selection
lines. Truth table of 4:1 Multiplexer is shown below.
VLSI Lab Manual Page 58
From Truth table, we can directly write the Boolean
function for output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3
We can implement this Boolean function using Inverters, AND
gates & OR gate. The circuit diagram of 4:1 multiplexer is
shown in the following figure.

VLSI Lab Manual Page 59

8x1 Multiplexer

In this section, let us implement 8x1 Multiplexer using 4x1

Multiplexers and 2:1 Multiplexer. We know that 4x1
Multiplexer has 4 data inputs, 2 selection lines and one output.
Whereas, 8:1 Multiplexer has 8 data inputs, 3 selection lines
and one output.
So, we require two 4:1 Multiplexers in first stage in order to
get the 8 data inputs. Since, each 4:1 Multiplexer produces one
output, we require a 2:1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce
the final output.
Let the 8:1 Multiplexer has eight data inputs I7 to I0, three
selection lines s2, s1 & s0 and one output Y. The Truth
table of 8:1 Multiplexer is shown below.

VLSI Lab Manual Page 60

We can implement 8:1 Multiplexer using lower order
Multiplexers easily by considering the above Truth table.
The block diagram of 8:1 Multiplexer is shown in the
following figure.

VLSI Lab Manual Page 61

The same selection lines, s1 & s0 are applied to both 4:1
Multiplexers. The data inputs of upper 4:1 Multiplexer are I7 to
I4 and the data inputs of lower 4:1 Multiplexer are I3 to I0.
Therefore, each 4:1 Multiplexer produces an output based on
the values of selection lines, s1 & s0.
The outputs of first stage 4:1 Multiplexers are applied as inputs
of 2:1 Multiplexer that is present in second stage. The
other selection line, s2 is applied to 2:1 Multiplexer.
 If s2 is zero, then the output of 2:1 Multiplexer will be
one of the 4 inputs I3 to I0 based on the values of
selection lines s1 & s0.
 If s2 is one, then the output of 2:1 Multiplexer will be one
of the 4 inputs I7 to I4 based on the values of selection
lines s1 & s0.

VLSI Lab Manual Page 62

Therefore, the overall combination of two 4:1 Multiplexers and
one 2:1 Multiplexer performs as one 8:1 Multiplexer.
PROGRAMS:

4:1 MULTIPLEXER

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer4to1 is
Port ( I3 : in STD_LOGIC_VECTOR (2 downto 0);
I2 : in STD_LOGIC_VECTOR (2 downto 0);
I1 : in STD_LOGIC_VECTOR (2 downto 0);
I0 : in STD_LOGIC_VECTOR (2 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end Multiplexer4to1;

architecture Behavioral of Multiplexer4to1 is

begin
process(I3,I2,I1,I0,S)
begin
case S is
when "00" => Y <= I3;
when "01" => Y <= I2;
when "10" => Y <= I1;
when "11" => Y <= I0;
when others => Y <= "ZZZ";
end case;
end process;
end Behavioral;

2) VHDL TESTBENCH CODE

VLSI Lab Manual Page 63

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux_TB is
end Mux_TB;

architecture Behavioral of Mux_TB is

signal T_I3: std_logic_vector(2 downto 0):="000";
signal T_I2: std_logic_vector(2 downto 0):="000";
signal T_I1: std_logic_vector(2 downto 0):="000";
signal T_I0: std_logic_vector(2 downto 0):="000";
signal T_Y: std_logic_vector(2 downto 0);
signal T_S: std_logic_vector(1 downto 0);
component Multiplexer4to1
port(I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
Y: out std_logic_vector(2 downto 0)
);
end component;
begin
U_Mux: Multiplexer4to1 port map (T_I3, T_I2, T_I1, T_I0, T_S,
T_Y);
process
begin
T_I3 <= "001"; --1 -- I0-I3 are different signals
T_I2 <= "010"; --2
T_I1 <= "101"; --5
T_I0 <= "111"; --7
-- case select eqaul "00"
wait for 100 ns;
T_S <= "00"; T_Y <= T_I3;
-- case select equal "01"
wait for 100 ns;
T_S <= "01"; T_Y <= T_I2;

VLSI Lab Manual Page 64

 -- case select equal "10"
wait for 100 ns;
T_S <= "10"; T_Y <= T_I1;
-- case select equal "11"
wait for 100 ns;
T_S <= "11"; T_Y <= T_I0;
-- case equal "11"
wait for 100 ns;
T_S <= "UU";
wait;
end process;
end Behavioral;

8:1 MULTIPLEXER

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplexer8_to_1 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end multiplexer8_to_1;

architecture Behavioral of multiplexer8_to_1 is

begin
process (I, S)
begin
case S is
when "000" => Y <= I(0);
when "001" => Y <= I(1);
when "010" => Y <= I(2);
when "011" => Y <= I(3);
when "100" => Y <= I(4);
when "101" => Y <= I(5);

VLSI Lab Manual Page 65

when "110" => Y <= I(6);
when "111" => Y <= I(7);
when others=> null;
end case;
end process;
end Behavioral;

2) VHDL TESTBENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplexer8_to_1testbench is
-- Port ( );
end multiplexer8_to_1testbench;

architecture Behavioral of multiplexer8_to_1testbench is

COMPONENT multiplexer8_to_1
PORT(
I:IN std_logic_vector(7 downto 0);
S:IN std_logic_vector(2 downto 0);
Y:OUT std_logic
);
END COMPONENT;
SIGNAL I : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL S : std_logic_vector(2 downto 0) := (others=>'0');
SIGNAL Y : std_logic;
BEGIN
uut: multiplexer8_to_1 PORT MAP(I => I,
S => S,
Y => Y
);
stim_proc_I : process
begin
I <= "10101010";
wait for 1000ns;
end process;

VLSI Lab Manual Page 66

stim_proc_S : process
begin
S<="000";
wait for 100ns;
S<="001";
wait for 100ns;
S<="010";
wait for 100ns;
S<="011";
wait for 100ns;
S<="100";
wait for 100ns;
S<="101";
wait for 100ns;
S<="110";
wait for 100ns;
S<="111";
wait for 100ns;
end process;
end Behavioral;

Observation:
1) K- map whenever required
2) Truth table whenever required
3) RTC Schematic for all
4)Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

SIMULATION RESULT:

4:1 MULTIPLEXER
VIVADO Schematic Diagram

VLSI Lab Manual Page 67

VIVADO Test Bench

8:1 MULTIPLEXER

VIVADO Schematic Diagram

VLSI Lab Manual Page 68

VIVADO Test Bench

CONCLUSION: Hence, we have analyzed Multiplexer 4:1 and

8:1 using VHDL.

Experiment No.7

AIM:To design 1:4 and 1:8 Demultiplexers using VHDL.

VLSI Lab Manual Page 69

SOFTWARE USED: Xilinx Vivado 2017.

HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable
 PC

PROCEDURE:
1) Open Xilinx Vivado 2017 software to write aprogram for 1:4
and 1:8 Demultiplexers.
2) Declare input and output in entity.
3) Write VHDL code for 1:4 and 1:8Demultiplexers in
architecture.
4) Save the program and check the syntax.
5) Assign the package pins for input and output which is
mentioned inentity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

THEORY:

A Demultiplexer is a data distributor read as DEMUX. It is quite

opposite to multiplexer or MUX. It is a process of taking
information from one input and transmitting over one of many
outputs. This article explains different types of Demultiplexers.

VLSI Lab Manual Page 70

DEMUX are used to implement general-purpose logic systems.
A demultiplexer takes one single input data line and distributes
it to any one of a number of individual output lines one at a
time. Demultiplexing is the process of converting a signal
containing multiple analog or digital signals backs into the
original and separate signals. A demultiplexer of 2^n outputs
has n select lines.

1:4 DEMULTIPLEXER
The 1:4 demultiplexer consists of one input, four outputs, and
two control lines to make selections The below diagram shows
the circuit of 1:4 demultiplexer.

VLSI Lab Manual Page 71

The input bit is Data D with two select lines A and B. The input
bit D is transmitted to four output bits Y0, Y1, Y2, and Y4.
When AB is 01 The upper second AND gate is enabled while
the other AND gate is disabled. Thus, only one data is
transmitted at Y1. If D is low, then Y1 is low and if D is high,
Y1 is high. The value of Y1 depends on the value of D.

If the control input changes to AB=10 all the gates are disabled
except the third AND gate from the top. Then D is transmitted
to output Y2.

The below is the truth table for the 1 to 4demultiplexer.

VLSI Lab Manual Page 72

1:8 DEMULTIPLEXER

A 1 to 8 demultiplexer consists of one input line, 8 output lines

and 3 select lines. Let the input be D, S1 and S2 are two select
lines and eight outputs from Y0 to Y7. It is also called as 3 to 8
demux because of the 3 selection lines. Below is the block
diagram of 1 to 8 demux.

The below is the truth table for 1 to 8 demultiplexer. It tells the

functionality of the demux, like, if S1S2S0=000, then the output
is seen at Y0 and so on.

VLSI Lab Manual Page 73

Using the above truth table the logic diagram of the
demultiplexer is implemented using eight AND and three NOT
gates. The different combinations of the select lines select one
AND gate at given time, such that data input will be seen at a
particular output.

A 1 to 8 demultiplexer can be implemented using two 1 to 4

demultiplexers. Implementation of large output demultiplexers
becomes complex, so smaller demux is used to implement large
demultiplexers.

VLSI Lab Manual Page 74

PROGRAMS:

1:4 DEMULTIPLEXER

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demultiplexer1_4 is
Port ( D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
I : out STD_LOGIC_VECTOR (3 downto 0));
end demultiplexer1_4;

architecture Behavioral of demultiplexer1_4 is

begin
process(D,S)
begin
I <= "0000";
case S is

VLSI Lab Manual Page 75

 when"00" => I(0) <= D;
when"01" => I(1) <= D;
when"10" => I(2) <= D;
when others => I(3) <= D;
end case;
end process;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demultiplexer1_4testbench is
-- Port ( );
end demultiplexer1_4testbench;

architecture Behavioral of demultiplexer1_4testbench is

component demultiplexer1_4 is
Port( D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
I : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal D: STD_LOGIC;
signal S: STD_LOGIC_VECTOR (1 downto 0);
signal I: STD_LOGIC_VECTOR (3 downto 0);
begin
uut: demultiplexer1_4 port map(D => D,S => S,I => I);
stim: process
begin
D <= '1';
S <= "00";
wait for 100 ns;
S <= "01";
wait for 100 ns;
S <= "10";
wait for 100 ns;

VLSI Lab Manual Page 76

S <= "11";
wait for 100 ns;
wait;
end process;
end Behavioral;

1:8 DEMULTIPLEXER

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demultiplexer1_8 is
Port ( D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (2 downto 0);
I : out STD_LOGIC_VECTOR (7 downto 0));
end demultiplexer1_8;

architecture Behavioral of demultiplexer1_8 is

begin
process(D, S)
begin
case S is
when "000" => I(0) <= D;
when "001" => I(1) <= D;
when "010" => I(2) <= D;
when "011" => I(3) <= D;
when "100" => I(4) <= D;
when "101" => I(5) <= D;
when "110" => I(6) <= D;
when others => I(7) <= D;
end case;
end process;
end Behavioral;

2) VHDL TEST BENCH CODE

VLSI Lab Manual Page 77

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demultiplexer1_8testbench is
end demultiplexer1_8testbench;

architecture Behavioral of demultiplexer1_8testbench is

component demultiplexer1_8 is
Port( D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (2 downto 0);
I : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal D: STD_LOGIC;
signal S: STD_LOGIC_VECTOR (2 downto 0);
signal I: STD_LOGIC_VECTOR (7 downto 0);
begin
uut: demultiplexer1_8 port map(D => D,S => S,I => I);
stim: process
begin
D <= '1';
S <= "000";
wait for 100 ns;
S <= "001";
wait for 100 ns;
S <= "010";
wait for 100 ns;
S <= "011";
wait for 100 ns;
S <= "100";
wait for 100 ns;
S <= "101";
wait for 100 ns;
S <= "110";
wait for 100 ns;
S <= "111";
wait for 100 ns;

VLSI Lab Manual Page 78

 wait;
end process;
end Behavioral;

Observation:
1) K- map whenever required
2) Truth table whenever required
3) RTC Schematic for all
4) Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

SIMULATION RESULT:

1:4 DEMULTIPLEXER
VIVADO Schematic Diagram

VIVADO Test Bench

VLSI Lab Manual Page 79

1:8 DEMULTIPLEXER
VIVADO Schematic Diagram

VIVADO Test Bench

VLSI Lab Manual Page 80

CONCLUSION: Hence, we have analyzed 1:4 and 1:8
Demultiplexers using VHDL.

Experiment No.8

AIM:To design 4-bit ALU using VHDL.

SOFTWARE USED: Xilinx Vivado 2017.

VLSI Lab Manual Page 81
HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable
 PC

PROCEDURE:
1) Open Xilinx Vivado 2017 software to write aprogram for
4-bit ALU.
2) Declare input and output in entity.
3) Write VHDL code for 4-bit ALU in architecture.
4) Save the program and check the syntax.
5) Assign the package pins for input and output which is
mentioned inentity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

THEORY:

ALU or Arithmetic Logical Unit is a digital circuit to do

arithmetic operations like addition, subtraction,division,
multiplication and logical oparations like and, or, xor, nand, nor
etc. A simple block diagram of a 4 bit ALU for operations
and,or,xor and Add is shown here :

VLSI Lab Manual Page 82

The 4-bit ALU block is combined using 4 1-bit ALU block
The circuit functionality of a 1 bit ALU is shown here,
depending upon the control signal S1 and S0 the circuit operates
as follows:
for Control signal S1 = 0 , S0 = 0, the output is A and B,
for Control signal S1 = 0 , S0 = 1, the output is A or B,
for Control signal S1 = 1 , S0 = 0, the output is A xor B,
for Control signal S1 = 1 , S0 = 1, the output is A add B.

PROGRAMS:

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU4bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
VLSI Lab Manual Page 83
 S : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end ALU4bit;

architecture Behavioral of ALU4bit is

begin
process(A, B, S)
begin
case S is
when "000" => Y <= "0011";
when "001" => Y <= A nand B;
when "010" => Y <= A nor B;
when "011" => Y <= A xor B;
when "100" => Y<= A and B;
when "101" => Y <= A or B;
when "110" => Y <= not A ;
when others => Y <= "1111";
end case;
end process;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU4bit_testbench is
-- Port ( );
end ALU4bit_testbench;

architecture Behavioral of ALU4bit_testbench is

COMPONENT ALU4bit
PORT(
A : IN STD_LOGIC_VECTOR(3 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
S : IN std_logic_vector(2 downto 0);
Y : OUT STD_LOGIC_VECTOR(3 downto 0));

VLSI Lab Manual Page 84

END COMPONENT;
signal A : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal B : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal S : std_logic_vector(2 downto 0) := (others => '0');
signal Y : STD_LOGIC_VECTOR(3 downto 0);
BEGIN
uut: ALU4bit PORT MAP (
A => A,
B => B,
S => S,
Y => Y
);
stim_proc: process
begin
wait for 100 ns;
A <= "1001";
B <= "1111";
S <= "000";
wait for 100 ns;
S <= "001";
wait for 100 ns;
S <= "010";
wait for 100 ns;
S <= "011";
wait for 100 ns;
S <= "100";
wait for 100 ns;
S <= "101";
wait for 100 ns;
S <= "110";
wait for 100 ns;
S <= "111";
end process;
end Behavioral;

Observation:
1) K- map whenever required

VLSI Lab Manual Page 85

 2) Truth table whenever required
3) RTC Schematic for all
4) Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

SIMULATION RESULT:

VIVADO Schematic Diagram

VIVADO Test Bench

VLSI Lab Manual Page 86

CONCLUSION: Hence we have analyzed 4-bit ALU using
VHDL.

Experiment No.9

AIM:To design Flip Flops using VHDL.

A) SR Flip Flop C) D FlipFlop
B) JK Flip Flop D) T Flip Flop

SOFTWARE USED: Xilinx Vivado 2017.

HARDWARE USED: Laptop.

APPARATUS REQUIRED:
 Basys 3 Kit
 Power Cord
 Interfacing cable

VLSI Lab Manual Page 87

 PC

PROCEDURE:
1) Open Xilinx Vivado 2017 software to write aprogram for Flip
Flops.
2) Declare input and output in entity.
3) Write VHDL code for Flip Flops in architecture.
4) Save the program and check the syntax.
5) Assign the package pins for input and output which is
mentioned inentity.
6) Configuring the impact in generating programming to
download the program.
7) Write Test Bench Code for Observe the Output in software
simulation.
8) Then check the result in Basys 3 kit.

THEORY:

Flip-flops are also the building blocks of sequential circuits.

They are made using latches. They are circuits where the output
depends not only on the current input but also on the previous
inputs. They are also known as memory cells, as they can store
one bit of binary data.
In fact, flip-flops are the fundamental memory units in
electronics. Flip-flops work on the application of a clock signal.
This makes them synchronous. A flip-flop has two inputs and
two outputs. The outputs (Q and Q’) are complements of each
other.
Just like a latch, a flip-flop is a bistable multivibrator too. It has
two stable states. When Q = 1; Q’ = 0, the flip is said to be in a
set state. When Q = 0;Q’ = 1, it is said to be in a reset state.

VLSI Lab Manual Page 88

Basic digital circuits like shift registers and counters are made
using flip-flops. So are complex devices like FPGAs, CPLDs,
and RAMs.

A) SR Flip-Flop

The circuit above shows an SR flip-flop with two inputs and two
outputs. The outputs are complementary to each other. The SR
in SR flip-flop stands for Set-Reset.

Characteristics Equation
Q(next) = S + R'Q

Truth table for SR flip-flop

VLSI Lab Manual Page 89

B) JK Flip-Flop

The JK flip-flop removes the not allowed condition that occurs

when both inputs are high in an SR flip-flop. Additionally,
the Master-Slave configuration of the JK flip-flop also removes
the race-around-condition.
The race around condition is when a normal JK flip-flop gets
stuck in a toggling loop for every clock pulse change when both

VLSI Lab Manual Page 90

the inputs are high. The Master-slave configuration ends that
loop and stabilizes the output.

Characteristics Equation
Q(next) = JQ' + K'Q

Truth table for JK flip-flop

C) D Flip-Flop

The circuit above shows a D flip-flop using an SR latch. The D

flip-flop has one input and two outputs. The outputs are
complementary to each other. The D in D flip-flop stands for
Data or Delay.
Regardless, the circuit’s structural aspect is only necessary to
figure out the I/O ports. In behavioral architecture, what’s
VLSI Lab Manual Page 91
necessary is the behavior of the circuit. The way the circuit
responds to a certain set of inputs. This is given by the truth
table.

Characteristics Equation
Q(next) = D

Truth table for D flip-flop

D) T Flip-Flop

The T in T flip-flop stands for ‘toggle’. This is because a T

flip-flop toggles (changes) its value whenever the input is high.
When the input is low, the output remains the same as the
previous output. A T flip-flop can be made using an SR latch, as
VLSI Lab Manual Page 92
shown above. Or it can be made using a JK flip-flop as shown
below.

Truth table for T flip-flop

PROGRAMS:

A) SR Flip-Flop

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_FLIPFLOP_1 is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
RST : in STD_LOGIC;

VLSI Lab Manual Page 93

 CLK : in STD_LOGIC;
Q : out STD_LOGIC;
Qb : out STD_LOGIC);
end SR_FLIPFLOP_1;

architecture Behavioral of SR_FLIPFLOP_1 is

begin
process (S,R,RST,CLK)
begin
if (RST = '1') then
Q <= '0';
elsif (RISING_EDGE(CLK))then
if (S /= R) then
Q <= S;
Qb <= R;
elsif (S = '1' AND R = '1') then
Q <= 'Z';
Qb <= 'Z';
end if;
end if;
end process;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_FLIPFLOP_1Testbench is
end SR_FLIPFLOP_1Testbench;

architecture Behavioral of SR_FLIPFLOP_1Testbench is

component SR_FLIPFLOP_1 is
Port ( S,R,RST,CLK : in STD_LOGIC;
Q,Qb : out STD_LOGIC);
end component;

VLSI Lab Manual Page 94

signal S, R, RST, CLK, Q, Qb : STD_LOGIC;
begin
uut: SR_FLIPFLOP_1 port map(
S => S,
R => R,
RST => RST,
CLK => CLK,
Q => Q,
Qb => Qb);
Clock : process
begin
CLK <= '0';
wait for 30 ns;
CLK <= '1';
wait for 30 ns;
end process;
Stim : process
begin
RST <= '0';
S <= '0';
R <= '0';
wait for 100 ns;
S <= '0';
R <= '1';
wait for 100 ns;
S <= '1';
R <= '0';
wait for 100 ns;
S <= '1';
R <= '1';
wait for 100 ns;
end process;
end Behavioral;

B) JK Flip-Flop

1) VHDL CODE

VLSI Lab Manual Page 95

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JK_FLIPFLOP_1 is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC;
Qbar : out STD_LOGIC);
end JK_FLIPFLOP_1;

architecture Behavioral of JK_FLIPFLOP_1 is

Signal qn : std_logic;
begin
process(clk, rst)
begin
if(rst = '1')then
qn <= '0';
elsif(clk'event and clk = '1')then
if(J='0' and K='0')then
qn <= qn;
elsif(J='0' and K='1')then
qn <= '0';
elsif(J='1' and K='0')then
qn <= '1';
elsif(J='1' and K='1')then
qn <= not qn;
else
null;
end if;
else
null;
end if;
Q <= qn;
Qbar <= not qn;

VLSI Lab Manual Page 96

end process;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JK_FLIPFLOP_1Testbench is
end JK_FLIPFLOP_1Testbench;

architecture Behavioral of JK_FLIPFLOP_1Testbench is

component JK_FLIPFLOP_1 is
port(J, K, clk, rst : in std_logic;
Q, Qbar : out std_logic
);
end component;
signal J, K, clk, rst : std_logic;
signal Q, Qbar : std_logic;
begin
uut: JK_FLIPFLOP_1 port map(
J => J,
K => K,
clk => clk,
rst => rst,
Q => Q,
Qbar => Qbar);
clock: process
begin
clk <= '1';
wait for 30 ns;
clk <= '0';
wait for 30 ns;
end process;
Force: process
begin
J <= '0';

VLSI Lab Manual Page 97

K <= '0';
rst <= '0';
wait for 100 ns;
J <= '0';
K <= '1';
rst <= '0';
wait for 100 ns;
J <= '1';
K <= '0';
rst <= '0';
wait for 100 ns;
J <= '1';
K <= '1';
rst <= '0';
wait for 100 ns;
J <= '1';
K <= '1';
rst <= '0';
wait for 100 ns;
J <= '0';
K <= '0';
rst <= '0';
wait for 100 ns;
J <= '0';
K <= '0';
rst <= '1';
wait for 100 ns;
end process;
end Behavioral;

C) D Flip-Flop

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

VLSI Lab Manual Page 98

entity D_FLIPFLOP_1 is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC;
Qb : out STD_LOGIC);
end D_FLIPFLOP_1;

architecture Behavioral of D_FLIPFLOP_1 is

begin
process (D, CLK, RST)
begin
if (RST = '1') then
Q <= '0';
elsif (rising_edge(CLK)) then
Q <= D;
Qb <= not D;
end if;
end process;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FLIPFLOP_1Testbench is
end D_FLIPFLOP_1Testbench;

architecture Behavioral of D_FLIPFLOP_1Testbench is

component D_FLIPFLOP_1 is
Port ( D, CLK, RST : in STD_LOGIC;
Q, Qb : out STD_LOGIC);
end component ;

signal D, CLK, RST, Q, Qb : STD_LOGIC;

VLSI Lab Manual Page 99

begin
uut: D_FLIPFLOP_1 port map(
D => D,
CLK => CLK,
RST => RST,
Q => Q,
Qb => Qb);

Clock : process
begin
CLK <= '0';
wait for 10 ns;
CLK <= '1';
wait for 10 ns;
end process;
stim : process
begin
RST <= '0';
D <= '0';
wait for 40 ns;
D <= '1';
wait for 40 ns;
end process;
end Behavioral;

D) T Flip-Flop

1) VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity T_FLIPFLOP_1 is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;

VLSI Lab Manual Page 100

 RES : in STD_LOGIC;
Q : out STD_LOGIC;
Qb : out STD_LOGIC);
end T_FLIPFLOP_1;

architecture Behavioral of T_FLIPFLOP_1 is

SIGNAL TEMP:STD_LOGIC:='0';
begin
process(T,CLK,RES)
begin
if(RES='1') then
TEMP <= '0';
elsif(RISING_EDGE(CLK)) then
if(T='1') then
TEMP <= NOT TEMP;
end if;
end if;
Q <= NOT TEMP;
Qb <= TEMP;
End process;
end Behavioral;

2) VHDL TEST BENCH CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity T_FLIPFLOP_1Testbench is
end T_FLIPFLOP_1Testbench;

architecture Behavioral of T_FLIPFLOP_1Testbench is

component T_FLIPFLOP_1 is
Port ( T,CLK,RES : in STD_LOGIC;
Q,Qb : out STD_LOGIC);

VLSI Lab Manual Page 101

end component;
signal T,CLK,RES,Q,Qb : STD_LOGIC;
begin
uut: T_FLIPFLOP_1 port map(
T => T,
CLK => CLK,
RES => RES,
Q => Q,
QB => Qb);
clock : process
begin
CLK <= '0';
wait for 50 ns;
CLK <= '1';
wait for 50 ns;
end process;
stim: process
begin
RES <= '0';
T <= '0';
wait for 100 ns;
T <= '1';
wait for 100 ns;
end process;
end Behavioral;

Observation:
1) K- map whenever required
2) Truth table whenever required
3) RTC Schematic for all
4) Technological Schematic for all
5) Test Bench output for all
6) Screen Shot for Basys 3 Kit FPGA Board

SIMULATION RESULT:

VLSI Lab Manual Page 102

 A) SR FLIP-FLOP

VIVADO Schematic Diagram

VIVADO Test Bench

B) JK FLIP-FLOP

VIVADO Schematic Diagram

VLSI Lab Manual Page 103

VIVADO Test Bench

C) D FLIP-FLOP

VLSI Lab Manual Page 104

VIVADO Schematic Diagram

VIVADO Test Bench

D) T FLIP-FLOP

VIVADO Schematic Diagram

VLSI Lab Manual Page 105

VIVADO Test Bench

CONCLUSION: Hence, we have analyzed Flip-Flops using

VHDL.

VLSI Lab Manual Page 106