LTC1608

High Speed, 16-Bit, 500ksps

Sampling A/D Converter
with Shutdown
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FEATURES DESCRIPTIO
■ A Complete, 500ksps 16-Bit ADC The LTC®1608 is a 500ksps, 16-bit sampling A/D con-
■ 90dB S/(N+D) and –100dB THD (Typ) verter that draws only 270mW from ±5V supplies. This
■ Power Dissipation: 270mW (Typ) high performance device includes a high dynamic range
■ No Pipeline Delay sample-and-hold, a precision reference and a high speed
■ No Missing Codes Over Temperature parallel output. Two digitally selectable power shutdown
■ Nap (7mW) and Sleep (10µW) Shutdown Modes modes provide power savings for low power systems.
■ Operates with Internal 15ppm/°C Reference
The LTC1608’s full-scale input range is ± 2.5V. Outstand-
or External Reference
ing AC performance includes 90dB S/(N+D) and – 100dB
■ True Differential Inputs Reject Common Mode Noise
THD at a sample rate of 500ksps.
■ 5MHz Full Power Bandwidth
■ ±2.5V Bipolar Input Range The unique differential input sample-and-hold can acquire
■ 36-Pin SSOP Package single-ended or differential input signals up to its 15MHz
■ Pin Compatible with the LTC1604 bandwidth. The 68dB common mode rejection allows
U users to eliminate ground loops and common mode noise
APPLICATIO S by measuring signals differentially from the source.
■ Telecommunications The ADC has µP compatible,16-bit parallel output port.
■ Digital Signal Processing There is no pipeline delay in conversion results. A separate
■ Multiplexed Data Acquisition Systems convert start input and a data ready signal (BUSY) ease
■ High Speed Data Acquisition connections to FlFOs, DSPs and microprocessors.
■ Spectrum Analysis , LTC and LT are registered trademarks of Linear Technology Corporation.
■ Imaging Systems Circuitry in the LTC1608 is covered under US Patent #5,764,175

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TYPICAL APPLICATIO
2.2µF 10µF 5V 10µF 5V 10µF
10Ω
+ + +
3 36 35 9 10
VREF AVDD AVDD DVDD DGND LTC1608 4096 Point FFT
SHDN 33 0
fSAMPLE = 500kHz
LTC1608 CS 32
CONTROL fIN = 98.754kHz
µP –20 SINAD = 86.7dB
LOGIC CONVST 31
CONTROL THD = –92.6dB
4 REFCOMP 7.5k
2.5V AND
RD 30
1.75X TIMING LINES –40
+ REF
AMPLITUDE (dB)

BUSY 27
22µF
–60
OVDD 29 5V OR
+ 3V
–80
+ OGND 28 10µF
1 AIN
DIFFERENTIAL + –100
16-BIT OUTPUT
ANALOG INPUT – SAMPLING B15 TO B0 16-BIT
2 AIN BUFFERS
± 2.5V D15 TO D0 PARALLEL
– ADC
BUS
–120

11 TO 26 –140
AGND AGND AGND AGND VSS
1608 TA01 0 50 100 150 200 250
5 6 7 8 34 FREQUENCY (kHz)
10µF 1608 TA02

+
–5V

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LTC1608
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ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
AVDD = DVDD = OVDD = VDD (Notes 1, 2)
TOP VIEW ORDER
Supply Voltage (VDD) ................................................ 6V AIN+ 1 36 AVDD PART NUMBER
Negative Supply Voltage (VSS) ............................... – 6V AIN– 2 35 AVDD
VREF 3 34 VSS
Total Supply Voltage (VDD to VSS) .......................... 12V REFCOMP 4 33 SHDN
LTC1608CG
Analog Input Voltage AGND 5 32 CS LTC1608ACG
AGND 6 31 CONV
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) AGND 7 30 RD
LTC1608IG
VREF Voltage (Note 4) ................. – 0.3V to (VDD + 0.3V) AGND 8 29 OVDD LTC1608AIG
REFCOMP Voltage (Note 4) ......... – 0.3V to (VDD + 0.3V) DVDD 9 28 OGND
DGND 10 27 BUSY
Digital Input Voltage (Note 4) ....................– 0.3V to 10V D15 (MSB) 11 26 D0
Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) D14 12 25 D1
D13 13 24 D2
Power Dissipation ............................................. 500mW D12 14 23 D3
Operating Temperature Range D11 15 22 D4

LTC1608C .............................................. 0°C to 70°C D10 16

D9 17
21 D5
20 D6
LTC1608I ............................................ – 40°C to 85°C D8 18 19 D7
Storage Temperature Range ................ – 65°C to 150°C G PACKAGE
36-LEAD PLASTIC SSOP
Lead Temperature (Soldering, 10 sec)................. 300°C TJMAX = 125°C, θJA = 95°C/W

Consult factory for parts specified with wider operating temperature ranges.

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CO VERTER CHARACTERISTICS The ● denotes specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6), unless otherwise noted.
LTC1608 LTC1608A
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) ● 15 16 16 16 Bits
Integral Linearity Error (Note 7) ● ±1 ±4 ±0.5 ±2 LSB
Transition Noise (Note 8) 0.7 0.7 LSBRMS
Offset Error (Note 9) ● ± 0.05 ± 0.125 ±0.05 ±0.125 % FSR
Offset Tempco (Note 9) 0.5 0.5 ppm/°C
Full-Scale Error Internal Reference ± 0.125 ± 0.25 ±0.125 ±0.25 %
External Reference ±0.25 ±0.25 %
Full-Scale Tempco IOUT(Reference) = 0, Internal Reference ±15 ±15 ppm/°C
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A ALOG I PUT The ● denotes specifications that apply over the full operating temperature range, otherwise
specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (Note 2) 4.75 ≤ VDD ≤ 5.25V, – 5.25 ≤ VSS ≤ – 4.75V, ±2.5 V
VSS ≤ (AIN–, AIN+) ≤ AVDD
IIN Analog Input Leakage Current CS = High ● ±1 µA
CIN Analog Input Capacitance Between Conversions 43 pF
During Conversions 5 pF
tACQ Sample-and-Hold Acquisition Time 380 ns
tAP Sample-and-Hold Acquisition Delay Time – 1.5 ns
tjitter Sample-and-Hold Acquisition Delay Time Jitter 5 psRMS
CMRR Analog Input Common Mode Rejection Ratio – 2.5V < (AIN– = AIN +) < 2.5V 68 dB

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 LTC1608
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DY A IC ACCURACY TA = 25°C (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/N Signal-to-Noise Ratio 5kHz Input Signal 90 dB
100kHz Input Signal 88 dB
S/(N + D) Signal-to-(Noise + Distortion) Ratio 5kHz Input Signal 90 dB
100kHz Input Signal (Note 10) 84 dB
THD Total Harmonic Distortion 5kHz Input Signal – 100 dB
Up to 5th Harmonic 100kHz Input Signal – 91 dB
SFDR Spurious Free Dynamic Range 100kHz Input Signal 94 dB
IMD Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.446kHz – 88 dB
Full Power Bandwidth 5 MHz
Full Linear Bandwidth (S/(N + D) ≥ 84dB) 350 kHz

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I TER AL REFERE CE CHARACTERISTICS TA = 25°C (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 2.475 2.500 2.515 V
VREF Output Tempco IOUT = 0 ±15 ppm/°C
VREF Line Regulation 4.75 ≤ VDD ≤ 5.25V 0.01 LSB/V
– 5.25V ≤ VSS ≤ – 4.75V 0.01 LSB/V
VREF Output Resistance 0 ≤ IOUT ≤ 1mA 7.5 kΩ
REFCOMP Output Voltage IOUT = 0 4.375 V

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DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications that apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 5.25V ● 2.4 V
VIL Low Level Input Voltage VDD = 4.75V ● 0.8 V
IIN Digital Input Current VIN = 0V to VDD ● ±1 0 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage VDD = 4.75V, IOUT = – 10µA 4.5 V
VDD = 4.75V, IOUT = – 400µA ● 4.0 V
VOL Low Level Output Voltage VDD = 4.75V, IOUT = 160µA 0.05 V
VDD = 4.75V, IOUT = 1.6mA ● 0.10 0.4 V
IOZ Hi-Z Output Leakage D15 to D0 VOUT = 0V to VDD, CS High ● ±10 µA
COZ Hi-Z Output Capacitance D15 to D0 CS High (Note 11) ● 15 pF
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = VDD 10 mA

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LTC1608
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POWER REQUIRE E TS The ● denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage (Notes 12, 13) 4.75 5.25 V
VSS Negative Supply Voltage (Note 12) – 4.75 – 5.25 V
IDD Positive Supply Current CS = RD = 0V ● 22 35 mA
Nap Mode CS = 0V, SHDN = 0V 1.5 2.4 mA
Sleep Mode CS = 5V, SHDN = 0V 1 100 µA
ISS Negative Supply Current CS = RD = 0V ● 32 49 mA
Nap Mode CS = 0V, SHDN = 0V 1 100 µA
Sleep Mode CS = 5V, SHDN = 0V 1 100 µA
PD Power Dissipation CS = RD = 0V ● 270 420 mW
Nap Mode CS = 0V, SHDN = 0V 7.5 12 mW
Sleep Mode CS = 5V, SHDN = 0V 0.01 1 mW

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TI I G CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency ● 500 600 kHz
tCONV Conversion Time ● 1.0 1.45 1.8 µs
tACQ Acquisition Time (Notes 11, 14) ● 400 ns
tACQ+CONV(MIN) Throughput Time (Acquisition + Conversion) ● 1.67 2 µs
t1 CS to RD Setup Time (Notes 11, 12, 15) ● 0 ns
t2 CS↓ to CONVST↓ Setup Time (Notes 11, 12) ● 10 ns
t3 SHDN↓ to CS↑ Setup Time (Notes 11, 12) ● 10 ns
t4 SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) 400 ns
t5 CONVST Low Time (Note 12) ● 40 ns
t6 CONVST to BUSY Delay CL = 25pF 36 ns
● 80 ns
t7 Data Ready Before BUSY↑ 60 ns
● 32 ns
t8 Delay Between Conversions (Note 12) ● 200 ns
t9 Wait Time RD↓ After BUSY↑ (Note 12) ● –5 ns
t10 Data Access Time After RD↓ CL = 25pF 25 40 ns
● 50 ns
CL = 100pF (Note 11) 45 60 ns
● 75 ns
t11 Bus Relinquish Time 30 50 ns
● 60 ns
t12 RD Low Time (Note 12) ● t10 ns
t13 CONVST High Time (Note 12) ● 40 ns
t14 Aperture Delay of Sample-and-Hold 2 ns

Note 1: Absolute Maximum Ratings are those values beyond which the life Note 3: When these pin voltages are taken below VSS or above VDD, they
of a device may be impaired. will be clamped by internal diodes. This product can handle input currents
Note 2: All voltage values are with respect to ground with DGND, OGND greater than 100mA below VSS or above VDD without latchup.
and AGND wired together unless otherwise noted.

4
 LTC1608
ELECTRICAL CHARACTERISTICS
Note 4: When these pin voltages are taken below VSS, they will be clamped Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
by internal diodes. This product can handle input currents greater than is measured at 100kHz. These results are used to calculate Signal-to-Nosie
100mA below VSS without latchup. These pins are not clamped to VDD. Plus Distortion (SINAD).
Note 5: VDD = 5V, VSS = – 5V, fSMPL = 500kHz, and t r = t f = 5ns unless Note 11: Guaranteed by design, not subject to test.
otherwise specified. Note 12: Recommended operating conditions.
Note 6: Linearity, offset and full-scale specification apply for a single- Note 13: The falling CONVST edge starts a conversion. If CONVST returns
ended AIN+ input with AIN– grounded. high at a critical point during the conversion it can create small errors. For
Note 7: Integral nonlinearity is defined as the deviation of a code from a best performance ensure that CONVST returns high either within 250ns
straight line passing through the actual endpoints of the transfer curve. after conversion start or after BUSY rises.
The deviation is measured from the center of the quantization band. Note 14: The acquisition time would go up to 400ns and the conversion
Note 8: Typical RMS noise at the code transitions. time would go up to 1.8µs. However, the throughput time (acquisition +
Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when conversion) is guaranteed by test to be 2µs max.
the output code flickers between 0000 0000 0000 0000 and 1111 1111 Note 15: If RD↓ precedes CS↓, the output enable will be gated by CS↓.
1111 1111.

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TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity Differential Nonlinearity S/(N + D) vs Input Frequency
vs Output Code vs Output Code and Amplitude
2.0 1.0 100
VIN = 0dB
0.8 90
1.5
0.6 80
1.0 VIN = –20dB
0.4 70
0.5
SINAD (dB)
0.2 60
DNL (LSB)
INL (LSB)

VIN = –40dB
0 0 50
–0.2 40
–0.5
–0.4 30
–1.0
–0.6 20
–1.5 –0.8 10
–2.0 –1.0 0
–32768 –16384 0 16384 32767 –32768 –16384 0 16384 32767 1k 10k 100k 1M
CODE CODE FREQUENCY (Hz)
1608 G01 1608 G02 1608 G03

Signal-to-Noise Ratio Spurious-Free Dynamic Range

vs Input Frequency Distortion vs Input Frequency vs Input Frequency
100 0 0
AMPLITUDE (dB BELOW THE FUNDAMENTAL)

SPURIOUS-FREE DYNAMIC RANGE (dB)

90 –10 –10
–20 –20
SIGNAL-TO-NOISE RATIO (dB)

80
70 –30 –30
–40 –40
60
–50 –50
50
–60 –60
40
–70 –70
30
–80 THD –80
20 3RD
–90 2ND –90
10 –100 –100
0 –110 –110
1k 10k 100k 1M 1k 10k 100k 1M 1k 10k 100k 1M
FREQUENCY (Hz) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz)
1608 G04 1608 G05 1608 G06

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LTC1608
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TYPICAL PERFOR A CE CHARACTERISTICS
Power Supply Feedthrough Input Common Mode Rejection
Intermodulation Distortion vs Ripple Frequency vs Input Frequency
0 0 80
fSAMPLE = 500kHz fSAMPLE = 500kHz
fIN1 = 96.56kHz VRIPPLE = 10mV 70
–20 –20

COMMON MODE REJECTION (dB)

AMPLITUDE OF POWER SUPPLY
fIN2 = 99.98kHz
60
–40 –40

FEEDTHROUGH (dB)
AMPLITUDE (dB)

50
–60 –60
40
–80 –80
30
–100 –100
20
AVDD
–120 –120 V SS
10

–140 –140 0
0 50 100 150 200 250 1k 10k 100k 1M 1k 10k 100k 1M
FREQUENCY (kHz) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz)
1608 G07 1608 G08 1608 G14a

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PI FU CTIO S
AIN+ (Pin 1): Positive Analog Input. The ADC converts the OGND (Pin 28): Digital Ground for Output Drivers.
difference voltage between AIN+ and AIN– with a differen-
OVDD (Pin 29): Digital Power Supply for Output Drivers.
tial range of ±2.5V. AIN+ has a ±2.5V input range when
Bypass to OGND with 10µF tantalum in parallel with 0.1µF
AIN– is grounded.
ceramic.
AIN– (Pin 2): Negative Analog Input. Can be grounded, tied
RD (Pin 30): Read Input. A logic low enables the output
to a DC voltage or driven differentially with AIN+ .
drivers when CS is low.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with
CONVST (Pin 31): Conversion Start Signal. This active
2.2µF tantalum in parallel with 0.1µF ceramic.
low signal starts a conversion on its falling edge when CS
REFCOMP (Pin 4): 4.375V (Nominal) Reference Compen- is low.
sation Pin. Bypass to AGND with 22µF tantalum in parallel
CS (Pin 32): The Chip Select Input. Must be low for the ADC
with 0.1µF ceramic. This is not recommended for use as
to recognize CONVST and RD inputs.
an external reference due to part-to-part output voltage
variations and glitches that occur during the conversion. SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground
sleep mode.
plane.
VSS (Pin 34): – 5V Negative Supply. Bypass to AGND with
DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND
10µF tantalum in parallel with 0.1µF ceramic.
with 10µF tantalum in parallel with 0.1µF ceramic.
AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND
DGND (Pin 10): Digital Ground for Internal Logic. Tie to
with 10µF tantalum in parallel with 0.1µF ceramic.
analog ground plane.
AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND
D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
with 10µF tantalum in parallel with 0.1µF ceramic and
is the Most Significant Bit.
connect this pin to Pin 35 with a 10Ω resistor.
BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.

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 LTC1608
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FU CTIO AL BLOCK DIAGRA
2.2µF 10µF 5V 10µF 5V 10µF
10Ω
+ + +
3 36 35 9 10
VREF AVDD AVDD DVDD DGND
SHDN 33
CS 32
CONTROL
LOGIC CONVST 31 µP
CONTROL
4 REFCOMP 7.5k
2.5V AND
RD 30 LINES
1.75X TIMING
+ 4.375V REF
BUSY 27
22µF
OVDD 29 5V OR
+ 3V
OGND 28 10µF
1 AIN+
DIFFERENTIAL +
16-BIT OUTPUT
ANALOG INPUT SAMPLING B15 TO B0 16-BIT
±2.5V 2 AIN– BUFFERS
D15 TO D0 PARALLEL
– ADC
BUS
11 TO 26
AGND AGND AGND AGND VSS
5 6 7 8 34 1608 BD

10µF
+
–5V

TEST CIRCUITS
Load Circuits for Access Timing Load Circuits for Output Float Delay

5V 5V

1k 1k

DN DN DN DN

1k CL CL 1k CL CL

(A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z
1608 TC01 1608 TC02

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APPLICATIO S I FOR ATIO
CONVERSION DETAILS During the conversion, the internal differential 16-bit
The LTC1608 uses a successive approximation algorithm capacitive DAC output is sequenced by the SAR from the
and internal sample-and-hold circuit to convert an analog Most Significant Bit (MSB) to the Least Significant Bit
signal to a 16-bit parallel output. The ADC is complete with (LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
a sample-and-hold, a precision reference and an internal acquired during the acquire phase and the comparator
clock. The control logic provides easy interface to micro- offset is nulled by the zeroing switches. In this acquire
processors and DSPs. (Please refer to the Digital Interface phase, a duration of 480ns will provide enough time for the
section for the data format.) sample-and-hold capacitors to acquire the analog signal.
During the convert phase, the comparator zeroing switches
Conversion start is controlled by the CS and CONVST open, putting the comparator into compare mode. The
inputs. At the start of the conversion, the successive input switches connect the CSMPL capacitors to ground,
approximation register (SAR) resets. Once a conversion transferring the differential analog input charge onto the
cycle has begun, it cannot be restarted. summing junctions. This input charge is successively

7
LTC1608
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APPLICATIO S I FOR ATIO
CSMPL 3V Input/Output Compatible
SAMPLE
AIN+ The LTC1608 operates on ±5V supplies, which makes the
HOLD
device easy to interface to 5V digital systems. This device
CSMPL
ZEROING SWITCHES can also talk to 3V digital systems: the digital input pins
HOLD
AIN–
SAMPLE (SHDN, CS, CONVST and RD) of the LTC1608 recognize
HOLD 3V or 5V inputs. The LTC1608 has a dedicated output
HOLD
supply pin (OVDD) that controls the output swings of the
+CDAC digital output pins (D0 to D15, BUSY) and allows the part
+ to talk to either 3V or 5V digital systems. The output is
–CDAC COMP
two’s complement binary.
+VDAC –
Power Shutdown
–VDAC
16 D15
The LTC1608 provides two power shutdown modes, Nap
OUTPUT •
SAR
LATCHES
•
• and Sleep, to save power during inactive periods. The Nap
D0
mode reduces the power by 95% and leaves only the
1608 F01
digital logic and reference powered up. The wake-up time
Figure 1. Simplified Block Diagram from Nap to active is 200ns. In Sleep mode, all bias
currents are shut down and only leakage current remains
(about 1µA). Wake-up time from Sleep mode is much
compared with the binary-weighted charges supplied by
longer since the reference circuit must power up and
the differential capacitive DAC. Bit decisions are made by
settle. Sleep mode wake-up time is dependent on the
the high speed comparator. At the end of a conversion, the
value of the capacitor connected to the REFCOMP (Pin 4).
differential DAC output balances the AIN+ and AIN– input
The wake-up time is 80ms with the recommended 22µF
charges. The SAR contents (a 16-bit data word) which
capacitor.
represent the difference of AIN+ and AIN– are loaded into
the 16-bit output latches. Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
DIGITAL INTERFACE selected with Pin 32 (CS). When SHDN is low, CS low
The A/D converter is designed to interface with micropro- selects nap and CS high selects sleep.
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory SHDN

interfacing. A separate CONVST is used to initiate a con- t3

version. CS
1608 F02a

Internal Clock
The A/D converter has an internal clock that runs the A/D Figure 2a. Nap Mode to Sleep Mode Timing
conversion. The internal clock is factory trimmed to achieve
a typical conversion time of 1.45µs and a maximum SHDN
conversion time of 1.8µs over the full temperature range.
t4
No external adjustments are required. The guaranteed
maximum acquisition time is 400ns. In addition, a through- CONVST
1608 F02b

put time (acquisition + conversion) of 2µs and a minimum

sampling rate of 500ksps are guaranteed.
Figure 2b. SHDN to CONVST Wake-Up Timing

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 LTC1608
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APPLICATIO S I FOR ATIO
CS (e.g., CONVST low time >tCONV), accuracy is unaffected.
For best results, keep t 5 less than 500ns or greater than
t2
tCONV.
CONVST
Figures 5 through 9 show several different modes of
t1
operation. In modes 1a and 1b (Figures 5 and 6), CS and
RD RD are both tied low. The falling edge of CONVST starts the
1608 F03 conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
Figure 3. CS top CONVST Setup Timing operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
4
In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are in
3
CHANGE IN DNL (LSB)

three-state until read by the MPU with the RD signal. Mode

2 can be used for operation with a shared data bus.
2
tCONV tACQ In slow memory and ROM modes (Figures 8 and 9), CS is
tied low and CONVST and RD are tied together. The MPU
1
starts the conversion and reads the output with the com-
bined CONVST-RD signal. Conversions are started by the
0 MPU or DSP (no external sample clock is needed).
0 250 500 750 1000 1250 1500 1750 2000
CONVST LOW TIME, t5 (ns)
1608 F04
In slow memory mode, the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
low, forcing the processor into a wait state. The previous
the End of Conversion conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
Timing and Control appear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (= CONVST) back
Conversion start and data read operations are controlled high and reads the new conversion data.
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the In ROM mode, the processor takes RD (= CONVST) low,
ADC has been selected (i.e., CS is low). Once initiated, it starting a conversion and reading the previous conversion
cannot be restarted until the conversion is complete. result. After the conversion is complete, the processor can
Converter status is indicated by the BUSY output. BUSY is read the new result and initiate another conversion.
low during a conversion.
DIFFERENTIAL ANALOG INPUTS
We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in Driving the Analog Inputs
Figures 5 and 6. A narrow low or high CONVST pulse
The differential analog inputs of the LTC1608 are easy to
prevents the rising edge of the CONVST pulse from upset-
drive. The inputs may be driven differentially or as a single-
ting the critical bit decisions during the conversion time.
ended input (i.e., the AIN – input is grounded). The AIN+ and
Figure 4 shows the change of the differential nonlinearity
AIN – inputs are sampled at the same instant. Any un-
error versus the low time of the CONVST pulse. As shown,
wanted signal that is common mode to both inputs will be
if CONVST returns high early in the conversion (e.g.,
reduced by the common mode rejection of the sample-
CONVST low time <300ns), accuracy is unaffected. Simi-
and-hold circuit. The inputs draw only one small current
larly, if CONVST returns high after the conversion is over

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LTC1608
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APPLICATIO S I FOR ATIO
CS = RD = 0 t CONV

t5

CONVST

t6 t8

BUSY

t7
DATA (N – 1) DATA N DATA (N + 1)
DATA D15 TO D0 D15 TO D0
D15 TO D0
1608 F05

Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )

CS = RD = 0 tCONV t8
t13 t5

CONVST

t6 t6

BUSY

t7
DATA (N – 1) DATA N DATA (N + 1)
DATA
D15 TO D0 D15 TO D0 D15 TO D0
1608 F06

Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )

t13
CS = 0 tCONV t8
t5

CONVST

t6

BUSY

t9 t 11
t 12
RD

t 10
DATA N
DATA
D15 TO D0
1608 F07

Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD

10
 LTC1608
U U W U
APPLICATIO S I FOR ATIO
CS = 0 t CONV t8

RD = CONVST

t6 t 11

BUSY

t 10 t7
DATA (N – 1) DATA N DATA N DATA (N + 1)
DATA
D15 TO D0 D15 TO D0 D15 TO D0 D15 TO D0
1608 F08

Figure 8. Mode 2. Slow Memory Mode Timing

CS = 0 t CONV t8

RD = CONVST

t6 t 11

BUSY

t 10
DATA (N – 1) DATA N
DATA
D15 TO D0 D15 TO D0 1608 F09

Figure 9. ROM Mode Timing

10
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
ACQUISITION TIME (µs)

impedance of the driving circuit is low, then the LTC1608 1

inputs can be driven directly. As source impedance in-

creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a 0.1

buffer amplifier should be used. The only requirement is

that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion 0.01
1 10 100 1k 10k
starts (settling time must be 200ns for full throughput SOURCE RESISTANCE (Ω)
rate). 1608 F10

Choosing an Input Amplifier Figure 10. tACQ vs Source Resistance

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude the output impedance at 50MHz should be less than
of the voltage spike seen by the amplifier from charging 100Ω. The second requirement is that the closed-loop
the sampling capacitor, choose an amplifier that has a bandwidth must be greater than 15MHz to ensure
low output impedance (< 100Ω) at the closed-loop band- adequate small-signal settling for full throughput rate. If
width frequency. For example, if an amplifier is used in a slower op amps are used, more settling time can be
gain of +1 and has a unity-gain bandwidth of 50MHz, then provided by increasing the time between conversions.

11
LTC1608
U U W U
APPLICATIO S I FOR ATIO
The best choice for an op amp to drive the LTC1608 will minimize noise. A simple 1-pole RC filter is sufficient for
depend on the application. Generally applications fall into many applications. For example, Figure 11 shows a 3000pF
two categories: AC applications where dynamic specifi- capacitor from AIN+ to ground and a 100Ω source resistor
cations are most critical and time domain applications to limit the input bandwidth to 530kHz. The 3000pF
where DC accuracy and settling time are most critical. capacitor also acts as a charge reservoir for the input
The following list is a summary of the op amps that are sample-and-hold and isolates the ADC input from sam-
suitable for driving the LTC1608. More detailed informa- pling glitch sensitive circuitry. High quality capacitors and
tion is available in the Linear Technology databooks, the resistors should be used since these components can add
LinearViewTM CD-ROM and on our web site at: distortion. NPO and silver mica type dielectric capacitors
www.linear-tech. com. have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
LT ® 1007: Low Noise Precision Amplifier. 2.7mA supply
current, ±5V to ±15V supplies, gain bandwidth product that may occur during soldering. Metal film surface mount
8MHz, DC applications. resistors are much less susceptible to both problems.

LT1097: Low Cost, Low Power Precision Amplifier. 300µA ANALOG INPUT
100Ω 1
AIN+
supply current, ±5V to ±15V supplies, gain bandwidth 3000pF
2
product 0.7MHz, DC applications. AIN–
LTC1608
LT1227: 140MHz Video Current Feedback Amplifier. 10mA 3
VREF
supply current, ±5V to ±15V supplies, low noise and low
4
distortion. REFCOMP
22µF
LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA sup- 5
AGND
ply current, ±5V to ±15V supplies, good AC/DC specs.
1608 F11

LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA sup-

ply current, good AC/DC specs. Figure 11. RC Input Filter

LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback Input Range

Amplifiers. 6.3mA supply current per amplifier, good The ±2.5V input range of the LTC1608 is optimized for low
AC/DC specs. noise and low distortion. Most op amps also perform well
LT1468: 90MHz, 22V/µs 16-Bit Accurate Operational over this same range, allowing direct coupling to the
Amplifier. 3.8mA supply current, excellent DC specs and analog inputs and eliminating the need for special transla-
very low distortion performance to 100kHz. tion circuitry.
LT1469: Dual 90MHz, 22V/µs 16-Bit Accurate Operational Some applications may require other input ranges. The
Amplifier. 4.1mA supply current, excellent DC specs and LTC1608 differential inputs and reference circuitry can ac-
very low distortion performance to 100kHz. commodate other input ranges often with little or no addi-
tional circuitry. The following sections describe the refer-
Input Filtering ence and input circuitry and how they affect the input range.
The noise and the distortion of the input amplifier and
Internal Reference
other circuitry must be considered since they will add to
the LTC1608 noise and distortion. The small-signal band- The LTC1608 has an on-chip, temperature compensated,
width of the sample-and-hold circuit is 15MHz. Any noise curvature corrected, bandgap reference that is factory
or distortion products that are present at the analog inputs trimmed to 2.500V. It is connected internally to a reference
will be summed over this entire bandwidth. Noisy input amplifier and is available at VREF (Pin 3) (see Figure 12a).
circuitry should be filtered prior to the analog inputs to LinearView is a trademark of Linear Technology Corporation.

12
 LTC1608
U U W U
APPLICATIO S I FOR ATIO
R1 1
AIN+
3 VREF 7.5k BANDGAP ANALOG INPUT
2.500V 2V TO 2.7V
REFERENCE
DIFFERENTIAL 2
AIN–

LTC1608
4 REFCOMP REFERENCE 2V TO 2.7V 3
4.375V LTC1450 VREF
AMP

R2 4
22µF 12k REFCOMP

R3 22µF
16k 5
5 AGND AGND
LTC1608 1608 F13

1608 F12a

Figure 13. Driving VREF with a DAC

Figure 12a. LTC1608 Reference Circuit

Differential Inputs
5V 1
AIN+
ANALOG The LTC1608 has a unique differential sample-and-hold
VIN INPUT 2
AIN– circuit that allows rail-to-rail inputs. The ADC will always
LT1019A-2.5
VOUT
3
VREF
convert the difference of AIN+ – AIN– independent of the
LTC1608
common mode voltage (see Figure 15a). The common
4 mode rejection holds up to extremely high frequencies
REFCOMP
+ (see Figure 14a). The only requirement is that both inputs
22µF 0.1µF
5
can not exceed the AVDD or VSS power supply voltages.
AGND
Integral nonlinearity errors (INL) and differential nonlin-
1608 F12b
earity errors (DNL) are independent of the common mode
Figure 12b. Using the LT1019-2.5 as an External Reference
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
A 7.5k resistor is in series with the output so that it can be common mode voltage. Dynamic performance is also
easily overdriven by an external reference or other affected by the common mode voltage. THD will degrade
circuitry (see Figure 12b). The reference amplifier gains as the inputs approach either power supply rail, from 96dB
the voltage at the VREF pin by 1.75 to create the required with a common mode of 0V to 86dB with a common mode
internal reference voltage. This provides buffering of 2.5V or – 2.5V.
between the VREF pin and the high speed capacitive DAC.
80
The reference amplifier compensation pin (REFCOMP, Pin
4) must be bypassed with a capacitor to ground. The 70
COMMON MODE REJECTION (dB)

reference amplifier is stable with capacitors of 22µF or 60

greater. Using a 0.1µF ceramic in parallel is recommended. 50

The VREF pin can be driven with a DAC or other means 40

shown in Figure 13. This is useful in applications where the 30

peak input signal amplitude may vary. The input span of 20
the ADC can then be adjusted to match the peak input
10
signal, maximizing the signal-to-noise ratio. The filtering
0
of the internal LTC1608 reference amplifier will limit 1k 10k 100k 1M
the bandwidth and settling time of this circuit. A settling INPUT FREQUENCY (Hz)
1608 G14a

time of 20ms should be allowed for after a reference

adjustment. Figure 14a. CMRR vs Input Frequency

13
LTC1608
U U W U
APPLICATIO S I FOR ATIO
Differential inputs allow greater flexibility for accepting
011...111
different input ranges. Figure 14b shows a circuit that
011...110
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.

OUTPUT CODE
000...001
000...000
1 111...111
ANALOG INPUT AIN+
2 111...110
AIN–
0V TO 3
±2.5V 5V
+ VREF 100...001
100...000
– LTC1608
– (FS – 1LSB) FS – 1LSB
4 INPUT VOLTAGE (AIN+ – AIN– )
REFCOMP 1608 F15a

22µF
5
AGND Figure 15a. LTC1608 Transfer Characteristics
1608 F14b

ANALOG 1
AIN+
Figure 14b. Selectable 0V to 5V or ±2.5V Input Range INPUT
2
R1 AIN–
LTC1662
Full-Scale and Offset Adjustment 40.2k R2
100Ω
CS/LD VOUTA
LTC1608
Figure 15a shows the ideal input/output characteristics SCK GND
R3 3
VREF
SDI VCC 1.5M
for the LTC1608. The code transitions occur midway 5V REF VOUTB
+
between successive integer LSB values (i.e., – FS + 2.2µF
4
REFCOMP
0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,... FS – 1.5LSB, 0.1µF +
80.6k 22µF
FS – 0.5LSB). The output is two’s complement binary with 1% 5
AGND
1LSB = FS – (– FS)/65536 = 5V/65536 = 76.3µV. OFFSET ADJ RANGE: ±0.125% –5V 1608 F15b
FULL-SCALE ADJ RANGE: ±0.25%
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset Figure 15b. Offset and Full-Scale Adjust Circuit
error must be adjusted before full-scale error. Figure 15b
shows the extra components required for full-scale error ground plane is required. Layout should ensure that digital
adjustment. Zero offset is achieved by adjusting the offset and analog signal lines are separated as much as possible.
applied to the AIN– input. For zero offset error, apply Particular care should be taken not to run any digital track
– 38µV (i.e., – 0.5LSB) at AIN+ and adjust the offset at the alongside an analog signal track or underneath the ADC.The
AIN– input by varying the output voltage of pin VOUTA from analog input should be screened by AGND.
the LTC1662 until the output code flickers between 0000
0000 0000 0000 and 1111 1111 1111 1111. For full-scale An analog ground plane separate from the logic system
adjustment, an input voltage of 2.499886V (FS/2 – 1.5LSBs) ground should be established under and around the ADC.
is applied to AIN+ and the output voltage of pin VOUTB is Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other
adjusted until the output code flickers between 0111 1111 analog grounds should be connected to this single analog
1111 1110 and 0111 1111 1111 1111. ground point. The REFCOMP bypass capacitor and the
DVDD bypass capacitor should also be connected to this
analog ground plane. No other digital grounds should be
BOARD LAYOUT AND GROUNDING connected to this analog ground plane. Low impedance
Wire wrap boards are not recommended for high resolu- analog and digital power supply common returns are
tion or high speed A/D converters. To obtain the best per- essential to low noise operation of the ADC and the foil
formance from the LTC1608, a printed circuit board with width for these tracks should be as wide as possible. In

14
 LTC1608
U U W U
APPLICATIO S I FOR ATIO
applications where the ADC data outputs and control EXAMPLE LAYOUT
signals are connected to a continuously active micropro- Figures 17a, 17b, 17c, 17d and 17e show the schematic
cessor bus, it is possible to get errors in the conversion and layout of an evaluation board. The layout demon-
results. These errors are due to feedthrough from the strates the proper use of decoupling capacitors and ground
microprocessor to the successive approximation com-
plane with a 4-layer printed circuit board.
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The DC PERFORMANCE
traces connecting the pins and bypass capacitors must be The noise of an ADC can be evaluated in two ways: signal-
kept short and should be made as wide as possible. to-noise raio (SNR) in frequency domain and histogram in
The LTC1608 has differential inputs to minimize noise time domain. The LTC1608 excels in both. Figure 19a
coupling. Common mode noise on the AIN+ and AIN– leads demonstrates that the LTC1608 has an SNR of over 90dB
will be rejected by the input CMRR. The AIN– input can be in frequency domain. The noise in the time domain histo-
used as a ground sense for the AIN+ input; the LTC1608 gram is the transition noise associated with a high resolu-
will hold and convert the difference voltage between AIN+ tion ADC which can be measured with a fixed DC signal
and AIN– . The leads to AIN+ (Pin 1) and AIN– (Pin 2) should applied to the input of the ADC. The resulting output codes
be kept as short as possible. In applications where this is are collected over a large number of conversions. The
not possible, the AIN+ and AIN– traces should be run side shape of the distribution of codes will give an indication of
by side to equalize coupling. the magnitude of the transition noise. In Figure 18, the
distribution of output codes is shown for a DC input that
has been digitized 4096 times. The distribution is Gaussian
SUPPLY BYPASSING
and the RMS code transition noise is about 0.66LSB. This
High quality, low series resistance ceramic, 10µF or 22µF corresponds to a noise level of 90.9dB relative to full scale.
bypass capacitors should be used at the VDD and REFCOMP Adding to that the theoretical 98dB of quantization error
pins as shown in Figure 16 and in the Typical Application for 16-bit ADC, the resultant corresponds to an SNR level
on the first page of this data sheet. Surface mount ceramic of 90.1dB which correlates very well to the frequency
capacitors such as Taiyo Yuden’s LMK325BJ106MN and domain measurements in Dynamic Performance section.
LMK432BJ226MM provide excellent bypassing in a small
board space. Alternatively, 10µF tantalum capacitors in DYNAMIC PERFORMANCE
parallel with 0.1µF ceramic capacitors can be used. By-
pass capacitors must be located as close to the pins as The LTC1608 has excellent high speed sampling capabil-
possible. The traces connecting the pins and the bypass ity. Fast fourier transform (FFT) test techniques are used
capacitors must be kept short and should be made as wide to test the ADC’s frequency response, distortions and
as possible.

1 DIGITAL
AIN+ LTC1608
SYSTEM
AIN–
VREF REFCOMP AGND VSS AVDD AVDD DVDD DGND OVDD OGND
ANALOG 2
INPUT + 3 4 5, 6, 7, 8 34 36 35 9 10 29 28
CIRCUITRY
– 2.2µF 10µF
22µF 10µF 10µF 10µF 10µF

1608 F16

Figure 16. Power Supply Grounding Practice

15
LTC1608
U U W U
APPLICATIO S I FOR ATIO
E5
E2
3V
R6 JP1 –5V C28 C8
OVDD
10Ω + 22µF 0.1µF
E1
5V OVDD
+ C13
+ C12
22µF 22µF U5
C7 E6 TC7SH08FUTE85L
1µF GND 5V
J2
E3 CONVERT
VREF U1 LTC1608 R3 R5 JP3 R4 10k R2 R1 START
1 36 C6 10k 51k
5V 10Ω 1µF 10k
AIN+ AIN+ AVDD1 C1 J1
C11 2 35
2.2µF AIN– AIN– AVDD2 0.1µF CONN20
3 34 C5 1µF OVDD E7 1
VREF VSS U2 MC74HC574ADT GND
C10 22µF 4 33 3
REFCOMP SHDN 1 20 CLK
OE VCC 5
5 32 MSB
AGND CS 2 19 7
D0 Q0
6 31
AGND CONV 3 18 9
D1 Q1
7 30 11
AGND RD 4 17
C9 5V OVDD D2 Q2
8 29 C4 1µF 13
1µF AGND OVDD 5 16
D3 Q3 15
E4 9 28
DVDD OGND 6 15
GND D4 Q4 17
10 27
DGND BUSY 7 14
D5 Q5 19
11 26
D15 D0 8 13 21
D6 Q6
12 25
D14 D1 9 12 23
D7 Q7
13 24 25
D13 D2 10 11
GND CLK 27
14 23
D12 D3
15 22 29
D11 D4 C3 0.1µF 31
16 21
D10 D5 OVDD 33
17 20
D9 D6 U3 74HC574 35
18 19 1 20
D8 D7 OE VCC 37
2 19 LSB
D0 Q0 39
3 18
D1 Q1
4 17
D2 Q2
5 16
D3 Q3
5V 6 15
D4 Q4
C21 C27 7 14
0.1µF 100pF D5 Q5
8 13
R7 D6 Q6
J3 50Ω 3 8 9 12
+ D7 Q7 OVDD
AIN+
1 + 10 11
R17 C14 U4A AIN GND CLK
10k 1000pF 2 LT1469 (U1-1) JP2
C20 R11 R13
– 4 0.1µF 50Ω 50Ω U6
C17 –5V C25 TC7SH04F
10pF 100pF
R8 402Ω
C15 10pF

C18 C24 C26

10pF R15 C16 10pF 100pF 1000pF
100Ω

R9
6 402Ω R14
– R12
U4B 7 50Ω 50Ω AIN–
R10
J4 50Ω LT1469 (U1-2)
5 C22 C23
AIN– +
100pF 100pF
R16 C19
10k 1000pF

Figure 17a. LTC1608 Suggested Evaluation Circuit Schematic

16
 LTC1608
U U W U
APPLICATIO S I FOR ATIO

Figure 17b. Suggested Evaluation Circuit Board. Figure 17c. Suggested Evaluation Circuit Board.
Component Side Silkscreen and Signal Traces Bottom Side Showing Signal Traces
ANALOG GROUND PLANE DIGITAL GROUND PLANE ANALOG GROUND PLANE DIGITAL GROUND PLANE

Figure 17d. Suggested Evaluation Circuit Board. Inner Layer 1 Figure 17e. Suggested Evaluation Circuit Board. Inner Layer 2
Showing Separate Analog and Digital Ground Planes Showing Separate Analog and Digital Ground Planes

2500
noise at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
2000
algorithm, the ADC’s spectral content can be examined for
1500
frequencies outside the fundamental. Figures 19a and 19b
show typical LTC1608 FFT plots.
COUNT

1000
Signal-to-Noise Ratio
500 The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental
0
–5 –4 –3 –2 –1 0 1 2 3 4 5 input frequency to the RMS amplitude of all other fre-
CODE quency components at the A/D output. The output is band
1608 F18
limited to frequencies from above DC and below half the
Figure 18. Histogram for 4096 Conversions sampling frequency. Figure 19a shows a typical spectral
content with a 500kHz sampling rate and a 3kHz input.

17
LTC1608
U U W U
APPLICATIO S I FOR ATIO
0 16 98
fSAMPLE = 500kHz
fIN = 2.807kHz 15 92
–20 SINAD = 88.9dB
THD = –98dB 14 86
–40
AMPLITUDE (dB)

EFFECTIVE BITS
13 80

SINAD (dB)
–60
12 74
–80
11 68
–100 62
10

–120 9 56

–140 8 50
0 50 100 150 200 250 1k 10k 100k 1M
FREQUENCY (kHz) FREQUENCY (Hz)
1608 F20
1608 F19a

Figure 19a. This FFT of the LTC1608’s Conversion of a Figure 20. Effective Bits and Signal/(Noise + Distortion)
Full-Scale 3kHz Sine Wave Shows Outstanding Response vs Input Frequency
with a Very Low Noise Floor When Sampling at 500ksps
Total Harmonic Distortion
0
fSAMPLE = 500kHz
fIN = 98.754kHz
Total harmonic distortion (THD) is the ratio of the RMS
–20 SINAD = 86.7dB sum of all harmonics of the input signal to the fundamental
THD = –92.6dB
–40 itself. The out-of-band harmonics alias into the frequency
AMPLITUDE (dB)

band between DC and half the sampling frequency. THD is

–60
expressed as:
–80

–100 V22 + V32 + V 42 + ...Vn2

THD = 20Log
–120 V1
–140
0 50 100 150 200 250 where V1 is the RMS amplitude of the fundamental fre-
FREQUENCY (kHz) quency and V2 through Vn are the amplitudes of the
1608 F19b
second through nth harmonics. THD vs Input Frequency is
Figure 19b. Even with Inputs at 100kHz, the shown in Figure 21. The LTC1608 has good distortion
LTC1608’s Dynamic Linearity Remains Robust performance up to the Nyquist frequency and beyond.
The dynamic performance is excellent for input frequen- Intermodulation Distortion
cies up to and beyond the Nyquist limit of 250kHz.
If the ADC input signal consists of more than one spectral
Effective Number of Bits component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
The effective number of bits (ENOBs) is a measurement of THD. IMD is the change in one sinusoidal input caused by
the resolution of an ADC and is directly related to the the presence of another sinusoidal input at a different
S/(N + D) by the equation: frequency.
ENOB = [S/(N + D) – 1.76]/6.02 If two pure sine waves of frequencies fa and fb are applied
where ENOB is the effective number of bits of resolution to the ADC input, nonlinearities in the ADC transfer
and S/(N + D) is expressed in dB. At the maximum function can create distortion products at the sum and
sampling rate of 500kHz, the LTC1608 maintains above 14 difference frequencies of mfa ±nfb, where m and n = 0,
bits up to the Nyquist input frequency of 250kHz (refer to 1, 2, 3, etc. For example, the 2nd order IMD terms include
Figure 20).

18
 LTC1608
U U W U
APPLICATIO S I FOR ATIO
0
(fa ± fb). If the two input sine waves are equal in
AMPLITUDE (dB BELOW THE FUNDAMENTAL)

–10
–20
magnitude, the value (in decibels) of the 2nd order IMD
–30 products can be expressed by the following formula:
–40
–50
–60 (
IMD fa ± fb = 20Log ) Amplitude at (fa ± fb)
Amplitude at fa
–70
–80 THD
3RD
–90 2ND
Peak Harmonic or Spurious Noise
–100
–110
The peak harmonic or spurious noise is the largest spec-
1k 10k 100k 1M tral component excluding the input signal and DC. This
INPUT FREQUENCY (Hz)
1608 F21
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Figure 21. Distortion vs Input Frequency
Full-Power and Full-Linear Bandwidth
0
fSAMPLE = 500kHz
–20
fIN1 = 96.56kHz The full-power bandwidth is that input frequency at which
fIN2 = 99.98kHz
the amplitude of the reconstructed fundamental is
–40 reduced by 3dB for a full-scale input signal.
AMPLITUDE (dB)

–60
The full-linear bandwidth is the input frequency at which
–80 the S/(N + D) has dropped to 84dB (13.66 effective bits).
–100
The LTC1608 has been designed to optimize input band-
width, allowing the ADC to undersample input signals with
–120
frequencies above the converter’s Nyquist Frequency. The
–140 noise floor stays very low at high frequencies; S/(N + D)
0 50 100 150 200 250
FREQUENCY (kHz) becomes dominated by distortion at frequencies far
1608 F22 beyond Nyquist.
Figure 22. Intermodulation Distortion Plot

U
PACKAGE DESCRIPTIO
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.67 – 12.93*
(.499 – .509)
5.20 – 5.38**
(.205 – .212) 1.73 – 1.99 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
(.068 – .078)

0° – 8°

7.65 – 7.90
.65 (.301 – .311)
.13 – .22 .55 – .95
(.022 – .037) (.0256)
(.005 – .009)
BSC .05 – .21
NOTE: .25 – .38 (.002 – .008)
1. CONTROLLING DIMENSION: MILLIMETERS (.010 – .015)
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 G36 SSOP 0501

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1608
U
TYPICAL APPLICATIO
Using the LTC1608 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System

5V 2.2µF 10µF 5V 10µF 5V 10µF

10Ω

+ + + +
LTC1391 3 36 35 9 10
1µF
1 16 DVDD
CH0+ CH0 V+ VREF AVDD AVDD DGND
2 15 SHDN 33
CH1 D
–5V
3 – 14 LTC1608 CS 32
CH2 V CONTROL
1µF LOGIC CONVST 31 µP
4 13 + 7.5k CONTROL
CH3 DOUT 4 REFCOMP 2.5V AND
5 12 1.75X TIMING RD 30 LINES
CH4 DIN + 4.375V REF
22µF BUSY 27
6 11
CH5 CS
OVDD 29 5V OR
7 10
CH6 CLK
+ + 3V
8 9 1 AIN 10µF
CH7 + CH7 GND + OGND 28
3000pF 16-BIT OUTPUT
SAMPLING B15 TO B0 BUFFERS 16-BIT
5V –
2 AIN ADC D15 TO D0 PARALLEL
– BUS
LTC1391 3000pF
1 16 1µF 11 TO 26
V+ AGND AGND AGND AGND VSS
CH0 – CH0
2 15 5 6 7 8 34 1608 TA03
CH1 D
–5V 10µF
3
CH2 V–
14 +
4
CH3 DOUT
13 + –5V
5 12
CH4 DIN DIN
6 11 µP
CH5 CS CS CONTROL
7 10 LINES
CH6 CLK CLK
– 8 9
CH7 CH7 GND

RELATED PARTS
SAMPLING ADCs
PART NUMBER DESCRIPTION COMMENTS
LTC1410 12-Bit, 1.25Msps, ±5V ADC 71.5dB SINAD at Nyquist, 150mW Dissipation
LTC1415 12-Bit, 1.25Msps, Single 5V ADC 55mW Power Dissipation, 72dB SINAD
LTC1418 14-Bit, 200ksps, Single 5V ADC 15mW, Serial/Parallel ±10V
LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LTC1604 16-Bit, 333ksps, ±5V ADC 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608
LTC1605 16-Bit, 100ksps, Single 5V ADC ±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606
LTC1606 16-Bit, 250ksps, Single 5V ADC ±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605

DACs
PART NUMBER DESCRIPTION COMMENTS
LTC1595 16-Bit Serial Multiplying IOUT DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
LTC1596 16-Bit Serial Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
LTC1597/LTC1591 16-Bit/14-Bit Parallel, Multiplying DACs ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650 16-Bit Serial VOUT DAC Low Power, Low Gritch, 4-Quadrant Multiplication

Linear Technology Corporation 1608fs, sn1608 LT/TP 0601 2K • PRINTED IN USA

20 1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 2000