SIDDHARTH INSTITUTE OF ENGINEERING & TECHNOLOGY

(AUTONOMOUS)
(Approved by AICTE, New Delhi& Affiliated to JNTUA, Ananthapuramu)
(Accredited by NBA for Civil, EEE, Mech., ECE & CSE)
(Accredited by NAAC with ‘A+’ Grade)
Puttur -517583, Chittoor District, A.P. (India)
SUBJECT WITH MICROPROCESSORS AND COURSE & B.Tech – CSE&
CODE: MICROCONTROLLERS (20EC0416) BRANCH: CSIT
YEAR & SEM: II-B. Tech & II- Sem REGULATION: R20
UNIT–V
Applications

1 a) Discuss about Keyboards and human factors. [L2] [CO5] [6M]

Keyboards:
The predominant interface between humans and computers is the keyboard. Keyboards
range in complexity from the "up-down" buttons used for elevators to the personal computer
QWERTY layout, with the addition of function keys and numeric keypads.
One of the first mass uses for the microcontroller was to interface between the keyboard
and the main processor in personal computers. Industrial and commercial applications fall
somewhere in between these extremes, using layouts that might feature from six to twenty keys.

The one constant in all keyboard applications is the need to accommodate the human user.
Human beings can be irritable. They have little tolerance for machine failure; watch what happens
when the product isn't ejected from the vending machine. Sometimes they are bored by routine, or
even hostile towards the machine. The hardware designer has to select keys that will survive in the
intended environment.
The programmer must write code that will anticipate and defeat inadvertent and also
deliberate attempts by the human to confuse the program. It is very important to give instant
feedback to the user that the key hit has been acknowledged by the program. By light of a light,
beep of a buzzer, display of the key hit, or whatever, the human user must know that the key has
been recognized.
Even feedback sometimes is not enough; note the behavior of people at an elevator. Even
if the "up" light is lit when we arrive, we will push it again to let the machine know that "I'm here
too."

Human Factors:
The keyboard application program must guard against the following possibilities:
• More than one key pressed (simultaneously or released in any sequence).
• Key pressed and held
• Rapid key press and release
 All of these situations can be addressed by hardware or software means: software, which
is the most cost-effective, is emphasized here.
1 b) Describe and draw the keyboard configurations. [L1] [CO5] [6M]
Keypads are widely used input devices being used in various electronics and
embedded projects. They are used to take inputs in the form of numbers and alphabets and
feed the same into system for further processing.

Matrix keypad consists of set of Push buttons, which are interconnected. Like in our case
we are using 4X4 matrix keypad, in which there are 4 push buttons in each of four rows. And the
terminals of the push buttons are connected according to diagram. In first row, one terminal of all
the 4 push buttons are connected together and another terminal of 4 push buttons are representing
each of 4 columns, same goes for each row. So we are getting 8 terminals to connect with a
microcontroller.

As shown in above circuit diagram, to interface Keypad, we need to connect 8 terminals of

the keypad to any port (8 pins) of the microcontroller. Like we have connected keypad terminals
to Port 1 of 8051. Whenever any button is pressed we need to get the location of the button, means
the corresponding ROW a COLUMN no.

To read the key press, we need to configure the rows as outputs and columns as
inputs.

Columns are read after applying signals to the rows in order to determine whether or not
a key is pressed and if pressed, which key is pressed.
2 a) List out types of 16 key layout and draw the diagram of the lead per key keyboard
configuration [L4] [CO5] [6M]
Keyboards are commercially produced in one of the three general hypothetical wiring configurations for a
16-key layout shown in Figure. The lead-per-key

Configuration is typically used when there are very few keys to be sensed. Since each key
could tie up a port pin, it is suggested that the number be kept to 16 or fewer for this keyboard
type. This configuration is the most cost-effective for a small number of keys.
2 b) Design the x-y matrix keyboard and coded key board. [L6] [CO5] [6M]

X-Y Matrix Keyboard:

The X-Y matrix connections shown in Figure 10.1 are very popular when the number of
keys exceeds 10. The matrix is most efficient when arranged as a square so that N leads for X and
N leads for Y can be used to sense as many as N² keys. Matrices are the most cost-effective for a
large number of keys.

Coded key board:

 Coded keyboards were evolved originally for telephonic applications involving touch-
tone signaling. The coding permits multiple key presses to be easily detected.
The quality and durability of these keypads are excellent as a result of the high
production volumes and intended use. They are generally limited to 16 keys or fewer, and tend to
be the most expensive of all keyboard types.

3 a) Illustrate the programs for keyboards [L3] [CO5] [6M]

Programs that deal with humans via keyboards approach the human and key switch
factors identified in the following manner:

• Bounce: A time delay that is known to exceed the manufacturer's specification is used to
wait out the bounce period in both directions.

• Multiple keys: Only patterns that are generated by a valid key pressed are accepted all
others are ignored-and the first valid pattern is accepted.

• Key held: Valid key pattern accepted after valid debounce delay; no additional keys
accepted until all keys are seen to be up for a certain period of time.

• Rapid key hit: The design is such that the keys are scanned at a rate faster than any
human reaction time.

The last item brings up an important point: Should the keyboard be read as the program loops
(software-polled) or read only when a key has been hit (interrupt driven)?

In general, the smaller keyboards (lead-per-key and coded) can be handled either way. The
common lead can be grounded and the key pattern read periodically. Or, the lows from each can
be active-low ORed and connected to one of the external INTX pins.
Matrix keyboards are scanned by bringing each X row low in sequence and detecting a Y column
low to identify each key in the matrix. X-Y scanning can be done by using dedicated keyboard
scanning circuitry or by using the microcontroller ports under program control. The scanning
circuitry adds cost to the system. The programming approach takes processor time, and the
possibility exists that response to the user may be sluggish if the program is busy elsewhere when
a key is hit.
Note how long your personal computer takes to respond to a break key when it is executing
a print command, for instance. The choice between adding scanning hardware or program software
is decided by how busy the processor is and the volume of entries by the user.

3 b) Explain and draw the scanning keyboards and it configuration. [L2] [CO5] [6M]

Assume that a lead-per-key keyboard is to be interfaced to the microcontroller. The

keyboard has 10 keys (0-9), and the debounce time, when a key is pressed or released, is 50
milliseconds. The keyboard is used to select snacks from a vending machine, so the processor is
only occupied when a selection is made.

The program constantly scans the keyboard waiting for a key to be pressed before calling
the vending machine actuator subroutine. The keys are connected to port 1 (0-7) and ports 3.2 and
3.3 (8-9).The 8031 works best when handling data in byte-sized packages. To save internal space,
the 10-bit word representing the port pin configuration is converted to a single-byte number.

Because the processor has nothing to do until the key has been detected, the time delay softime is
used to debounce the keys.
4 a) Design and explain the large matrix keyboard. [L2] [CO5] [6M]

A 64-key keyboard, arranged as an 8-row by 8-column matrix, will be interfaced to the

8051 microcontroller, Port 1 will be used to bring each row low, one row at a time, using an 8-bit
latch that is strobed by port 3.2. P1 will then read the 8-bit column pattern by enabling the tri- state
buffer from port 3.3. A pressed key will have a unique row-column pattern of one row low, one
column low.
Multiple key presses are rejected by either an invalid pattern or a failure to match for three
complete cycles. Each row is scanned at an interval of 2 milliseconds, or a 16-millisecond cycle
for the entire keyboard.
A valid key must be seen to be the same key for three cycles (48 milliseconds). There must
then be three cycles with no key down before a new key will be accepted. The 2- millisecond delay
between scans is generated by timer TO in an interrupt mode.
Bigkey:

The bigkey program scans an 8 × 8 keyboard matrix using T0 to generate a periodic 2-ms
delay in an interrupt mode. Each row is scanned via an external latch driven by port 1 and strobed
by port 3.2. Columns are read via a tri-state buffer under control of port 3.3. Keys found to be valid
are passed to the main program by setting the flag newflag and placing the key identifiers in
locations newrow and newcol. The main program resets newflag when the new key is fetched. R4
is used as a cycle counter for successful matches and up time cycles. R5 is used to hold the row
scan pattern: only 1 bit low.

4 b) Discuss about interrupt driven program for small keyboards. [L2] [CO5] [6M]

If the application is so time sensitive that the delays associated with debouncing and
waiting an all-up cannot be tolerated, then some form of interrupt must be used so that the main
program can run unhindered.

A compromise may be made by polling the keyboard as the main program loops, but all
time delays are done using timers so that the main program does not wait for a software delay. The
getkey program can be modified to use a timer to generate the delays associated with the key-down
debounce time and the “all-up” delay. The challenge associated with this approach isto have the
program remember which delay is being timed out. Remembering which delay is in progress can
be handled using a flag bit, or one timer can be used to generate the key-down debounce delay,
and another timer to generate the key-up delay. The two-timer approach is examined in the
example given in this section.

The important feature of the program is that the main program will check a flag to see whether
there is any keyboard activity. If the flag is set, then the program finds the key stored in a RAM
location and resets the flag. The getting of the key is transparent to the main program; it is done in
the interrupt program.

Inkey:

The program inkey uses both hardware timers, T0 and T1, to generate the time delays needed to
scan and debounce the keyboard.

The subroutines that get a key run in the background by using timer T1 to generate a main program
interrupt every 50 milliseconds. At least one 50ms time interval must occur before the T1 interrupt
routine will scan the keys. The T1 interrupt routine scankey then scans the keys. If a valid key is
found down, T0 is started to debounce the key for 20 milliseconds. Timer T1 is stopped, and the
T1 interrupt routine returns to the main program. After 20 milliseconds, T0 times out and
interrupts the main program.

The T0 interrupt routine same key checks for the same valid key down as was found by scankey.
If the same valid key is found, the key's code is stored and a flag, keyflag, is set. T0 is stopped and
T1 is restarted for the next 50ms keyboard scan delay.

5 a) Explain and design the 2*4 coded keyboard [L2] [CO5] [6M]

Codekey:

The completely interrupt-driven small keyboard example given in this section requires no program
action until a key has been pressed. Hardware must be added to attain a completely interrupt- driven event.

An inspection of the code reveals that each nibble of P1 has only 1 bit that is low for each key
and that 2 of the 8 bits are uniquely low for each key. If more than one key is pressed, then 3 or more bits
go low, signaling an invalid condition. This popular scheme allows for up to 16 keys to be coded in this
manner. Unlike the lead-per-key arrangement, only four of the lines must be active-low ORed to generate
an interrupt.
 The hardware serves to detect when any number of keys are hit by using an AND gate to detect
when any nibble bit goes low. The high-to-low transition then serves to interrupt the microcontroller on
port 3.2 (INT0). The interrupt program reads the keys connected to port 1 and uses timer T0 to generate
the debounce time and T1 for the keys-up delay. The total delay possible at 12 megahertz for the timers is
65.53 milliseconds, which covers the delay times used in the previous examples.

The program Codekey is interrupt-driven by a high-to-low transition on INT0. Timers T0 and T1

generate the debounce and delay times in an interrupt mode. The INT0 interrupt input is disabled until all
keys have been seen up for the T1 delay. A lookup table is used to verify that only one key is pressed.

5 b) Illustrate the seven segment numeric led Display and explain the operation
Seven segment. [L2] [CO5] [6M]

Seven-segment displays commonly contain LED segments arranged as an 8, with one

common lead (anode or cathode) and seven individual leads for each segment. If more than one
display is to be used, then they can be time multiplexed; the human eye cannot detect the blinking
if each display is relit every 10 milliseconds or so. The 10 milliseconds is divided by the number
of displays used to find the interval between updating each display.
 The example examined here uses four seven-segment displays; the segment informationis
output on port 1 and the cathode selection is done on ports 3.2 to 3.5.A segment will be lit only if
the segment line is brought high and the common cathode is brought low.
Transistors must be used to handle the currents required by the LEDs, typically 10
milliamperes for each segment and 70 milliamperes for each cathode. These are average current
values; the peak currents will be four times as high for the 2.5 milliseconds each display is
illuminated.
The program is interrupt driven by T0 in a manner similar to that used in the program
bigkey. The interrupt program goes to one of four 2-byte character locations and finds the cathode
segment pattern to be latched to port 1 and the anode pattern to be latched to port 3.

The main program uses a lookup table to convert from a hex number to the segment pattern
for that number. In this way, the interrupt program automatically displays whatever number the
main program has placed in the character locations and is not concerned with how they are
displayed.

6 a) List out the types of led displays and draw the seven segment display circuit used for
SVNSEG program [L3] [CO5] [6M]

The program svnseg displays characters found in locations ch1 to ch4 on four common-
cathode seven-segment displays. Port 1 holds the segment pattern from the low byte of chx; port
3 holds the cathode pattern from the high byte of chx. To generates a 2.5 milliseconds delay
interval between characters in an interrupt mode. The main program uses a lookup table to convert
from hex to a corresponding pattern. RO of bank 1 is dedicated as a pointer to the displayed
character.
 Seven segment display circuit used for SVNSEG program

6 b) Draw the pin diagram and explain the intelligent LCD display [L1] [CO4] [6M]

The display contains two internal byte-wide registers, one for commands (RS= 0) and the
second for characters to be displayed (RS 1). It also contains a user-programmed RAM area (the
character RAM) that can be programmed to generate any desired character that can be formed
using a dot matrix.
To distinguish between these two data areas, the hex command byte 80 will be used to
signify that the display RAM address 00h is chosen. 14 Port 1 is used to furnish the command or
data byte, and ports 3.2 to 3.4 furnish register select and read/write levels. The display takes
varying amounts of time to accomplish the functions.
LCD bit 7 is monitored for logic high (busy) to ensure the display is not overwritten. A
slightly more complicated LCD display (4 lines X 40 characters) is currently being used in medical
diagnostic systems to run a very similar program.
7 a) Define the D/A and A/D conversions and write any five advantages [L1] [CO4] [6M]

Conversion between the analog and digital worlds requires the use of integrated circuits that have
been designed to interface with computers. Highly intelligent converters are commercially available that
all have the following essential characteristics
D/A Conversion:
Basically, D/A conversion is the process of taking a value represented in digital code (such as
straight binary or BCD) and converting it to a voltage or current which is proportional to the digital value.
Now, we will examine the various input/output relationships. \
D/A converter (DAC) Vout Analog output Digital inputs MSB LSB Four bit DAC with voltage
output. The digital inputs D, C, B, and A are usually derived from the output register of a digital system.
The 24 = 16 different binary numbers represented by these 4 bits for each input number, the D/A
converter output voltage is a unique value. In fact, for this case, the analog output voltage Vout is equal in
volts to the binary number.
A/D Conversion:
The transducer’s electrical analog output serves as the analog input to the ADC. The ADC converts
this analog input to a digital output. This digital output consists of a number of bits that represent the value
of the analog input.
For example, the ADC might convert the transducer’s 800- to 1500-mV analog values to binary
values ranging from 01010000 (80) to 10010110 (150). Note that the binary output from the ADC is
proportional to the analog input voltages so that each unit of the digital output represents 10mV. The digital
representation of the analog vales is transmitted from the ADC to the digital computer, which stores the
digital value and processes it according to a program of instructions that it is executing.

A/D Converter D/A Converter

Advantages:

1. The conversion result is insensitive to errors in the component values.

2. Fewer adverse effects from “noise”

3. High Accuracy

4. ADC output can be sent over long distances

5. Weighted Resistor Circuit is the fastest converting circuit compared to other methods.

6. High resolution and accuracy can be achieved.

7. DAC’s are simple to implement.

7 b) Draw diagram and explain the D/A converter circuit [L4] [CO5] [6M]

D/A Conversion:
A generic R-2R type D/A converter, based on several commercial models, is connected to ports 1
and 3 as shown in Figure 10.10. Port 1 furnishes the digital byte to be converted to an analog voltage; port
3 controls the conversion process.
The converter has these features:
• Vout = -Vref × (byte in/100H), Vref ±10v
• Conversion time: 5 micro sec
• Control sequence: CS bar then WR bar
Davcon:
The D/A converter program davcon generates a 1,000-hertz sine wave using an 8-bit converter.
166d samples are stored in a lookup table and fed to the converter at a rate of one sample every 6
microseconds. The lookup table is pointed to in external ROM by the DPTR, and R1 is used to count the
samples. Numbers in parentheses indicate the number of cycles.

8 a) Design and explain the A/D converter circuit [L2] [CO5] [8M]
A/D Conversion:
The easiest A/D converters to use are the flash types, which make conversions based on an array
of internal comparators. The conversion is very fast, typically in less than 1 microsecond. Thus, the
converter can be told to start, and the digital equivalent of the input analog value will be read one or two
instructions later.
Modern successive approximation register (SAR) converters do not lag far behind, however, with
conversion times in the 2-4 microsecond range for 8 bits. At this writing, flash converters are more
expensive (by a factor of two) than the traditional SAR types, but this cost differential should disappear
(within time).
Typical features of an 8-bit flash converter are:

• Data: Vin Vref(-), data 00h; Vin Vref(+), data= FFh

• Conversion time: 1micro sec

• Control sequence: CS bar then WR bar then RD bar

An example circuit, using a generic flash converter, Port 1 is used to read the byte value of the input
analog voltage, and port 3 controls the conversion. A conversion is started by pulsing the write line low,
and the data is read by bringing the read line low.
Our example involves the digitizing of an input waveform every 100d microseconds until 1,000d
samples have been stored in external RAM
Adconv:

The program adconv will digitize an input voltage by sampling the input every 100 us and storing
the digitized values in external RAM locations 4000h to 43E7h (1000d samples). Numbers in parentheses
are cycles. The actual delay between samples is 99.75 microseconds.
 begin equ 4000h ;start storage at 4000h
delay equ 74h ;delay in DJNZ loop for 87 usec
end1 equ 43h ;high byte of ending address
end2 equ 0e8h ;low byte of ending address
org 0000h
adconv: mov dptr,#begin
clr p3.2 ;generate CS bar to ADC
next: clr p3.3 ;generate WR bar pulse (1)
setb p3.3 ;(1)
clr p3.4 ; generate RD bar pulse (1)
mov a,p1
setb p3.4
movx @dptr,a
inc dptr
mov a,dph
cjne a,#end1,wait
mov a,dpl
cjne a,#end2,wait
sjmp done
wait: mov r1,#delay
here: djnz r1, here
sjmp next
done: sjmp done
end ;simulate rest of program
8 b) List any five advantages of A/D converter and it applications [L1] [CO5] [4M]
Advantages:

1. The conversion result is insensitive to errors in the component values.

2. Fewer adverse effects from “noise”

3. High Accuracy

4. ADC output can be sent over long distances

Applications:

1. Cell phones operate on the digital voice signal.

 2. Images and videos captured using camera is stored in any digital device, is also
converted into digital form using ADC.
3. Medical Imaging like x-ray & MRI also uses ADC to convert images into Digital form
before modification.
9 a) Explain multiple interrupts present [L2] [CO2] [6M]

Multiple Interrupts:
The 8051 is equipped with two external interrupt input pins: INT0 and INT1 (P3.2 and P3.3).
These are sufficient for small systems, but the need may arise for more than two interrupt points. There
are many schemes available to multiply the number of interrupt points; they all depend on the following
strategies:

Connect the interrupt sources to a common line

Identify the interrupting source using software

Because the external interrupts are active-low, the connections from the interrupt source to the
INTX pin must use open-collector or tri-state devices.

An example of increasing the INT0 from one to eight points. Each source goes to active-low when an
interrupt is desired. A corresponding pin on port 1 receives the identity of the interrupter. Once the
interrupt program has handled the interrupt situation, the interrupter must receive an acknowledgment so
that the interrupt line for that source can be brought back to a high state. Port 3 pins 3.3, 3.4, and 3.5
supply, via a 3-to-8 decoder, the acknowledgment feedback signal to the proper interrupt source. The
decoder is, enabled by port pin 3.0.

Multiple and simultaneous interrupts can be handled by the program in as complex a manner as is
desired. If there is no particular urgency attached to any of the interrupts then they can be handled as the
port 1 pins are scanned sequentially for a low.

A simple priority system can be established whereby the most important interrupt sources are
examined in the priority order, and the associated interrupt program is run until finished. An elaborate
priority system involves ordering the priority of each source.
 The elaborate system acknowledges an interrupt immediately, thus resetting that source's interrupt line,
and begins executing the particular interrupt program for that source. A new interrupt from a higher
priority source forces the current interrupt program to be suspended and the new interrupter to be
serviced.

To acknowledge the current interrupt in anticipation of another, it is necessary to also re-arm the
INTX interrupt by issuing a "dummy" RETI instruction. The mechanism for accomplishing this task is
illustrated in the program named hipri. First, a low priority scheme is considered.

9 b) illustrate the multiple source interrupt circuit used in Lopri and Hipri program

[L3] [CO6] [6M]

Lopri
The program lopri scans port P1 for the source of an interrupt that has triggered INTO. The pins
are scanned for a low and the scan resumed after any interrupt is found and serviced. The interrupt source
is acknowledged prior to a RETI instruction. R5 of bank 1 is used to store the next pin to be scanned, and
R6 is used to scan the pins for a low. A jump table is used to select the interrupt routine that matches the
particular interrupt. Each interrupt routine supplies the 3-to-8 decoder a unique acknowledge pattern before
a RETI.
Hipri
Suppose that we wish to have a priority system by which the priority of each input pin is assigned
at a different level-that is, there are eight priority levels, and each higher level can interrupt one at a lower
level. Theoretically, this leads to at least nine return addresses being pushed on the stack (plus any other
registers saved), so the stack should be expected to grow more than 18d bytes; it is set above the addressable
bits at location 2Fh.
In order to enable the interrupt structure in anticipation of a higher level interrupt, it is necessary to
issue a RETI instruction without actually leaving the interrupt routine that currently has the highest priority.
One way to accomplish this task is to push on the stack the address of the current interrupt routine to be
done.
Then, use a RETI that will return to the address on the stack, the desired current interrupt
subroutine, and also re-arm the interrupt structure should another interrupt occur. The addresses of each
subroutine can be known before assembly by originating each at a known address, or the program can find
each address in a lookup table and push it on the stack, as illustrated in the example program.

10) Describe and design the hardware circuits for multiple interrupts [L1] [CO5] [10M]

Hardware Circuits for Multiple Interrupts:

Solutions to the expanded interrupt problem proposed to this point have emphasized using a
minimal amount of external circuitry to handle multiple, overlapping interrupts. A hardware strategy,
which can be expanded to cover up to 256 interrupt sources, is shown in Figure 10.13. This circuit is a
version of the daisy chain approach, which has long been popular.
The overall philosophy of the design is as follows:
1. The most important interrupt source is physically connected first in the chain, with those of lesser
importance next in line. Lower priority interrupt sources are "behind" (connected further from
INTO) those of a higher priority.

2. Each interrupting source can disable all signals from sources that are wired behind it. All sources
that lose the INACTOUT signal (a low level) from the source(s) ahead of it will place their
source address buffer in a tri-state mode until INACTOUT is restored.

3. A requesting source pulls its INTOUT line low and places its 8-bit identifier on the tri-state bus
connected to port.1. The interrupt routine at the INTO vector location reads P1 and, using a
lookup table, finds the address of the subroutine that handles that interrupt. The address is placed
on the stack and a RETI executed to go to that routine and re-arm the interrupt structure.

4. The interrupt subroutine generates an ACKIN signal (a low-level pulse) to the source from the
8051 at the end of the subroutine; the source then removes INTOUT and the 8-bit source address.
When an interrupt is acknowledged, the interrupting source mu t bring the INTOUT line high for
at least one machine cycle so that the 8051 interrupt structure can recognize the next high-to-low
transition on INTO.