8051 Timers and Counters aside for timer1.

aside for timer1. In each case, the lower 2 bits are used to set the timer
The 8051 has two counters/timers which can be used either as mode and upper 2 bits to specify the operation.
timer to generate a time delay or as counter to count events happening
outside the microcontroller.
The 8051 has two timers: timer0 and timer1. They can be used
either as timers or as counters. Both timers are 16 bits wide. Since the Gate: Bit D7 and D3 is allotted for gate. This bit is used to starting and
8051 has an 8-bit architecture, each 16-bit is accessed as two separate stopping the timer. Timers can be started by software means and
registers of low byte and high byte. hardware means also. If the gate bit is set to ‘0’ this is the software
way of starting and stopping the timer by an external source. If this bit
Timer0 registers is a 16 bits register and accessed as low byte is set to ‘1’ this is the software way of starting and stopping the timer.
and high byte. The low byte is referred as a TL0 and the high byte is C/T: Bit D6 and D2 is allotted for counter / Timer (C/T). This bit is
referred as TH0. These registers can be accessed like any other used to decide whether a timer is used as a timer to generate time delay
registers. or used as a counter to work as a event counter. If this bit is set to be
“0” then it is used as a timer to generate time delay and if it is “1” then
it is used as a counter to external count event.
Mode selection Bits (M0 and M1): Bit D0, D1 and D4, D5 is allotted
for M0 and M1 these are Mode selection Bits. The combination of
Timer1 registers is also a 16 bits register and is split into two
these bits are used to select the timer mode.
bytes, referred to as TL1 and TH1.

TMOD (timer mode) Register: This is an 8-bit register which is used

by both timers 0 and 1 to set the various timer modes. In this TMOD
register, lower 4 bits are set aside for timer0 and the upper 4 bits are set

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 Mode0- Mode 0 is exactly same like mode 1 except that it is a
13-bit timer instead of 16-bit. The 13-bit counter can hold values
between 0000 to 1FFFH in TH-TL. Therefore, when the timer reaches
its maximum of 1FFH, it rolls over to 0000, and TF is raised.
Mode 1- It is a 16-bit timer; therefore it allows values from TF1: The bit 7 is allotted for Timer1 over flow flag bit. This bit is Set
0000 to FFFFH to be loaded into the timer’s registers TL and TH. to 1 whenever timer rolls from all 1s to 0. And this bit is reset or
It can set by “SETB TR0” for timer 0 and “SETB TR1” for cleared When the processor executes interrupt service routine (ISR)
timer 1. Located at program address 001Bh.
It starts count up until it reaches its limit of FFFFH. When it TR1: The bit 6 is allotted as a Timer 1 run control bit. This bit is Set
rolls over from FFFF to 0000H, it sets high a flag bit called TF (timer to 1 by programmer to enable timer to count; It is reset or cleared to 0
flag). by program to halt timer.
When this timer flag is raised, one option would be stop the TF0: The bit 5 is allotted as a Timer 0 over flow flag. Same as TF1
timer with the instructions “CLR TR0“ or CLR TR1 for timer 0 and (Timer1 over flow flag bit).
timer 1 respectively. TR0: The bit 4 is allotted as a Timer 0 run control bit. Same as TR1
Mode 2- It is an 8 bit Auto Reload mode timer that allows (Timer 1 run control bit).
only values of 00 to FFH to be loaded into the timer’s register TH. IE1: The bit 3 is allotted as an External interrupt 1 Edge flag. It is not
After TH is loaded with 8 bit value, the 8051 gives a copy of it used in timer operations.
to TL. Then the timer must be started. It is done by the instruction IT1: The bit 2 is allotted as a External interrupt1 signal type control
“SETB TR0” for timer 0 and “SETB TR1” for timer1. bit. This bit is Set to be 1 by program to Enable the external interrupt 1
Mode3- Mode 3 is also known as a split timer mode. Timer 0 to be triggered by a falling edge signal. This bit is Set to be 0 by
and 1 may be programmed to be in mode 0, 1 and 2 independently of program to enable a low-level signal on external interrupt1 to generate
similar mode for other timer. an interrupt.
TCON register- Bits and symbol and functions of every bits of IE0: The bit 1 is allotted as an External interrupt 0 Edge flag. It is not
TCON are as follows: used in to timer operations.
IT0: The bit 0 is allotted as an External interrupt 0 signal type control
bit. Perform same function as IT1.

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 Falling edge triggered
External interrupts in 8051

 8051 has two external interrupt INT0 and INT1. Whenever falling edge is detected on the INT0/INT1 pin while

 8051 controller can be interrupted by external Interrupt, by global and ext. interrupts are enabled, the controller jumps to interrupt

providing level or edge on external interrupt pins PORT3.2, service routine (ISR) to serve interrupt.

PORT3.3.
8051 MCU Interrupt priority
 External peripherals can interrupt the microcontroller through
these external interrupts if global and external interrupts are Priority to the interrupt can be assigned by using the interrupt
enabled. priority register (IP)
 Then the microcontroller will execute current instruction and Interrupt priority after Reset:
jump to the Interrupt Service Routine (ISR) to serve to
interrupt. Priority Interrupt source Intr. bit / flag
 In the polling, method the microcontroller has to continuously 1 External Interrupt 0 INT0
check for a pulse by monitoring pin, whereas, in the interrupt
2 Timer Interrupt 0 TF0
method, the microcontroller does not need to poll. Whenever an
interrupt occurs microcontroller serves the interrupt request. 3 External Interrupt 1 INT1

4 Timer Interrupt 1 TF1

8051 mcu has two types of external interrupts of activation level
5 Serial interrupt (TI/RI)
1. Edge triggered (Interrupt occur on rising/falling edge detection)
2. Level triggered (Interrupt occur on high/low-level detection)

In the table, interrupts priorities upon reset are shown. As per 8051
In 8051 mcu, two types of activation levels are used. These are,
interrupt priorities, the lowest priority interrupts are not served until the
Low level triggered microcontroller is finished with higher priority ones. In a case when
two or more interrupts arrive microcontroller queues them according to
Whenever a low level is detected on the INT0/INT1 pin while
priority.
global and external interrupts are enabled, the controller jumps to
interrupt service routine (ISR) to serve interrupt. IP Register: Interrupt priority register

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 8051 interrupt vector table
8051 has an interrupt priority register to assign priority to interrupts.
Vector Address: This is the address where the controller jumps after
the interrupt to serve the ISR (interrupt service routine).

Interrupt Flag Interrupt vector address

Bit 7,6,5 – Reserved bits.
Reset - 0000H
Bit 4 – PS: Serial Interrupt Priority Bit
INT0 (Ext. int. 0) IE0 0003H
1 = Assign a high priority to serial interrupt.
Timer 0 TF0 000BH
0 = Assign low priority to serial interrupt.
INT1 (Ext. int. 1) IE1 0013H
Bit 3 – PT1: Timer1 Interrupt Priority Bit
Timer 1 TF1 001BH
1 = Assign high priority to Timer1 interrupt.
Serial TI/RI 0023H
0 = Assign low priority to Timer1 interrupt.
Reset
Bit 2 – PX1: External Interrupt 1 Priority Bit Reset is the highest priority interrupt, upon reset 8051 microcontroller

1 = Assign high priority to External1 interrupt. start executing code from 0x0000 address.
8051 Internal interrupt (Timer Interrupt)
0 = Assign low priority to External1 interrupt.
8051 mcu has two internal interrupts namely timer0 and timer1.
Bit 1 – PT0: Timer0 Interrupt Priority Bit Whenever timer overflows, timer overflow flags (TF0/TF1) are set.
Then the microcontroller jumps to their vector address to serve the
1 = Assign high priority to Timer0 interrupt.
interrupt. For this, global and timer interrupt should be enabled.
0 = Assign low priority to Timer0 interrupt. 8051 Serial interrupt
Bit 0 – PX0: External0 Interrupt Priority Bit 8051 mcu has a serial communication port and have related serial
interrupt flags (TI/RI). When the last bit (stop bit) of a byte is
1 = Assign high priority to External0 interrupt.
transmitted, the TI serial interrupt flag is set, and when the last bit (stop
0 = Assign low priority to External0 interrupt. bit) of the receiving data byte is received, the RI flag gets set.

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IE register: Interrupt Enable Register 0 = Disable Timer0 interrupt

IE register is used to enable/disable interrupt sources. Bit 0 – EX0: Enable External0 Interrupt Bit

1 = Enable External0 interrupt

0 = Disable External0 interrupt

Bit 7 – EA: Enable All Bit

1 = Enable all interrupts

0 = Disable all interrupts

Bit 6,5 – Reserved bits

Bit 4 – ES: Enable Serial Interrupt Bit

1 = Enable serial interrupt

0 = Disable serial interrupt

Bit 3 – ET1: Enable Timer1 Interrupt Bit

1 = Enable Timer1 interrupt

0 = Disable Timer1 interrupt

Bit 2 – EX1: Enable External1 Interrupt Bit

1 = Enable External1 interrupt

0 = Disable External1 interrupt

Bit 1 – ET0: Enable Timer0 Interrupt Bit

1 = Enable Timer0 interrupt

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