2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT) | 978-1-7281-5791-7/20/$31.

00 ©2021 IEEE | DOI: 10.1109/ICAECT49130.2021.9392518

Assertion & Functional Coverage Driven

Verification of AMBA Advance Peripheral Bus
Protocol Using System Verilog
Prashant Dwivedi, Neha-Mishra and Amit-Singh-Rajput
1
UTD CSVTU, Bhilai/BIT Durg, Chhattisgarh, India
2
Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat, India.
E-mail: [email protected], [email protected]

Abstract: Abstract— Design and Verification of the AMBA verification flow. HDL’s like Verilog and VHDL has
based Advanced Peripheral bus is presented in this paper. made functional coverage analysis even more inarticulate
Verification environment is constructed using the System as these HDL’s were realized with a hardware design point
Verilog, it has features like Functional coverage, Assertion of view, this motivated for the formation of new HDL well
coverage, constrained Randomization and Code coverage.;
suited for verification as well designing. System Verilog
Functional coverage makes sure that Hardware Descriptive
Language (HDL) Code written performs all the functionality was introduced for solving the above mentioned problems,
described in the Design specification; Code coverage shows it has all the constructs of an HDL as well as many other
total RTL codes is covered by the test cases. Assertions are features of the data structure languages like C++ and Java,
used as additional checkers for making sure there are no of which OPPS in the most prominent feature included in
protocol violation in the designed protocol. APB 4.0 protocol System Verilog [3]. Data structure features facilitates to
is completely designed and verified, there is no data loss in write test cases at higher level of abstraction thud can help
the designed system, AMBA’s APB is used for low power in modeling tangled data types also. AMBA is an generic
low-cost interfacing of high speed and low speed Systems. open-source communication protocol which can be used to
This paper focuses on APB protocols verification and covers
coordinate communications among countless IP’s
all the internal transactions of the APB protocol, complete
cycle for designing of the verification environment is (Intellectual Properties), sub-blocks and blocks in any SoC
discussed in detail, the designed system can be successfully (System on Chip) device [5].
implemented in any Microcontroller system having very
high and low speed peripherals. Designing is done by Verilog Highly complex design structure of the Integrated circuits
HDL using Mentor graphics tools Questa and Precision Pro based on reusability of IP’s demands for the need of a
is used for simulation of the Verification Environment OCB (on chip bus) protocol which can be compatible with
respectively. 100 percentage Functional coverage with 1030 all kinds of IP’s, due to this many OCB’ were introduced
Bins & 97 percentage code coverage is achieved. like Core-connect from IBM, AMBA from ARM [9],
Silicon-Black from Sonics. Among different OCB’s
Index Terms—– RTL (Register transfer logic), DUT (Design
under test), System Verilog, Functional coverage, Code AMBA is most widely used standard bus due to its
coverage, SOC (System on chip) flexibility in Arbitration, BUS width and Mode of Data
transfer [5]. AMBA bus protocols are defined to achieve
I. INTRODUCTION higher performance in the modern-day microcontrollers
following are some major AMBA buses.
Today due to huge progress in the VLSI technology the  Advanced extensible interface (AXI)
era of System on chip integrated circuits has come which  Advanced high-performance Bus (AHB)
has enabled integration on few million transistors in a  Advanced peripheral Bus (APB)
single chip [1], due to this SoC vverification has become  Advanced system Bus (ASB)
very cumbersome task in the field of Electronic System  Advanced Trace Bus (ATS)
design and verification. Around 65 to 75 percent of the
total SoC design period is consumed by its HDL design II. AMBA APB SYSTEM
and verification so formation of test cases with very
precise corner cases from the design specification is highly Advance Pheripherial Bus System
desirable but is very lengthy and time consuming so there Advance Peripheral Bus is for easy and fast interfacing of
is always a trade-off between complex functional coverage any low power and low bandwidth peripherals which are
and short time to design the test cases [5]. The fast- not high-performance systems as compared to their
growing electronics market with ephemeral time to market pipelining-based counterparts and is used for the general-
demands products which are well verified and are accurate purpose low power and low speed peripheral devices [5].
as the system specification are to be released in a very The APB bridge is the master for the slave peripherals
short period of time thus it demands for rigorous UART, Timer, Keypad, PIO. High speed devices are

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connected with AHB/AXI/AHB ect. as shown in Fig. 1., speed & low speed system peripherals for example if 5
data transfer between the high-speed devices and low high speed RAMS & small 25 low speed devices are to
speed peripherals takes place through APB bridge that communicate data then for the RAMs to access the low
acts a slave for any high speed AMBA Bus and acts as a speed devices would require a high-capacity Mux operated
master for the low power, low speed peripheral devices. at low frequency which would dissipate extra power and
Easy Data or Command transfer takes place via APB as it would require hugh decoding time, instead we can use the
can provides low-cost interface and reduced power combination of RAM’s connected to high speed Bus, ABP
consumption with less complex interfacing. If any high Slave connected to low speed devices and APB Master
speed bus say AHB is directly interfaced with large coordinating the overall data transfer, this would save both
number of slow peripheral devices it will require huge power and processing time. As only one master exists as
amount of multiplexing which will be reducing the overall per the AMBA APB protocol so this system does not
performance and would consume high amount of power require any Arbiter to coordinate. APB master is
so AHB can be interfaced with these slow devices responsible for driving all the Address & Write Buses and
through APB bus, Advance Peripheral Bus solves the also does combinatorial decoding of the input address and
problem by dividing and transferring the data bust and makes sure the communication is established with the
decoding them in multiple steps by transferring the data desired peripheral through APB Slave.
burst at all the rising edges of the system clock thereby
avoiding loading of the main system bus. APB is APB Master is also responsible for coordination of proper
compatible with large number of other protocols like timings and for the data transfer as it controls the
AXI, high speed AHB Light, ASB, Wishbone ect, [7]. PENABLE signal as shown in Fig 3, it is also responsible
Following are key features of APB protocol. for read data operation between the high-speed system bus
& low speed peripherals, as per the APB protocol rule all
the Data & Address transactions occur on the rising edge
of the system clock. Figure 3 shows various input and
output signals transactions of the APB Master-Slave
systems

Fig. 1. Advance microcontroller bus design

 Low power consumption

 Reduced interface complexity
 Latched Address and control
 Suitable for many peripherals

APB Master connects high-speed bus & APB Slave is

responsible for coordination with the low power and low
speed peripheral devices. Slave serves all the low-speed
peripherals based on the directives from the APB Master.
APB Master keep the high-speed bus in wait state until it Fig. 2. APB Bridge State Machine
severs the low-speed peripherals and allows the high-speed
Buses to Burst data or read data when it is in idle state as Figure 6 shows FSM diagram for mode of data transfer in
shown in APB Bridge State diagram Fig 2. the Advance Peripheral Bus protocol, below is small
description of various states involved in the data transfer
APB Protocol Communication process.
APB uses massive memory Input-output Access
methodology, major use of this protocol is interfacing of IDLE: - This is the state when no task is being performed
low & high speed protocols, APB master is connected by the peripheral and the bus.
with high-speed Bus protocols & on the other side it is SETUP:- It is the state of the bus when data transfer takes
connected to APB Salve which controls low power and place. In the SETUP state the PSELx select signal
low speed peripherals like FIFO, Timer, UART ect., the becomes active. For only one clock cycle the bus remains
designed and verified bus protocol is compatible with all in the SETUP state and bus always moves to the ENABLE
the AMBA’s 4.0 & older version protocols, APB Master- state at the onset of next clock edge.
Salve system make sure that the main system Bus is not ENABLE: - Assertion of PENABLE, the enable signal
loaded due to difference is operating speed of the high- commences the ENABLE state when there is transition

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from the SETUP to the ENABLE state, all the signals binds the whole test environment. as shown in Fig 4 the
related to writing or reading of data, address and selection- whole test program environment is composed of different
based signals are active during the state transitions phase. classes which are connected together to form the
In normal conditions this state lasts only for one clock verification environment. The Generator class is used to
cycle but if the transfer request is for higher amount of generate constrained random vectors. These test vectors
data then bus moves back to the SETUP state and comes are sent to the Driver via mailbox through which it
back to ENABLE sate after fetching next address or data, stimulates the DUT.
this process continues until all the desired data is
transferred. For instance, if the protocol has to write data
from a high-speed bus to a low-speed peripheral then there
will be two ways to do so i.e one with a wait sate and
without wait state. If small data bust is required to be
written then write without wait state option is used else if a
higher amount of data burst is required then write with
wait states option is utilized. Write operation starts with
arrival of all the data, address and selection related signals
at the same rising edge of the clock, this clock phase is
termed as the Set-up phase, second state called as the
Enable state starts where the enable signal PENABLE
signal is asserted. Data, address and all other control Fig. 4. System Verilog Verification Environment
signals together make sure that data transfer occurs at the
end of the clock cycle of Enable phase, there is read with Monitor generates verification reports on states,
and without wait states depending upon quantity of Data transaction and model messages. Results can be checked
that need to transferred, all these cases are simulated and by the checker and is added to the coverage report. As
corresponding waveforms are shown in the Result section. shown in Fig 4 the test environment consists of three parts.
Design specification clearly defined that read and write First is the DUT, which is the design to be verified.
modes should include wait states if the data transfer Second is the test program which is implemented using
between the bus and peripherals is required for more than System Verilog consisting all the test cases. Third is the
one clock cycle. Interface in between command & signal layer which is
used to connect DUT and test program. This verification
environment is reusable and can be repeatedly used to
write as many tests as possible using minimum amount of
code for DUT verification of numerous peripherals with
APB bus protocols. Execution flow of the verification is
shown in Figure 5 which shows all the steps required for
the formation of the test environment, this same flow is
always followed for designing verification environment
for any RTL and hence is reusable.

Fig. 3. APB Master-Slave Signal Transactions

III. TEST ENVIRONMENT

The major work of the Testing environment is to apply

stimulus to the given HDL Design and use the generated
results to verify correct functionality and dynamically
change the test cases according to the generated coverage
report. System Verilog performs this process easily and
accurately Fig 4 shows the block diagram of verification
environment formed using System Verilog, this
environment includes DUT written using VHDL/Verilog
HDL with System Verilog based testing environment
which includes Interface block, simulation top module that Fig. 5. Test Verification Environment Formation Steps

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 IV. ASSERTION BASED VERIFICATION V. SIMULATION & RESULTS

Assertions have great importance when used for the Fig 10 and Fig 11 shows RTL Schematic for APB Master
Verification of very complex Design Under Test (DUT). and APB Slave, Fig 12 Shows the Area report for the
Assertions are very powerful tool for verification because whole protocol RTL design, RTL code for APB Master &
they remove the necessity of complex Visual Waveform Slave is synthesized using Mentor Graphics tool Precision
debugging. Waveform debugging are recumbent to human Pro Fig 7 shows the waveform for simultaneous read and
error and are not suitable for complex designs. Assertions write operations between the APB slave & APB Master.
have a way of checking the anticipated results Fig 8 & Fig 9 shows the read and write with wait states,
automatically and are used for checking for any possible all waveforms have been generated using Mentor
Protocol violation in the APB 3 DUT. Figure 15 in result Graphics tool Questa. Fig 15 shows the Assertion
section shows an example of the Assertion waveform waveform making sure that the test bench covers all
generated for the APB Design Under Test (DUT). critical test corners.

Assertions given below are written for the verification of

the transfer modes, below assertions makes sure that two
back-to-back consecutives read or write occur as per the
protocol communication rules, similar assertions are
written to make sure that none of the protocol rules are
violated by the designed Advance Peripheral Bus HDL
code.

Fig. 7. Read and Write States

Fig. 6. FSM showing various states of APB Bus Fig. 8. Read with wait state

#cover property for b2b_rd

Apb_r :cover property (@posedge pclk)(!pwrite) ##2
(!pwrite));

# cover property for b2b_wr

Apb_w:cover property (@(posedge pclk) (pwrite )## 2
(pwrite));

It can be observed in the above two assertions shown that

all the checks are made at the positive edge of the clock
cycle occurrence of an assertion is marked at the top of the
assertion waveform this can be seen in the Fig. 15. which
Fig. 9. Write with wait state
shows a typical example of the result waveform generated
in response of various test cases.
Coverage analysis is done for APB3 slave using Questa
both Code coverage and Functional coverage have been
done, Fig 14 shows the Code coverage for the DUT

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overall 97 percent of codes are covered by the Verification
Environment, all 15 out of 15 Statement Coverage Bins are
covered, 12 out of 13 Branch Coverage Bins are covered, 79 out
of 80 Toggle Coverage Bins are covered by the Test
Environment, any coverage above 95 percent is considered
as very good [3]. A 100 percent Functional coverage is
achieved as shown in the Fig 13 and is generated using
1030 BINS, greater the total number of BINS better is the
reliability of the Functional Coverage.

Fig. 13. Functional Coverage Results

Fig. 10. Schematic for APB Master RTL

Fig. 14. Code Coverage Results

Fig. 11. Schematic for APB Slave

Fig. 15. Assertion Check Waveform

VI. SUMMARY

In this paper Design and Verification of Advance

Peripheral Bus protocols is done using System Verilog
Environment, the design includes all kinds of read and
writes states as defined in specification. High level
Functional coverage is archived due to inclusion of more
than thousand BINS in the functional coverage. A good
percentage of Code coverage for the DUT has been
archived, Assertions are written to make sure none of the
protocol rules are violated. This design can be used in any
Fig. 12. Area Report for the RTL Design
modern microcontroller system without any data loss.

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