2022 IEEE 2nd International Conference on Mobile Networks and Wireless Communications (ICMNWC)

The Configuration and Verification Analysis of

AMBA-Based AHB2APB Bridge
2022 IEEE 2nd International Conference on Mobile Networks and Wireless Communications (ICMNWC) | 978-1-6654-9111-2/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICMNWC56175.2022.10031928

1st Niharika BH 2nd Ramesh S

Dept. of Electronics and Communication Engineering Dept. of Electronics and Communication Engineering
Dr. Ambedkar Institute of Technology Dr.Ambedkar Institute of Technology
Bangalore, India Bangalore, India
[email protected] [email protected]

Abstract—To strengthen the IP core's reusability, AMBA is most notable one in System Verilog[4]. Data structure features
the on-chip bus architecture used widely for interconnection can assist in modeling tangled data types and make writing test
standards of SOC. In AMBA Architecture, Advanced High- cases at higher abstraction levels simpler.
performance Bus is connected to an ARM control unit, memory
interface, digital signal processing(DSP) and an Advanced ARM announced the release of the AMBA 4.0 specs on
peripheral bus used to connect to a timer, UART, keypad, and March 8th, 2010. The AMBA bus, which is an efficient SoC
PIO. A bridge is a standard bus-to-bus interface that helps to design, frequently makes use of the mandated industry-
build the communication gap between AHB and APB. Another standard SoC bus. For building high-performance embedded
importance of constructing a bridge is to avoid data loss when microcontrollers, the AMBA standard specifies an on-chip
data transfer is initiated. So keeping this in mind, the up- communication standard.
gradation in technology, tools and methodologies has made the
need for advancement in the verification environment. In this
paper, presents the design and verification of the AMBA-based
AHB2APB Bridge. The verification environment is developed in
the Questa-sim simulator. To verify the functional and code
coverage multiple test cases like Increment, Wrap Read and
write cycles with different bit sizes of 4,8,16 bits are done, and
100 percent Functional & 97 percent code coverage are
achieved.

Keywords—AHB2APB Bridge, System-On-Chip(SOC), UVM Fig. 1. A Simple AMBA Bus

Verification, Questa-sim.
In the above fig 1, an open-source communication
I. INTRODUCTION protocol that unifies communications between various IPs
A single chip can contain over a million transistors thanks (Intellectual Properties) and blocks in any System-on-chip
to the remarkable advancements in VLSI technology, which device[3]. In AMBA Architecture, Advanced High-
allows for creation SoCs (System-on-Chip). The term "chip," performance Bus is connected to an ARM control unit,
which describes the fusion of all electronic parts in a computer memory interface, digital signal processing(DSP), and an
or other device into a single chip, has entered the IC era. It Advanced peripheral bus used to connect to a timer, UART,
might have functions that are digital, analogue, mixed-signal, keypad, and PIO[5][8-11]. A bridge is a standard bus-to-bus
and frequently radio-frequency. The maximum percent of the interface that helps to build the communication gap between
total design time goes into the HDL design and verification of AHB and APB.
an SoC, necessitating the development of test cases. Highly The five interfaces are enumerated in the AMBA 4.0
desirable cases from the design specification are those that are specs; examples of advanced bus technologies include an
extremely precise. Because it is lengthy and time-consuming, advanced extensible interface (AXI), an advanced system bus
there is always a market between intricate functional coverage (ASB), an advanced peripheral bus (APB), and an advanced
and a finite amount of time to design the test cases [1].As the trace bus (ATB)[14-20].
system specification is succinctly released, the rapidly
expanding electronics market demands well-verified and The main objective of this design is to link the high-speed
precise products. [2]; thus, it requires a stringent verification ARM Microprocessor and other AHB components with the
flow. This paper utilizes the Universal Verification low bandwidth peripherals on APB; an AMBA-based
Methodology to verify AMBA [3][13] based AHB2APB AHB2APB bridge is necessary. This paper focuses on
Bridge's functionality. In our outcome, we plan to use a synthesizing and designing an AHB2APB bridge and
Questasim-based RTL (Register Transfer Level) validates the design and verification analysis carried out.
configuration code and UVM[4] for Verification. Synthesis
The following sections provide an overview of this paper:
and verification were accomplished using the Questa sim
Section two provides a depth description of the AHB and APB
simulator only. Functional coverage analysis has become even
protocols; the third Section presents the internal structure of
more imprecise as a result of Hardware Design Languages
the AHB2APB bridge; the following Section explains a basic
(HDLs) like Verilog and VHDL that adhere to a hardware
explanation of the Universal Verification Methodology
design perspective. As a result, the author provided inspiration
(UVM), which also sheds light on the system that is proposed
for the creation of a new HDL that is both well-designed and
for this paper; this final Section describes the important part
well-suited for verification. The above-mentioned issues were
of the paper, which is the result and its discussion with
resolved by the introduction of System Verilog. It includes
appropriate waveforms; and VI Section concludes.
many features from data structure languages like C++ and
Java as well as all the HDL constructs, with OPPS being the

978-1-6654-9111-2/22/$31.00 ©2022 IEEE

Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:11:36 UTC from IEEE Xplore. Restrictions apply.
 II. LITERATURE REVIEW
T. Koundinya et.al proposed AMBA9[1], an on-chip bus
topology, which has been discussed by the author in this work.
It is challenging to evaluate embedded systems that use
AMBA. A challenging interface between both the Modern
High Bus and the Advanced Peripherals Bus called the
AHB2APB Bridge is the subject of this study (APB). In this
article, the bridge module's synthesizing netlist is built. They
do functional and timing simulations using Xilinx, Model-
sim, and Verilog HDL.
Prashant Dwivedi et.al has described the development, and
testing of the AMBA displayed in this study. System Verilog
is used to build the verification environment, which includes
capabilities like functionality, assertions coverage and code Fig. 2. AHB2APB Bridge
cover. The system has no loss of data as envisioned, thanks to
the meticulous design and verification of APB 4.0 protocols. In fig 2, AHB and APB are connected by AHB2APB. It
The whole process of developing the verification environment operates the APB periphery, buffers the addresses, control,
is covered and put into practice. Verilog HDL design is carried and information from the AHB, and then transmits the
out utilizing Mentor graphical tools. For the corresponding information along with a signal obtained to the AHB. Any
Verification Environment simulations, Questa and Precision frequencies and phase combinations between both the AHB
Pro are employed. With 1030 Bins and 97 percent code and APB clocks will function with the AHB2APB
coverage, 100% functional coverage is achieved[2]. communication. The AHB2APB transferred information
Cheng hai Ma et.al proposed the Advanced extensible during the write cycle from AHB to APB and during the
Interface 4.0 standards[3], which are part of the AMBA 4.0 reading cycle. Communication between the AMBA efficient
standards, which were released in March 2010. The standard bus and the AMBA peripheral bus[8]. It provides gating of the
chip bus has been established as the AMBA bus protocol. This addresses and controlling.
implies that an increasing number of current IPs should be An AHB slave is the AHB to APB bridge interface; APB
able to interface. The author develops the Intellectual Property accesses last for various amounts of time. Additionally,
(IP) core, which converts AXI4.0-lite transactions into APB because of their fixed one-word width, it is impossible to write
4.0 transactions. AXI bus, which offers great performance, to just an 8- bit portion of a 32-bit register[9][12]. APB
and APB domain, which offers low power, are connected via controllers do not necessitate PClock input that's because the
the bridge[11]. APB accessing is coordinated with an activated signal emitted
Perumalla Giridhar proposed that the AHB, the elevated by the AHB to APB bridge connection. Due to the fact that
bus in the AMBA family, is the subject of the author's APB peripherals are only strobed when accessed, they use
attention. AHB's concept and testing were presented; it can little power.
support one master and 4 slaves. AHB is developed in this There are five key construction components that make up
study, and it consists of essential building pieces such as the AHB2APB Bridge's architectural framework:
Master, Slave, Decoder, and Mux. Verilog is used to construct
the mux, decoders, slaves, and design master. Creation of the • AHB Master
Verilog system's verification environment (SV). The Mentors • AHB2APB Bridge
Graphics tool for advanced testing, Questa-Sim, simulations,
and validates the designs while also calculating code and • AHB Interface
functionality coverage options[4]. • APB FSM Controller
III. AHB2APB BRIDGE • APB Interface
Either handshaking signals or asynchronous FIFO are
IV. PROPOSED WORK
used in the bridge's design. AMBA supports a variety of bus
bridges and protocols, including ASB2APB[7], AHB2APB, This paper explains every term related to UVM and
and AXI to APB. The reduced power APB as well as the provides examples. The introduction of UVM segments
speedy AHB, are connected by the AHB to APB bridge, an occurs in the first phase. Some of the characteristics related to
AHB master. Transfers from reading and writing towards the UVM are introduced in the second stage, and UVM is used to
AHB are translated into correspondent transfers. Wait states assemble an environment from scratch in the final stage.
are added throughout an apb transfer because apb is not
pipelined. When the AHB must wait for the APB, it must fill
the communication gap between the high-bandwidth ARM
microprocessor in addition to other quick gadgets on the AHB
and the low-bandwidth peripherals on the APB[9].

Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:11:36 UTC from IEEE Xplore. Restrictions apply.
 creates packet and sends to score board and as well as it also
collects the functionality coverage report from the scoreboard.
The below fsm model in the fig 4 provides the working
procedure of the discussed design can be seen clearly that
when the HRESETn=1 signal is high the address initially in
the idle state(ST_IDLE) that is forwarded to respective read
or write operation with respect to the user specification. If user
wants to write a data them AHB_valid signal=1 with
Hwrite=1 so the data is written in the AHB. And parallely
during read operation is indentified then AHB_valid=1 and
Hwrite=0 then data is read from the APB. This AHB_write
and APB_read transaction is initiated when signal Pready=1
or else if Pready=0 then it will remain in the same previous
state. After completion of the APB transaction when done
signal goes high again it comes to idle state with
HRESETn=0.
Fig. 3. Proposed Architecture of AHB2APB Bridge

In the ahb apb bridge uvm fig 3, shown above, there is a

test case called the ahb base test, which is a collection of test
cases. We build the main class environment inside that test
case. The command allows the user to specify which case
should be handled right away[10]. There will be numerous
agents in the environment, but in the proposed model, there is
only the ahb agent, which consists of the following classes are
ahb_master_driver it drives the randomized data in the
sequence to AHB bridge with some set of protocols defined
by the user. Whatever the received read data from rtl is get
back to ahb_master_driver, and following to the driver,
ahb_master_sequencer identifies which agent should run and
which ahb bridge should be drive. every sequence inside the
test case, the user wants to tell to drive the uvm pitch agent, so Fig. 4. FSM for AHB2APB Bridge
in a single AHB master-slave, this sequencer module is not so
important in this design it plays a major role in multiple agent V. RESULTS AND DISCUSSION
designs. This section describes the results and the purpose of
functional verification, the Bridge Structure performs both
The sequenced data is forwarded to the
read and write operations using UVM techniques. So the
ahb_master_monitor class in which master monitor will
complete code and functional coverage are obtained from the
receive the both ahb and apb transactions and whenever valid
RTL design verification. Bridge Functional Verification
AHB and APB data occurs it just converts onto data packet
Using UVM. A verification methodology is crucial to the
which is sent to the scoreboard. Monitor also contains
circuit design process shown in fig 5.
functional coverage unit that will tells what are the things
covered like increment and wrap with all the sizes for[12]
eg:4,8,16 bits functionality coverage. Scoreboard waits for the
AHB master and APB packet to arrive once it is received by
the scoreboard it compares both the packets and tells whether
it is converted properly from AHB to APB transactions. For
the design it needs a one interface to connect RTL design
because to interface the DUT and verification environment.
Environment consists of test cases, a simulation of the RTL
top module, a DUT written in Verilog HDL, and a testbench
in the System Verilog interface. The top test bench
architecture will be kept by one or more agents. It will connect
to the environment component if there are multiple agents.
How the scoreboard is connected to another component in a
way that the agents.
Whenever master_driver drives data through the virtual
interface by creating the interface in top file in the testbench
and set that using uvm object details. Same details reflected in
both driver and rtl interface[6]. Whatever random data is
present is driven though virtual interface to rtl. Also waits for Fig. 5. AHB2APB Bridge Schematic
the response from DUT and after getting the result it proceeds
for the next transaction. In monitor when ahb and apb signals The Bridge's read-and-write operations with the test cases
occurs it just monitors both when valid signal received it are in the increment test case; it checks the design, which is

Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:11:36 UTC from IEEE Xplore. Restrictions apply.
doing a proper incrementing operation of count increments 4,8
and 16 bits. In the wrap test case, it enquires that the data
address reaches the specified maximum bound(wrap) in
4,8,16 bits of a data address. For RTL design, the quest sim
10.2b simulator is used in Verilog; further UVM verification
for more in-depth Validation of code functionality in system
Verilog.
The AHB and APB input signals with the corresponding
output signals linked to the inputs are represented in the
behavioral simulation result of the increment 4 write
operation. The overall operation is enabled with the sequential
HBURST=3 signal when HRESETn=1 and HSIZE=2 will
specify the size of the transmitting data. When a transaction is Fig. 8. Wrap_4_Write waveform
invalid, the HTRANS signal is HADDR, which provides
information about the address for the specific data, and In the below fig 9, the test case wrap 8 read operation,
HTRANS=0 otherwise (valid transaction). HWRITE is which reads data from the APB protocol to AHB, is depicted
another crucial parameter signal that lets you know whether in the waveform above. When HWRITE=1 and HSIZE=2, the
the current operation is writing to or reading from AHB. data contains an HRDATA that reads data and an increment
Therefore, if HWRITE=1 then a write operation has been of 4 bits from the previous HADDR. The claim that PSEL=1
performed. HWDATA was asserted with the HREADYOUT and PENABLE=1 are true.
signal toggled. The main thing to look for in the waveform
window is the test case of increment 4, which shows the same
AHB data being transferred to APB without any data loss,
with the APB input signals PRESETn=1 asserted with
PADDR, PENABLE=1 with PSEL=1 signal made high, and
PSTRB=3 of size with PWRITE operation shown in the below
fig 6 and 7 with write and Read operation.

Fig. 9. Wrap_8_Read Waveform

The fig 8 informs how the proposed RTL functions are

provided in the coverage analysis and coverage description.
Both functionality coverage and code coverage are conducted
to the model as part of the coverage study for the AHB2APB
Fig. 6. Increment_4_Read Waveform bridges utilizing the Questa-sim simulation. The below steps
show how to create a functional coverage report in Questa sim.
After running the RTL program, the coverage report will
show, in which out of 67 bins, almost all 67 hits are covered
so by getting 100%. We can see the functional coverage
report, which has achieved in fig 10.

Fig. 7. Increment_8_Write Waveform

Wrap denotes the 32-bit memory panel, which we used for

our project. As a result, in a 32-bit panel, the address should Fig. 10. Functional and Code Coverage Report
repeat every 32 bits along with the boundary before the data is
wrapped. When HSIZE=1, a half-word with an increment of VI. CONCLUSION
plus two bits to the previous HADDR with the corresponding The fundamental difficulty is in connecting high-
HWDATA is written to the AHB in the waveform fig 7. peripheral and low-powered devices in system-on-chip (SOC)
architecture. This is essential to obtain error-free data and to
prevent data loss during transmission. As a result, the AHB to

Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:11:36 UTC from IEEE Xplore. Restrictions apply.
APB Bridge is designed in Verilog HDL and implemented in [7] Sandeep Jagre, Dr. Neelesh Gupta, Prof. Nishi Pandey, "Design and
this study to make the AHB and APB devices a low-power Implementation of AMBA APB Bridge with Low Power
Consumption," IJSTE - International Journal of Science Technology &
consuming system. HCLK and PENABLE signal mechanisms Engineering, Volume 4, Issue 2, August 2017.
were also implemented. The capability Several test cases, [8] Ankem Kiran, v Thrimurthulu, “VERIFICATION OF AMBA
including read transfer, write transfer, read increment and AHB2APB BRIDGE USING UNIVERSAL VERIFICATION
wrap transfer, and write wrap and increment transfer, were METHODOLOGY (UVM)”, International Journal in IT and
driven in order to verify the Bridge's functionality. The AHB Engineering, Vol.04 Issue-12, December 2016.
to APB bridge will be implemented in the future with [9] Priyanka M Shettar1, Ashwin Kumar “Verification IP of AMBA AXI
numerous masters and numerous slaves. The AHB and APB V1.0 Using UVM”. IOSR Journal of VLSI and Signal Processing
(IOSR-JVSP) Volume 6, Issue 3, Ver. II (May -Jun. 2016), pg. 54-58.
interface could be modified to work with additional AMBA
[10] Heli Shah, P Chinmay Modi, Bhargav Tarpara, "Design &
protocol versions, like ASB and AXI. And also will involve Implementation of Advance Peripheral Bus Protocol," International
implementing an interface between additional AMBA Journal of Scientific Engineering and Applied Science (IJSEAS) -
protocols and APB Volume-1, Issue-3, June 2015.
[11] Chenghai Ma, Zhijun Liu and Xiaoyue Ma, "Design and
ACKNOWLEDGMENT Implementation of APB Bridge based on AMBA 4.0”, School of
I would like to express my profound thankfulness Dr. Information Science and Engineering, Shandong University, Jinan,
China,2011 IEEE.
Ambedkar Institute of Technology in Bangalore for the
[12] Akhilesh Kumar and Richa Sinha, "DESIGN AND VERIFICATION
support. Additionally, I want to express my appreciation to my ANALYSIS OF APB3 PROTOCOL WITH COVERAGE”,
family and friends for their important assistance. International Journal of Advances in Engineering & Technology, Nov
2011.
REFERENCES [13] Anurag Shrivastava, GS Tomar, Ashutosh Kumar Singh, "Performance
[1] T. Koundinya,“Design and Implementation of AMBA-based Comparison of AMBA Bus-Based System-On-Chip Communication
AHB2APB Bridge”, on June 2022. Protocol," International Conference on Communication Systems and
Network Technologies,2011.
[2] Prashant Dwivedi, Neha-Mishra and Amit-Singh-Rajput, “Assertion &
Functional Coverage Driven Verification of AMBA Advanced [14] Jaehoon Song, Hyunbean Yi, Juhee Han, and Sungju Park, Member,
Peripheral Bus Protocol Using System Verilog,” (ICAECT) on May “An Efficient SoC Test Technique by Reusing On/Off-Chip Bus
25th, 2021. Bridge," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—
I: REGULAR PAPERS, VOL. 56, NO. 3, MARCH 2009.
[3] Bhagvati Panchal and Yogesh Parmar, "Implementation of AMBA
Based AHB2APB Bridge,” International Journal of Recent Technology [15] Kwang-Hyun Cho, Jaebeom Kim, Euibong Jung, "Reusable Platform
and Engineering (IJRTE) ISSN: 2277-3878 (Online), Volume-8 Issue- Design Methodology For SoC Integration And Verification," Design
6, March 2020. Technology Team, System LSI Division, Samsung Electronics,2008
International SoC Design Conference.
[4] Perumalla Giridhar , Dr Priyanka Choudhury ,“Design and Verification
of AMBA AHB”, NIT Agartala,2019,IEEE. [16] Han Ke, Deng Zhongliang and Shu Qiong “Verification of AMBA Bus
Model Using SystemVerilog." School of Electronic Engineering,
[5] L Deeksha, B. R Shivakumar “Effective Design and Implementation of
Beijing University of Posts and Telecommunications, 2007 IEEE.
AMBA AHB Bus Protocol using Verilog”. 2019 International
Conference on Intelligent Sustainable Systems (ICISS). [17] URL:http://www. Testbench. com.
[6] N.G.N.PRASAD “DEVELOPMENT AND VERIFICATION [18] AMBA Specification (Rev 2.0). http://www.arm.com
OFAHB2APB BRIDGE PROTOCOL USING UVM TECHNIQUE,” [19] ARM, "AMBA Specification Overview," http://www. arm. Com/.
International Journal of Scientific Research and Review, Volume 6, [20] URL: https://www.amazon.in/SystemVerilog-Verification-Learning-
Issue 12, 2017. TestbenchLanguage/dp/146140714

Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:11:36 UTC from IEEE Xplore. Restrictions apply.