MIPI I3C TECHNOLOGY

AN INTRODUCTION TO MIPI I3C

MICHAEL JOEHREN
SYSTEM ARCHITECT

AMF-DES-T2686 | JUNE 2017

NXP and the NXP logo are trademarks of NXP B.V. All other product or service names are the property
of their respective owners. © 2017 NXP B.V.
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AGENDA
1. Introduction
2. Basic MIPI I3CSM signaling and protocol
3. Bus signals and address arbitration
4. High Data Rate (HDR) modes
5. Error detection and recovery
6. Device Identifier – Provisional-ID
7. Common Command Codes (CCC)
8. NXP’s free MIPI I3CSM slave RTL
9. Summary
10. Public information

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01.
Introduction

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 MIPI I3C
MIPI I3C = Next generation from I2C no logo
yet
• MIPI I3C is a follow on to I2C
− Has major improvements in use and power and performance
− Optional alternative to SPI for mid-speed (equivalent to 30 Mbps)
• Background
− NXP (Philips legacy) is I2C leader and spec owner
− I2C is used predominantly as control and communication interface with a focus in sensors
(>90% according to 2013 MIPI Alliance survey)
− MIPI Alliance Sensor Interface Workgroup initiated an upgrade of requirements in 2013
• Rationale for upgrade
− In-band interrupt to reduce # of GPIO wires on SoC, as # of sensors increase on the mobile devices
− I2C speed has become limiting, as amount of data increases on the bus
− Upgrade Constraints
 Maintain backward compatibility, to enable a smooth transition from I2C to MIPI I3C and focus on simple implementation (recall I2C wide adoption is due to its seeming
simplicity)

• MIPI I3C Spec Contributors

− Primary Spec authoring: NXP (Paul Kimelman), Qualcomm, Intel, other contributors: Invensense, TI, STM, Synopsys,
Cadence, Mentor, Sony, Knowles, Lattice
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Sensor Interface Block Diagram
 In addition to higher data rate of the main interface,
side-band channels such as dedicated interrupts, enable, and sleep signals might be needed
 Increased number of GPIOs is adding system cost in the form of added SoC package pins and PCB layer count
Current Scenario Desired Scenario

I2C and SPI devices with side MIPI I3C with in-band interrupt, Common
band channels EN, INT, etc Command Codes for device control

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Sensor Interface Block Diagram for MIPI I3C vs. I2C & SPI
Parameter MIPI I3C I2 C SPI
Overview

# of lines 2-wire 2-wire (plus separate wires for each 4-wire (plus separate wires for each
required interrupt signal) required interrupt signal

Effective Data 33.3 Mbps max at 12.5 MHz 3 Mbps max at 3.4 MHz (Hs) Approx. 60 Mbps max at 60 MHz for
Bitrate (Typ.:10.6 Mbps at 12 MHz SDR) 0.8 Mbps max at 1 MHz (Fm+) conventional implementations
0.35 Mbps max at 400 KHz (Fm) (Typically: 10 Mbps at 10 MHz

From MIPI I3C White paper: http://resources.mipi.org/MIPI I3C-sensor-whitepaper-from-mipi-alliance

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 MIPI I3C versus I2C at-a-glance
I 2C MIPI I3C
Fast mode: 400kb/s
SDR: up to 12.5Mbps raw rate (Actual Data Rate: 8/9th – per 1 byte)
Clock Speed Fast Mode+: 1Mb/s
HDR-DDR: Actual Data Rate 20Mbps – 1 word
& Data Rate High speed: 3.4Mb/s
HDR-TSP: Actual Data Rate to ~30Mbps – 1 word
Actual Data: computed 8/9th – 1 byte

2 – multi-drop (OpenDrain IF) 2 – multi-drop (SCL is push-pull, SDA OpenDrain and push-pull)
# wires SCL: clock – from Master(s), Slaves stretch SCL = clock (except for HDR-TSP) - from current Master only
SDA: data – bidirectional (OpenDrain) SDA = data – bidirectional (OpenDrain and push-pull)

Lower due to SCL being push-pull only and

Power High due to open-drain SCL , SDA
SDA working in push-pull most of the time

Slave Read Master has to end Read

Slave ends Read, but Master may terminate early
termination (so has to know length in advance)

In-Band
None – use a separate wire/pin per slave Integrated, prioritized, and may include a byte (or more) of context
Interrupts

Hot-Plug None. Proprietary systems only Built-in. Same mechanism a in-band-interrupt

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 MIPI I3C versus I2C at-a-glance
I 2C MIPI I3C
Error detection No protocol inherent error detection Master and slave side error detection features

Has to be done by master once separate Is an essential part of the MIPI I3C spec – no dedicated INT
Time stamping
INT signal is triggered signal required.

Built-in Built-in for control, capabilities discovery, bus management, etc.

None. Proprietary messages only
Commands Expandable: e.g. Time Control, IO Expander use

Master / Slave Master-Slave, Multi-master optional Master-Slave; Master handoff (old Master->Slave)

IO pads I2C special pads (e.g. 50ns spike filter) Standard pads 4 mA drive, no spike filter

Dynamically assigned during initialization.

Slave address Static
Slaves may have static address at start

Clocking Slaves normally use inbound clock Slaves use inbound clock (allows slow/no internal clock)

Low for Slaves. Slaves as small as 2 K gates

Complexity Higher for masters, especially around Masters as small as 2.5 K gates
multi-master State machine or processor implementations

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Advantages in energy and data rate

I2C I2C

I2C I2C

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MIPI I3C Devices Roles vs. Responsibilities
Roles
Responsibilities / Comments
Features Main Master Secondary SDR Only Main SDR Only Slave SDR Only
Master Master Secondary Master Slave
For Address Arbitration, In-Band
Manages SDA Arbitration Interrupt, Hot-Join, Dynamic Y Y Y Y N N
Address, as appropriate

Dynamic Address Assignment Master assigns Dynamic Address Y N Y N N N

Hot-Join Dynamic Address Master capable of assignment Y Optional Y Optional N N

Assignment Dynamic Address after Hot-join
Self Dynamic Address Only Main Master can self-assign a Y N Y N N N
Assignment Dynamic Address
Static I2C Address1 – N/A Optional N/A Optional Optional Optional
Memory for Slaves’ Addresses Retaining registers Y Y Y Y N N
and Characteristics
HDR Slave capable Supports being accessed in at Y Y N N Y N
least one HDR Mode
HDR Master capable Supports Mastering in at least one Y Y N N N/A N/A
HDR Mode
HDR Exit Pattern Generation Able to generate the HDR Exit Y Y Y Y N N
capable2 Pattern on the Bus for error recovery

HDR Tolerant Recognizes HDR Exit Pattern Y Y Y Y Y Y

1) A Static Address may be used to more quickly assign a Dynamic Address. See Section 5.1.4.
2) All Slaves require an HDR Exit Pattern Detector, even Slaves that are not HDR capable

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02.
Basic MIPI I3C signaling and protocol

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 So, what does an MIPI I3C message look like?
MIPI I3C SDR looks almost the same as I2C:
− E.g. Write data
− 1 bit 8 bits 1 bit 8 bits 1 bit … 1 bit
MIPI S or Sr Addr+W ACK/ 1 Byte T bit = More data Sr or P
I3C NACK data Parity
I2C ACK/
NACK

− E.g. Read data (typical approach):

1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bit 1 bit 8 bit 1 bit … 1 bit
MIPI S or Sr Addr+ ACK / 1 Byte T bit Sr Addr ACK / 1 Byte T bit = ‘1 then Z’ to More Sr or P
I3C W NACK data = +R NACK from continue data Master
Parity Slave ends read
‘0’ Slave ends
transmission
I2C ACK/ ACK/ NACK Master
NACK Slave can’t abort read ends read

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 Open drain address transmission followed by push-pull data
• Example:
- Master starts communication and allows arbitration (open-drain mode)
- Data is transmitted in push-pull mode

SDR Transfer

SDA
Master A6 A5 A4 A3 A2 A1 A0 RnW ACK D7 D6 D5 D4 D3 D2 D1 D0 T

SCL
Master
200ns
45ns Open-drain 4 MHz Push-pull 12.5 MHz

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03.
Bus signals and address arbitration

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 MIPI I3C Bus signal in SDR mode after dynamic address assignment

SDR Transfer

SDA
Master A6 A5 A4 A3 A2 A1 A0 RnW ACK D7 D6 D5 D4 D3 D2 D1 D0 T

SCL
Master 200ns
200ns
45ns Open-drain 4 MHz 45ns Push-pull 12.5 MHz

80ns

SCL high-period is <45 ns,

well below 50 ns glitch filter After ‘ACK’ the master
Start condition required by I2C, changes its SDA to push-pull
Enabling up to ~4 MHz mode and increases
Same as I2C
its clock to 12.5 MHz

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Why is address arbitration important in MIPI I3C
Address arbitration is used for multiple function in the MIPI I3C specification:
• In-Band Interrupt
− slaves
can trigger the master by pulling SDA low during a quiet period and the
master will starting its SCL (start condition)
• Hot-Join
• Bus initialization if not all slave addresses are known

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Address Arbitration
• System setup
− MIPI I3C only system
−2 slaves with In-Band Interrupt enabled
− BOTH slaves trigger an interrupt at the same time

MIPI I3C
Slave A6 A5 A4 A3 A2 A1 A0
with interrupt
1 0 1 1 1 1 1
enabled
Host SCL Addr: 7’h 5F
MIPI I3C SDA
master
MIPI I3C
Slave A6 A5 A4 A3 A2 A1 A0
with interrupt
1 1 1 0 1 1 1
enabled
Addr: 7’h 77 PUBLIC 16
 Address Arbitration
• Example: Interrupt triggered by slave in a system with 2 IBI capable slaves
A6 A5 A4 A3 A2 A1 A0
1 - - - - - -
1. Master is idle with SCL stopped and SDA
R_pu
being pulled high by resistor
SDR Transfer
SDR Transfer

SDA
2. BOTH Slaves trigger an interrupt by pulling
A6 A5 A4 A3 A2 A1 A0 RnW ACK D7
D7 D6
D6 D5
D5 D4D4 D3 D3 D2D2 D1
D1 D0
D0 TT
Master A2 A1
SDAA0low RnW ACK

SCL
3. Master starts SCL, pulling it low
Master
200ns
4. Slave releases SDA
45ns Open-drain 4 MHz 5. SDA is pulled high by R_puPush-pull
Push-pull 12.5
12.5 MHz
MHz

SDA
6. SCL pulse to latch address bit A6
Slave A6 A5 A4 A3 A2
A2 A1
A1 A0
A0 RnW
RnW ACK
ACK D7 D6
D7 D6 D5
D5 D4
D4 D3
D3 D2
D2 D1
D1 D0
D0 TT
7'77

SDA
Slave A6 A5 A4 A3 A2
A2 A1
A1 A0
A0 RnW
RnW ACK
ACK D7 D6
D7 D6 D5
D5 D4
D4 D3
D3 D2
D2 D1
D1 D0
D0 TT
7'5F

1 2 3,4,5,6

Actively driving device signal on bus PUBLIC 17

 Address Arbitration
• Example: Interrupt triggered by slave in a system with 2 IBI capable slaves
A6 A5 A4 A3 A2 A1 A0 1. Master is idle with SCL stopped and SDA
R_pu 1 0 1- 1- - - - being pulled high by resistor
SDR Transfer
2. BOTH Slaves trigger an interrupt by pulling
SDA
Master A6 A5 A4 A3 A2 A1 SDA low
A0 RnW ACK D7 D6
ACK D7 D5 D4
D6 D5 D4 D3 D3 D2D2 D1 D0 TT
D1 D0

3. Master starts SCL, pulling it low

SCL
Master
4. Slave releases SDA
200ns
200ns
45ns
45ns Open-drain 4 MHz
Open-drain
5. SDA is pulled high by R_pu Push-pull 12.5 MHz
Push-pull 12.5 MHz
6. SCL pulse to latch address bit A6
SDA
Slave A6 A5 A4 A3 A2 7.A1 SlaveA07’5F pulls
RnW A5 ACK
low.D7
ACK D7Latched
D5 D4
D6 D5
D6 D4 D3 with
D3 D1next
D2 D1
D2 D0 TT
D0
7'77 SCL pulse – slave 7’77 keeps listening
SDA
Slave A6 A5 A4 A3 A2 8.A1 SlaveA07’5F releases
RnW SDA
ACK so
D7 D6
ACK D7
A4D4 is
D5 D4
D6 D5
‘1’
D3 D2
D3 D2 D1 D0 TT
D1 D0
7'5F 9. Slave 7’77 does NOT communicate since
1 2 3, 4,5,6 7 8 9
A5 deviates from it’s address so it ‘lost’ the
arbitration and abstains from
communication untilPUBLIC the Start condition
Actively driving device signal on bus 18
 Address Arbitration
• Example: Interrupt triggered by slave in a system with 2 IBI capable slaves
A6 A5 A4 A3 A2 A1 A0
10. [A2:A0] are latched by master (‘111’)
 address 7’ 5F successfully transmitted
R_pu 1 0 1- 1- 1- 1- 1-
by slave
SDR to master
Transfer

SDA
Master A6 A5 A4 A3 A2 A1 A0 RnW ACK D7 D6 D5 D4 D3 D2 D1 D0 T

SCL
Master
200ns
45ns Open-drain 4 MHz Push-pull 12.5 MHz

SDA
Slave A6 A5 A4 A3 A2 A1 A0 RnW ACK D7 D6 D5 D4 D3 D2 D1 D0 T
7'77

SDA
Slave A6 A5 A4 A3 A2 A1 A0 RnW ACK D7 D6 D5 D4 D3 D2 D1 D0 T
7'5F

1 2 3, 4,5,6 7 8 9 11. Master changes over to push-pull operation

10 11
Actively driving device signal on bus PUBLIC 19
In-band interrupts
In-Band interrupt allows Slaves to notify the master
• Can be used as an equivalent function compared to a separate GPIO
• additionally, the IBI data frame can also be directly data bearing
• and an IBI is prioritized. The lowest dynamic address slave will gain highest priority during
arbitration
• Interrupts can be started even when Master is not active on the bus
• No free running clock required (lower power)
• Time-stamping option to allow resolution of time of initial event
• 2 ways to do: both relate to when actual IBI gets through to Master
Drive High or Low, Optional
Open Drain Hand Off Push-Pull Push-Pull
and then High-Z (push-pull)
Slave_byte
S Slave_addr_as_IBI/R Master_ACK SCL High T More bytes Sr
(‘mandatory byte’)

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Note: How to increase the speed of the arbitration process

When a master has determined the slave’s dynamic address triggering the in-band
interrupt, it can switch from open drain mode to push-pull mode for the next clock
cycle as no other slave shall temper with SDA.

Therefore, dynamic addresses differentiated through their MSBs rather than their
LSBs can be used.

A hot-join / hot-plug device will announce itself by issuing 7’b 0000_010.

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04.
High Data Rate (HDR) modes

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HDR modes for higher throughput
High data rate (HDR) modes are optionally available
• No faster clock, but more bits for same frequency
• Optional to support for Master and Slave
− Incapable slaves know how to ignore, so others may use safely
• May have an HDR-DDR format
− About 2x the data rate of SDR (so about 20 Mbps net using 12.5 MHz SCL)
− Also includes CRC
− Uses same SCL clocking, so small adder to Slave logic
• May use HDR-TSP (Ternary Symbols)
− Results
in up to 3x the data rate (so about 30 Mbps at 12.5 MHz) by using
symbols on SCL,SDA rather than separate clock and data
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05.
Error detection and recovery

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Error Detection and Recovery Methods
The MIPI I3C bus specification details error detection and recovery methods for an SDR
slave, the SDR master and HDR mode(s).
The error detection and recovery methods specified are provided in order to avoid fatal
conditions when errors occur.
A set of 6 mandated methods and 1 optional method are specified for MIPI I3C Slave
Devices, and a separate set of required methods is specified for MIPI I3C Master Devices.

Side note:
Clock stretching by slaves is NOT permitted
( SCL is driven via push-pull by the master)

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Device error types
Slave side errors Master side errors

Error Type Description Error Type Description

S0 Broadcast Address/W (=7’h7E/W) M0 Transaction after sending CCC
or Dynamic Address/RW
S1 CCC Code M1 Monitoring Error
(optional)
S2 Write Data M2 No response to Broadcast Address (7’h7E)

S3 Assigned Address during Dynamic Address

Arbitration
S4 7’h7E/R after Sr during Dynamic Address
Arbitration
S5 Transaction after detecting CCC

S6 Monitoring Error
(optional)

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06.
Device Identifier – Provisional-ID

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Device Identifier - MIPI I3C slave addresses
Device Identifier
In order to support the Dynamic Address Assignment procedure, each MIPI I3C Device to be connected to an
MIPI I3C Bus shall be uniquely identifiable in one of two ways, before starting the procedure.
1. The Device may have a Static Address, in which case the Master may use that Static Address
For example, an Address similar to what I2C specifies
2. The Device shall in all cases have a 48-bit Provisional ID.
The Master shall rely on this 48-bit Provisional ID, unless the Device has a Static Address used by the master.
The 48-bit Provisional ID is composed of three parts:
Bits [47:33] Bit [32] Bits [31:00]
[31:16] [15:12] [11:0]
16 bits 4 bits 12 bit
MIPI Provisional ID Type Part ID: The meaning Instance ID: Value to identify the This is left for definition with additional
Manufacturer ID Selector of this 16-bit field is individual example: straps, meaning. For example: deeper Device
(Note: MSB is 1’b1: Random left to the Device fuses, non-volatile memory, or Characteristics, which could optionally
discarded) 1’b0: Fixed vendor to define another appropriate method include Device Characteristic Register
values
If Bit [32] = 1’b1: Random Value:
Bits [31:0]: 32-bit value randomly generated by the Device.

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07.
Common Command Codes (CCC)

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Command space (CCC – Common Command Codes)
• Built-in Commands (>40) in separate “space” to avoid collision with
normal Master  Slave messages
− Controls bus behavior, modes and states, low power state, enquiries, etc.
− Has additional room for new built-in commands to be used by other groups
− Some are required, some are optional
− Some may be direct communication with a single slave or are broadcasts
to all slaves (same commands might be available in either category)

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08.
NXP’s free MIPI I3C slave RTL

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NXP’s free MIPI I3C slave
• NXP offers a free license for companies that are and are not members of MIPI:
http://www.nxp.com/webapp/software-center/library.jsp#/home/query/MIPI%20MIPI
I3C%20Slave%20IP%20for%20MIPI/~filter~/popularity/0
− Non-members must agree to a confidentiality clause from MIPI (a requirement of MIPI Alliance: http://mipi.org).
This IP is provided with no warranty, as must be agreed to in the click-wrap license.

Full commercial license

• Support and a full commercial license is available from Silvaco at
http://www.silvaco.com/products/IP/MIPI I3C.html

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09.
Summary

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Summary
• MIPI I3C simplifies system design to a true two-wire interface
• Backward compatible to existing I2C devices (Supports legacy I2C messaging)
• Very small RTL footprint requiring 2 pins only
• Lower power consumption than I2C
• Supports in-bound error checking and CRC
• Supports peer-to-peer slave communication
• Supports hot-plug capability
• Dynamic addressing while supporting Static Addressing for legacy I2C devices
• Supports I2C-like SDR messaging and optional HDR messaging (up to 30Mbps)
• Supports multi-master and multi-drop capabilities

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10.
Public information

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Publicly available information:
• White paper: http://resources.mipi.org/MIPI I3C-sensor-whitepaper-from-mipi-alliance

• Press release: https://mipi.org/content/mipi-alliance-releases-MIPI I3C-sensor-interface-

specification

• Commercially available IP (e.g.):

http://www.silvaco.com/news/pressreleases/2016_12_01_01.html

• Free license MIPI I3C (incl. I2C) slave IP from NXP:

https://www.nxp.com/webapp/Download?colCode=MIPI I3C-NXP-FREE-LICENSE-
SLAVE&amp;appType=license&amp;location=null&fsrch=1&sr=1&pageNum=1&Parent_no
deId=&Parent_pageType=&Parent_nodeId=&Parent_pageType
or go to: www.nxp.com and search for ‘mipi i3c slave verilog’

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From MIPI I3C white paper 1/3
Parameter MIPI I3C I2C SPI
Overview

# of lines 2-wire 2-wire (plus separate wires for each 4-wire (plus separate wires for
required interrupt signal) eachrequired interrupt signal
Effective Data 33.3 Mbps max at 12.5 MHz 3 Mbps max at 3.4 MHz (Hs) Approx. 60 Mbps max at 60 MHz for
Bitrate (Typ.:10.6 Mbps at 12MHz SDR) 0.8 Mbps max at 1 MHz (Fm+) conventional implementations
0.35 Mbps max at 400 KHz (Fm) (Typically: 10 Mbps at 10 MHz

From MIPI I3C White paper: http://resources.mipi.org/MIPI I3C-sensor-whitepaper-from-mipi-alliance

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From MIPI I3C white paper 2/3
Parameter MIPI I3C I2 C SPI
Advantages • Only two signal lines • Only two signal lines • Full duplex communication
• Legacy I²C devices co-exist on the • Flexible data transmission rates • Push-pull drivers
same bus (with some limitations) • Each device on the bus is • Good signal integrity and high speed
• Flexible data transmission rates independently addressable below 20MHz (higher speed are
• Dynamic addressing and supports • Devices have a simple master/slave challenging)

static addressing for legacy I²C devices relationship • Higher throughput than I²C and SMBus

• I²C-like data rate messaging (SDR) • Simple implementation • Not limited to 8-bit words

• Optional high data rate messaging • Widely adopted in sensor applications • Arbitrary choice of message size,
modes (HDR) and beyond content and purpose

• Multi-drop capability and dynamic • Supports multi-master and multidrop • Simple hardware interfacing
addressing avoids collisions capability features • Lower power than I²C
• Multi-master capability • No arbitration or associated failure
• In-band Interrupt support modes

• Hot-join support • Slaves use the master's clock

• A clear master ownership and handover • Slaves do not need a unique address
mechanism is defined • Not limited by a standard to any
• In-band integrated commands (CCC) maximum clock speed (can vary between
Support SPI devices)

From MIPI I3C White paper: http://resources.mipi.org/MIPI I3C-sensor-whitepaper-from-mipi-alliance

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From MIPI I3C white paper 3/3
Parameter MIPI I3C I2 C SPI
Disadvantages • Only 7-bits are available for device • Only 7-bits (or 10-bits) are available for • Need more pins than I²C/MIPI I3C
addressing static device addressing • Need dedicated pin per slave for slave
• Slower than SPI (i.e. 20Mbps) • Limited communication speed rates and select (SS)
• New standard, adoption needs to be many devices do not support the higher • No in-band addressing
proven speeds
• No slave hardware flow control
• Limited number of devices* on a bus to • Slaves can hang the bus; will require
system restart • No hardware slave acknowledgment
around a dozen devices
• Slower devices can delay the operation • Supports only one master device
of faster speed devices • No error-checking protocol is defined
• Uses more power than SPI • No formal standard, validating
• Limited number of devices on a bus to conformance is not possible
around a dozen devices • SPI does not support hot swapping
• No clear master ownership and • Requires separate support signals for
handover mechanism interrupts
• Requires separate support signals for
Interrupts

From MIPI I3C White paper: http://resources.mipi.org/MIPI I3C-sensor-whitepaper-from-mipi-alliance

* This means physical devices. Total bus capacitance <= 50 pF.

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11.
Q&A

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NXP and the NXP logo are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2017 NXP B.V.