List of MIPS architecture processors - Wikipedia https://en.wikipedia.

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List of MIPS architecture processors

This is a list of processors that implement the MIPS instruction set architecture, sorted by year, process size, frequency, die area, and so on. These processors are designed by Imagination Technologies, MIPS
Technologies, and others. It displays an overview of the MIPS processors with performance and functionality versus capabilities for the more recent MIPS Aptiv families.

MIPS Computer Systems/MIPS Technologies

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Die
MIPS Process Frequency Transistors Pin Power Voltage D. cache I. cache L2 L3
Processor Year area MMU Features
version (nm) (MHz) (millions) count (W) (V) (KB) (KB) cache cache
(mm2)

64 5 stage pipelines,
R2000 1985 2000 8 to 16.67 0.11 80 64 external none none
external FPU: 2010
MIPS I
145, 32-256 32-256 0-1 MB same as R2000;
R3000 1988 1200 16.67 to 40 0.11 40 4 none
172 external external external FPU: 3010

32-bit register
size, 36-bit
MIPS II R6000 1990 60 to 66 external external none none
physical address,
FPU

128 KB to
R4000 1991 800 100 1.35 213 179 15 5 8 8 4 MB none
external

128 KB to
R4400 1992 600 100 to 250 2.3 186 179 15 5, 3.3 16 16 4 MB none
external

scalar design with

128 KB to
a five-stage
R4200 1993 600 80 1.3 81 179 1.8-2.0 3.3 8 16 4 MB none
classic RISC
external
MIPS III pipeline

R4300i 1995 350 100 / 133 45 120 2.2 3.3 none

512 KB
R4600 1994 640 100 / 133 2.2 77 179 4.6 5 16 16 none
external

512 KB
R4650 1994 640 133 / 180 2.2 77 179 4.6 5 16 16 none
external

R4640 1995 640 179 none

R4700 1996 500 100 to 200 2.2 179 16 16 External none

1 MB
R5000 1996 350 150 to 200 3.7 84 223 10 3.3 32 32 none
external

250, 180, 3.3, 2.5, 256 KB 1 MB

RM7000 1998 250 to 600 18 91 304 10, 6, 3 16 16
130 1.5 internal external

superscalar, up to
4 MB
R8000 1994 700 75 to 90 2.6 299 591 30 3.3 16 16 none 4 instructions per
external
cycle

512 KB –
R10000 1996 350, 250 150 to 250 6.7 350 599 30 3.3 32 32 16 MB none
MIPS IV external

512 KB – single-chip
R12000 1998 350, 250 270 to 360 7.15 229 600 20 4 32 32 16 MB none 4-issue
external superscalar

R12000A 2000 180 400 none

512 KB –
R14000 2001 130 500 7.2 204 527 17 32 32 16 MB none
external

R14000A 2002 130 600 17 32 32 none

MIPS Process Frequency Transistors Die area Pin Power Voltage D. cache I. cache L3
Processor Year MMU L2 cache Features
version (nm) (MHz) (millions) (mm2) count (W) (V) (KB) (KB) cache

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Die
MIPS Process Frequency Transistors Pin Power Voltage D. cache I. cache L2 L3
Processor Year area MMU Features
version (nm) (MHz) (millions) count (W) (V) (KB) (KB) cache cache
(mm2)

512 KB –
R16000 2003 110 700 to 1000 20 64 64 16 MB none
external

R16000A 2004 110 800 to 1000 64 64 none

was planned, but

R18000 2001 130 1.2 1 MB none
not manufactured

was planned, but

H1 "Beast" none
not manufactured
MIPS V
was planned, but
H2 "Captain" none
not manufactured

4K 1999 180 167 2.5 none

4KE 90 420 1.2 none

400 (130 nm)

130, 65, 4–16 MB
24K 2003 750 (65 nm) 0.83 0 to 64 0 to 64 none
40 external
1468 (40 nm)

130, 65,
24KE 2003 none
40

500 (90 nm)

34K 2006 90, 65, 40 none
1454 (40 nm)

74K 2007 65 1110 2.5 0 to 64 0 to 64 none

MIPS32 1004K 2008 65 1100 4.7 8 to 64 8 to 64 none

M14K 2009 130 200 none MicroMIPS

1074K 2010 40 1500 none

1074Kf 2010 40 none Floating point

microAptiv 2012 90, 65 8 to 64 8 to 64 none

up to
interAptiv 2012 4 to 64 4 to 64 8 MB none
internal

up to
proAptiv 2012 32 or 64 32 or 64 8 MB none
internal

5K 1999
MIPS64
20K 2000

MIPS Process Frequency Transistors Die area Pin Power Voltage D. cache I. cache L3
Processor Year MMU L2 cache Features
version (nm) (MHz) (millions) (mm2) count (W) (V) (KB) (KB) cache

Imagination Technologies
MIPS Technologies was acquired 17 December 2012, by Imagination Technologies. Since then, the following processors have been introduced by Imagination Technologies.

Imagination Technologies sold MIPS processor rights to Tallwood MIPS Inc in 2017.[1] MIPS Technologies was acquired by Wave Computing in 2018, where "MIPS operates as an IP licensing business unit". [2][3]

The Warrior P-Class CPU was announced on 14 October 2013.[4]

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The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on MIPS32 release 5 and MIPS64 release 6, and will come in three classes of performance and features:

▪ 'Warrior M-class': entry-level MIPS cores for embedded and microcontroller applications, a progression from the popular microAptiv family
▪ 'Warrior I-class': mid-range, feature-rich MIPS CPUs following on from the highly efficient interAptiv family. The I6400, with its 64-bit core, was launched September 2014. [5]
▪ 'Warrior P-class': high-performance MIPS processors building on the proAptiv family

Die
MIPS Process Frequency Transistors Pin Power Voltage D. cache I. cache L2 L3
level Processor Year area MMU Features
version (nm) (GHz) (billions) count (W) (V) (KB) (KB) cache cache
(mm2)

Up to 8
Warrior-P P5600 2013 ? 1.0 to 2.0 ? ? ? ? ? 32/64 32/64 TLb MB none VZ, MSA
external
MIPS32
Release 5 0.04 to
Warrior-M M5100 2014 65/28 0.1 to 0.497 ? ? none none FMT none none VZ
0.77

Warrior-M M5150 2014 65/28 0.372/0.576 ? 0.89/0.26 ? up to 64 up to 64 TLB none none VZ

0.5 -
Warrior-P P6600 2015 28 Up to 2.0 ? ? ? ? ? 32/64 32/64 TLB 8 MB none SMT, VZ
external

MIPS64 0.5 -
Release 6 Warrior-I I6400 2014 28 1.0 ? 1/core ? ? ? 32/64 32/64 TLB 8 MB none SMT, VZ
external

Warrior-M M6200 2015 65/40/28 up to 0.750 ? 0.19 ? none none FMT none none

Warrior-M M6250 2015 65/40/28 up to 0.750 ? 0.23 ? up to 64 up to 64 TLB none none XPA

MIPS Process Frequency Transistors Die area Pin Power Voltage D. cache I. cache L2 L3
level Processor Year MMU Features
version (nm) (GHz) (billions) (mm2) count (W) (V) (KB) (KB) cache cache

Other designers
A number of companies licensed the MIPS architecture and developed their own processors.

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Die
MIPS Process Frequency Transistors Pin Power Voltage D. cache I. cache L2 L3
Licensee Processor Features Year size MMU
version (nm) (MHz) (millions) count (W) (V) (KB) (KB) cache cache
(mm2)

LX4080,
LX4180,
MIPS I Lexra LX4280,
LX5280,
LX8000

MIPS II НИИСИ РАН KOMDIV-32

Sony Computer
Emotion
Entertainment
MIPS III Engine
+ Toshiba

НИИСИ РАН KOMDIV-64

Alchemy
Au1
Semiconductor

BMIPS3000

BMIPS4000

Broadcom BMIPS5000 1300

MIPS32
BCM53001 65 400 32 32

BCM1255

single
Ingenic issue, 180, 130,
XBurst 1 2005 240 0.15 1.8 16 16 yes none none
Semiconductor 8-stage 64, 40
pipeline

SiByte SB1

4w @
BCM1125H 400-800 32 32 yes 256 KB
400 MHz

Broadcom Dual-core,
DDR2, 4× 13 W @
BCM1255 800-1200 32 32 yes 512 KB
Gigabit 1 GHz
LAN

Octeon:
CN30xx,
CN31xx, 2006
CN36xx,
MIPS64 CN38xx

Cavium Octeon Plus:

2007
CN5xxx

Octeon II:
2009
CN6xxx

Octeon III:
2012
CN7xxx

dual-
Ingenic
XBurst 2 issue/dual- 2013 40 240 0.15 1.8 16 16 yes none none
Semiconductor
threaded

NEC VR4305

MIPS Process Frequency Transistors Die size Pin Power Voltage D. cache I. cache L2 L3
Licensee Processor Features Year MMU
version (nm) (MHz) (millions) (mm2) count (W) (V) (KB) (KB) cache cache

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Die
MIPS Process Frequency Transistors Pin Power Voltage D. cache I. cache L2 L3
Licensee Processor Features Year size MMU
version (nm) (MHz) (millions) count (W) (V) (KB) (KB) cache cache
(mm2)

VR4310

NXP ??
Semiconductors ??

none yet
CAS: ICT
??

MIPS Process Frequency Transistors Die size Pin Power Voltage D. cache I. cache L2 L3
Licensee Processor Features Year MMU
version (nm) (MHz) (millions) (mm2) count (W) (V) (KB) (KB) cache cache

Other
▪ PhysX P1 - A multi-core physics processing unit that contains MIPS cores

References
1. "Completion of sale of MIPS - Imagination" (https://www.im 2. "Wave Computing and MIPS Technologies Reach 4. "Imagination reveals first MIPS 'Warrior P-class' CPU core"
aginationtech.com/news/press-release/completion-of-sale- Agreement to Exit Bankruptcy" (https://www.prnewswire.c (http://www.imgtec.com/News/Release/index.asp?NewsID
of-mips/). 25 October 2017. om/news-releases/wave-computing-and-mips-technologies =804). 2013-10-14. Retrieved 2013-10-28.
-reach-agreement-to-exit-bankruptcy-301198786.html). 5. "MIPS reborn with 64-bit core launch" (http://www.v3.co.uk
3. "About – MIPS" (https://www.mips.com/about/). Retrieved /v3-uk/news/2363163/mips-architecture-reborn-with-64-bit
2019-11-06. -mips-i6400-targeting-mobile-devices-to-servers).

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