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Semiconductor 101

This document provides an overview of integrated circuits (ICs), including their functionality and manufacturing process. It begins with definitions of key semiconductor terms and describes the basic building block of ICs, the MOSFET transistor. It then discusses the overall IC manufacturing flow and the major drivers for change in the semiconductor industry. The document aims to explain what an integrated circuit is and how it is produced.

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jamalur.l
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
196 views79 pages

Semiconductor 101

This document provides an overview of integrated circuits (ICs), including their functionality and manufacturing process. It begins with definitions of key semiconductor terms and describes the basic building block of ICs, the MOSFET transistor. It then discusses the overall IC manufacturing flow and the major drivers for change in the semiconductor industry. The document aims to explain what an integrated circuit is and how it is produced.

Uploaded by

jamalur.l
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 79

Semiconductor 101 / 102:

Functionality and Manufacturing of


Integrated Circuits
FTF-INS-F1117

John Cotner | Freescale Automotive Field Engineering


JUNE.2015

TM

External Use
Semiconductor 101/102 Summary

The goal of this session is for you to understand:


• What Is An Integrated Circuit (IC)?
• Overall IC Manufacturing Flow
• Basic Drivers for Change in the Semiconductor Industry

TM

External Use 1 #FTF2015


Agenda
• Introduction to Integrated Circuits (IC’s)
• IC Manufacturing Process
• Tooling, Equipment, and Investment Needs for IC
Design and Manufacture
• Semiconductor Manufacturing Video

TM

External Use 2 #FTF2015


Introduction to Integrated Circuits
(IC’s)

TM

External Use 3 #FTF2015


Semiconductor Terms and Acronyms

TM

External Use 4 #FTF2015


What is a Semiconductor?

• A conductor carries electricity


like a pipe carries water.

• A semiconductor controls the Conductor

flow of electricity like a faucet


controls water.

• An insulator stops the flow of


electricity like a plug blocks
water.

Insulator

TM

External Use 5 #FTF2015


Semiconductor Basics

• Copper, a conductor, has one


electron per atom available for
conduction.

• A useful semiconductor
requires about 10 orders of
magnitude less

• This means adding as little as


one doping atom in a billion
n Type doped with p Type doped with B
• Impurities have to be below P or As
one in 10 billion

TM

External Use 6 #FTF2015


Basic IC Building Block: MOSFET
• A MOSFET transistor is nothing more than a voltage controlled switch!
• A transistor is just like a light switch on a wall, except that a voltage is used to turn the switch
on and off instead of a lever.
• A good analogy to a transistor is two lakes connected by a canal.

"flood gate"

Water
reservoir
(SOURCE) Water
reservoir
(DRAIN)

• The "flood gate" regulates the flow of water between the two lakes (source and drain).
• A real transistor switches the flow of electric current on and off instead of water.

TM

External Use 7 #FTF2015


N-Channel MOSFET Operation
• Current (water) will not flow from an n-type reservoir to a p-type region
because it would have to flow uphill. .

p-type channel

water
reservoir water
(SOURCE) reservoir
(DRAIN)
n-type

n-type
• Only way we can get water from one p-type reservoir to another is by way of a
n-type channel.
• By using a capacitor and applying a positive voltage to that capacitor, we can
change the apparent conductivity of the channel from p to n and turn the
transistor on.
• In reality, the drain is usually at a lower elevation than the source so the water
will flow downhill to the drain.
TM

External Use 8 #FTF2015


Anatomy of a MOSFET: Cross-Section

• A MOS transistor is nothing more than a voltage-controlled switch.


• A MOS transistor is really just a capacitor with two extra terminals.

Capacitor Doped
(gate) polysilicon
Direction of
electron flow

isolation n+ n- n- n+ isolation
(oxide) source channel drain (oxide)
p-type silicon

Cross-Section View

TM

External Use 9 #FTF2015


Anatomy of a MOSFET: Top View

Capacitor

Isolation
(oxide)

source drain

Top View

TM

External Use 10 #FTF2015


Semiconductor Device Types

• Analog semiconductor devices deal in precise electric properties, most commonly


voltages. Transistors within the device are designed to measure and manipulate
these properties. Analog devices are well suited to processing real-world signals,
as electronic patterns are used to directly represent the original.

• Digital devices do not deal in the values of actual voltages; rather, they simply
detect the presence or absence of a voltage. The presence of a voltage is
represented digitally as a “1,” with the absence represented as a “0.” These 1s and
0s can be processed and manipulated digitally with great flexibility.

• Mixed Signal – These devices include both analog and digital circuitry. Mixed
signal devices are difficult to design and build, but bring the benefits of both analog
and digital processing together.

TM

External Use 11 #FTF2015


Device Types: Semiconductor Industry Association (SIA)
Framework
• Discretes, Optoelectronics, Sensors – Includes all non-integrated circuit
semiconductor devices. A discrete is a single transistor in a package. Sensors are
discrete devices that measure real-world input. Optoelectronics are discrete devices
that produce or measure light.

• Analog – Devices used to process real-world signals using electronic voltage patterns
that represent the original. Includes SLICs (standard linear components) and ASSPs
(application-specific analog ICs).

• Logic – All non-microcomponent digital logic. Includes ASICs (custom logic), ASSPs
(standard specialty logic products), FPGAs (programmable logic), display drivers and
general purpose logic.

• Memory – Memory devices are used to store data either for short periods of time or
permanently. Includes volatile (DRAM, SRAM) and non-volatile (flash, ROM) memory.

• Microcomponents – All digital processors, including microprocessors (MPUs),


microcontrollers (MCUs) and digital signal processors (DSPs).

TM

External Use 12 #FTF2015


Microcomponents in Detail

Microcomponents: Devices designed to perform intensive


compute processing and system control
Three Key Types:
• Microprocessors – digital processors that execute instructions
and perform system control functions. MPUs are optimized for
general purpose data processing
• Microcontrollers – stand-alone devices that perform embedded
compute functions within an overall system. MCUs contain single
of multiple processing elements as well as on-chip, RAM, ROM,
and I/O logic.
• Digital Signal Processors – specialized high speed
programmable processors designed to perform real-time
processing of digital signals

TM

External Use 13 #FTF2015


Example Microcontroller - MPC5748G

TM

External Use 14 #FTF2015


Packaging Options for Mixed-Signal Functions

Semi-Discrete Solution Multi-die SiP Monolithic SiP

Standard MCU Single package MCU and Analog


on the same die

Die-to-die bonding

Application Specific
Analog IC (ASIC)

TM

External Use 15 #FTF2015


Example of Inertial Sensing Elements

Poly Silicon, Folded Beam


Z-Axis Sensing

Z axis
Elements

Poly Silicon, Interdigitated Harmems, Interdigitated


X and XY-Axis Sensing X and XY Sensing

X axis
Elements

TM

External Use 16 #FTF2015


Stacked-Die Packaging for Sensors and Processors

Wire bonds g-cell cap


1.98mm
g-cell device
ASIC
Lead Frame

6 mm

TM

External Use 17 #FTF2015


Accelerometer Device Images

G-Cell Die

ASIC Die

Mold Compound

TM

External Use 18 #FTF2015


Packaged Radar in Redistributed Chip Packaging (RCP)
Attributes
• Single Die
• 1 Metal Layer
• 6x6mm Body Size
• 0.5mm Pitch
• 0.3mm Solder Ball Diameter
• Leadfree

TM

External Use 19 #FTF2015


Major Freescale Packages
Current Qualified HVM Capability (Analog/CMOS/NVM)

FCPBGA
PBGA/TE-
Body Size (mm)

PBGA
QFP

PQFN MAPBGA FC-CSP


*
SOIC
RCP

QFN
WLCSP

Log (I/O Count)


IO Count

TM

External Use 20 #FTF2015


RF Power Packages

Metal-Ceramic
Plastic TO Packages
Air Cavity Package

PQFN Package PLD1.5 Package OMNI Packages

TM

External Use 21 #FTF2015


Body Controller Partitioning Example
MC33909 POWER

High End 32Bits MCU - MPC5645C


System Crossbar Master Debug
Auxiliary eXtreme Switch
JTAG
DC/DC Vreg - Vaux VReg
Penta Extrem Switch
Nexus
Pre Regulator FMPLL PPCTM
PPCTM Class 2+/3+ SPI
Buck e200z4d
e200z0 GPIO 7mW HSD
XOSC/SXOSC Core ATD 15mW HSD
Buck Boost MCU Core Vreg Core 7mW35mW
HSD HSD

Security
PWM*

CSE
15mW HSD

Ethernet

FlexRay
Config. Vcore 128k/16M IRC 4k I-cache (*Opt)

(FEC)
VLE 7mW HSD
32ch MMU
Internal RTC/API 15mW HSD
eDMA 17mW HSD
Power FET
INTC 15mW HSD
CAN Vreg 17mW HSD
CROSSBAR SWITCH SPI/Diag/Wdog
Low Power Modes
Memory Protection Unit (MPU)
6 Sw to Gnd Adv SPI
Wake Up pins Low current load
8xPIT
Debug pin Analog MUX 1xSWT 96k 3MB 128k 128k
4xSTM AIPS_L
DFLASH CFLASH SRAM SRAM 0.7W HSD/LSD
Bridge
Static & dynamic safe pins (ECC) (ECC) (ECC) (ECC)
0.7W HSD/LSD
BAM
Fail Safe State Machine SSCM
0.7W HSD/LSD

0.7W HSD/LSD
1 CAN High Speed
0.7W HSD/LSD

Communications I/O
0 up to 4 LIN / J2602 SPI
GPIO 0.7W HSD/LSD
PWM

System
CTU 32 ch+ 16 ch 0.7W HSD/LSD
eMIOS eMIOS 8 10 1 6
ATD ATD
32 ch. 32 ch. 10bit
DSPI LinFlex I2C FlexCan 0.7W HSD/LSD
12bit
Limp SPI / Diag.

MC33879
High/Low side configurable
SPI / GPIO SPI switch
SPI / GPIO
INT / ATD GPIO PWM
Flexray Tr
FlexRay Tr
FlexRay
Switch
Switch RF transceiver H-bridge
LINTr
LIN
LIN
LIN Tr
Tr
Tr detection
detection Echo+ MERLOT
DRIVERS
MC33662/3 SCI (TX & RX) interface
interface
4x MC33662 GPIO (EN)

CAN TrTr MC33972/5/8 MC33696 MC33926


CAN
CAN
CAN TrTr
MC33901/2 CAN (TX & RX)
GPIO (EN, …) Switch interface Motor
RF interface interface
Communication

TM

External Use 22 #FTF2015


Control Modules – Functional Breakdown

Compute Engine
Analog Signal Conditioning

Low Voltage Protection


Core/NVM
High Voltage

Power Drivers

Peripherals interface to the real world


Mother Nature

TM

External Use 23 #FTF2015


Example Die Photos of Integrated Circuits
Radar Transceiver

VCO PLL

TX2 BU
Digital
F

TX1

RX1 RX2 RX3 RX4


RX

TM

External Use 24 #FTF2015


MPC561 Die Photo

• 32-bit MCU with Power


Architecture® CPU core

• Die size = .55 cm2

• 5 million transistors

• 16 million vias and local


interconnects

• 2 polysilicon layers

• 3 aluminum metal layers

• 0.25 µm technology

TM

External Use 25 #FTF2015


MPC5554 Floor Plan

• Red – CPU
ADC
• Blue – eTPU
• Green – eQADC
• Purple – DSPI
Flash
• Yellow – eMIOS
RAM

• Orange – FlexCAN
• White – EBI
• Dark Green – SIU
• Magenta – JTAG
• Grey – SCI

PLL

TM

External Use 26 #FTF2015


MPC5674F Technology Highlights
• ~350 process steps, 55 mask layers
• ~75 million transistors
• ~400 chips per 200 mm wafer
• Embedded ADC, SRAM, non-volatile memory

6 Layers of Cu Metal 1.15 um2 SRAM Bitcell Array

State-of-the-art Power Architecture®


32-bit MCU engine control
600+ DMIPS – MPC5674F
NVM Bitcell Array NVM Bitcell Logic

TM

External Use 27 #FTF2015


What Is a Micron Between Friends?

• 0.5 micron is 1/200th the


width of a human hair

1997 mainstream process

• 55 nm is 1/2000th the
width of a human hair

2014 mainstream process


0.5 um
Electron microscope photograph
of a common Texas fire-ant eye

TM

External Use 28 #FTF2015


What Is a Nanometer Between Friends?

Source: nano.gov/nanotech-101/what/nano-size & http://www.nanosciencekits.org/

TM

External Use 29 #FTF2015


Semiconductor Terms and Acronyms: Review

TM

External Use 30 #FTF2015


Integrated Circuit Manufacturing
Process

TM

External Use 31 #FTF2015


Semiconductor Manufacturing Overview

Sand Silicon Ingots

Die

Chip Packaging
Wafer

TM

External Use 32 #FTF2015


Semiconductor Overview: Fundamental Processes

Raw silicon substrate


E

Chemical deposits
Diffusion grows or deposits a layer of oxide, nitride, poly or similar material.
Poly/Nitride/TEOS Coat

Oxide Growth
Silicon Wafer

Chemical deposits

Photo spins on photoresist, aligns reticle and exposes wafer


with reticle pattern. Develop removes resist from exposed areas.

Etch removes film layer that was uncovered


during develop. Strips resist.

Implant dopants are implanted for


IC manufacturing uses a electrical characteristics.
Doped Region

recursive deposition and Substrate Metals/Films


masking process to define connects devices
electrically and isolates
patterns of doped areas, circuit pathways.
isolation films and metal
conductors to create solid CMP polishing technique Probe/Test
state devices. to keep surfaces flat so test device
more layers can be added functions

TM

External Use 33 #FTF2015


Semiconductor Front-End Manufacturing Process

Test and back-end

Outgoing
Room Temp Hot Temp Dicing Inspection,
Probe Probe (for Pack & Ship
KGD)

TM

External Use 34 #FTF2015


Anatomy of a MOSFET: Cross-Section

• A MOSFET is the basis for all CMOS digital logic

Capacitor Doped
(gate) polysilicon

Direction of
electron flow

isolation n+ n- n- n+ isolation
(oxide) channel (oxide)
source drain
p-type silicon

Cross-Section View

TM

External Use 35 #FTF2015


Examples of a Completed Ingot

Single crystal silicon ingot length: 110 cm

TM

External Use 36 #FTF2015


Preparing the Wafers

• The ingot is ground into the correct


diameter for the wafers.

• Then, it is sliced into very thin


wafers.

• This is usually done with a diamond


saw.

Slicing : 640m thick

TM

External Use 37 #FTF2015


Mask-Making Process

The Process
• Start with ultra-pure glass plates with
a surface deposition of chromium.
• Computer generated layouts of the IC
drive a laser beam or electron beam to
selectively remove chromium and
create the mask or reticle.
Design Driven
• Increased complexity
• Long write times

TM

External Use 38 #FTF2015


Lithography Process Overview (1 of 2)

Substrate with Thin Film

Resist Coat and Post Apply Bake (PAB)

Expose Resist

Post Exposure Bake (PEB)

Develop Resist

Etch

TM

External Use 39 #FTF2015


Lithography Process Overview (2 of 2)

TM

External Use 40 #FTF2015


Adding Photoresist
Dispenses
Wafers receivers
Hot plate

Unloading
Track 1
Loading

Track 2

Control keyboard

TM

External Use 41 #FTF2015


Exposure

Mercury Lamp

Shutter

Reticles Reticle
Storage

Lens

Wafer Stage

Wafer
Loading /Unloading

TM

External Use 42 #FTF2015


Develop
Wafers receivers
Hot plates
Dispense

Track 1

Un loading
Loading
Track 2

Control panel

TM

External Use 43 #FTF2015


Etching (Chemical and Reactive Ion)
Process gases
Process
Radio frequency chamber
under
power supply vacuum

Ionized
Gas ETCH

Exhaust management Wafers with resist


Vacuum system

45:00 45:00 45:00 45:00 Process control

Acid Acid
QDR
Heating element
QDR QDR

Acid waste Drain Rinse

TM

External Use 44 #FTF2015


Diffusion Furnace
Atmospheric Pressure Furnace
• Diffusion furnaces are classified as
either horizontal or vertical. Exhaust
Heating elements
• Vertical gives better process control
and tends to be cleaner but takes up GAS
more space.

• Changing the process gases allow us


to grow films (oxide, nitride, poly) or
dope the wafers to change the Wafers on quartz boat
electrical characteristics.

• They operate at temperatures


generally between 650°C and 1200°C. Gases Management

• Temperatures in furnaces are


controlled to better than +/- 1°C.

• Furnaces can process 50-200 wafers


per run depending on type of process.

• Process times can vary from 4-20


hours (thicker films take longer to
grow/deposit). Vertical Furnace

TM

External Use 45 #FTF2015


Ion Implantation and Annealing

Gas
box
Too heavy ions

Source

Ion Accelerator Ion Accelerator


Too light ions

Loading

Machine Management

TM

External Use 46 #FTF2015


Typical Photo-Lithography Process

optical
oxidation mask

photoresist photoresist coating


removal (ashing)
stepper exposure

photoresist
acid etch development
process spin, rinse, dry
step

TM

External Use 47 #FTF2015


Copper Metallization

Metal 6

Via 4 Metal 5

Via 3
Metal 4
Via 2
Metal 3
Via 1

Metal 2

Photo by Timothy Nguyen Metal 1

TM

External Use 49 #FTF2015


Chemical Mechanical Planarization (CMP)

• Without CMP, the wafer will


have a lot of topography
(mountains and valleys).
• Excessive topography will:
− Limithow small
photolithography can print
− Compromise etch and film
deposition uniformity

TM

External Use 50 #FTF2015


Typical Processor Cross-Section
POLYIMIDE Cleared Bond POLYIMIDE
Pad Opening
SION exposed
150 PEN to PadClear
Etch MHATFuse
150 PEN
This process requires
4500 SION
more than 190 stages.
Each stage contains
METAL 4 METAL 4
multiple substeps.
Via 3 Via 3
SION
PEN ESL
METAL 3 METAL 3

Via 2 Via 2
PETEOS
PEN ESL
METAL 2 METAL 2

Via 1 Via 1

PEN ESL
METAL 1 METAL 1

TEOS+SION
LI LI BAR LI LI
BPTEOS

ESL

n+ n+ n+ P+ P+

P-Well
N-Well
Epi 2.0 µm

P + Substrate

TM

External Use 51 #FTF2015


Class Probe

• Parametric testing of test structures


• Test structures in scribe lines
between product die

CDs
FNF

AG004
FNF

Reticle
CDs

Product Die Product Die Product Die


field
PID1

PID1

ESD17
TS311 BITD1 C180 FE47 TS311
BE751 C190 BE752
FE05 BITM1 C22 FE48 BE102

PRB01

Product Die Product Die Product Die


IRPR1
CDs

CDs

BE145 TS301 TS311 T100 C100


BE767 TS401 R0111 T110 C110
OPN01

C90_OPCTP BE700 LCAP8 C90SOI_RLM_RO C110A

Product Die Product Die Product Die


IRPR3
PID3

PID3

SIMS

BITP2 T182 TS300 T100A BE123


BITP3 T192 TS400 T110A BE701
Label IDs

BITL4 BITL5 FE49 FE50 FE04


C90_OPCTP

SGPC = scribe grid process control


CDs Scat

Product Die Product Die Product Die


PID4

PID4

PRB01 BE753 BE750


Not to scale (~0.1mm)
CDs
FNF

TS311 G110 RO101 G210 TS311


FNF

TM

External Use 52 #FTF2015


Backgrind

Wafer thickness is reduced from 640m to 300m

2
3 1

Rotated table

Unloading Loading

TM

External Use 53 #FTF2015


Integrated Circuit Back-End
Manufacturing Processes

TM

External Use 54 #FTF2015


Test and Assembly Process

TM

External Use 55 #FTF2015


Assembly Package Process Flow

Wafer
Wafer Backgrind Wafer Saw Die Bonding Die Attach Cure
Clean & Mount

QFP
Lead Plating &
Post Mold Cure Mold Wire Bonding Plasma Clean
Post Plating Bake

BGA

Laser Mark
QFP
BGA

Trim & Form or Lead / Ball Final Visual


Solder Ball Attach Flux Clean
Pkg Singulation Integrity Scan Inspection

TM

External Use 56 #FTF2015


Burn-In

TM

External Use 57 #FTF2015


Final Test Process Flow
Burn-in
24 hrs, 125º C Bake
or Equivalent

Functional
Test – Cold Lead / Ball
Integrity Scan

Functional
Test – Hot

Tape & Reel


(optional)
Functional
Test – Room

QC RHC Dry Pack &


Gate Ship

TM

External Use 58 #FTF2015


Semiconductor Fabrication
Equipment

TM

External Use 59 #FTF2015


Freescale ATMC Factory Configuration

Air Air Air Air Air


Recirc Recirc Recirc Recirc Recirc Fan Deck
ULPA Ceiling Interstitial SEM,
Center Computer Center,
Corridor Work Utility Zone Work
Work
Zone
Utility Zone
Class 100
Work
Zone Zone Class 100 Zone Smock Rooms
Class 1 Class 1 Class 1 Class 1
Process Level
Process Process Process Process
Tool Tool Tool Tool

Raised Floor

Electric
HPM Rooms Exhaust Exhaust
Rooms
Maintenance Shops
Piping Piping
Subfab Parts, Quartz,
Wafer Storage

Ele
c. Ele
Suppor Suppor c.
t Tools t Tools

Crawl Space

TM

External Use 60 #FTF2015


ATMC Cleanroom: Systems, Controls, Airflow
Infrastructure

ATMC Specs
ATMC Site: 951K ft2
Clean Room: 140K ft2

TM

External Use 61 #FTF2015


ATMC Cleanroom Airflow Filtration

• First stage makeup air pre-filters are 30% efficient for 3-10um sized particles.
• Second stage makeup air pre-filters (inside makeup air units) are 95% efficient for
0.3-1µm sized particles.
• Final stage filters (cleanroom ceiling grid) are Ultra Low Penetrating Air (ULPA)
filters that are 99.9995% efficient for 0.1um sized particles.
• 100% cleanroom ceiling ULPA filter coverage in work zone (40% coverage in utility
zone)
• Average laminar airflow velocity is 90-110 ft/min
• Cleanroom Airborne Particle Monitoring

− Portable laser sensors are used to measure airborne particles at 561 locations
throughout the cleanroom
− Cleanroom Classification criteria specifies a maximum of 35 particles/ft3 (0.1um)
to achieve Class 1 designation – ATMC averages < 1 particle/ft3

TM

External Use 62 #FTF2015


Freescale CHD-Fab Macro Layout
North & South
Cleans/ISD
CVD
2.5k sf
(TEOS, East Module (Bldg “M”)
PAS)
Implant 5.6k sf

Etch Metals
4.2k sf Implant
PVD
23k sf
“ 11 k sf
C” Bldg Epi
Diffusion/

6.5ksf
Photo
Cleans Photo
10k sf i -line Gown MRAM
Analytical
Probe 2.1ksf
Polyimide 7k sf
8.3k sf 5.8k sf 9k sf
Lot
Start
Ship Implant YE Probe
2.5k sf 27k sf
Diffusion/
N
Cleans Photo CMP
6.6k sf 22k sf
DUV
Implant 6.1k sf
Cleans
“A” Building to the East of “M” Building
CVD
4k sf ETCH has additional 8k sqft of Probe
8.2k sf
ETCH CLNS

Metals
(W,RTP)

TM

External Use 63 #FTF2015


Oak Hill Texas Fab Facts
• 85,000+ square feet of sub-class 1 clean room space supporting wafer
capacity of 6,000 WPW

• Approximately 750 people working at OHT-Fab

• Factory operates 24 hours per day, 364 days per year

• Factory moves ~6,400,000 CFM, enough to fill 120 hot air balloons every
minute

• 9,300 tons of refrigeration capacity, sufficient to cool 2,800 homes

• Factory uses 44,000,000 gallons of water/month, equivalent to 4,400 homes

• Factory uses ~215,000,000 KWH per year, equivalent to 6,000 homes

• Factory has more than 17 miles of stainless steel piping and more than 50
miles of electrical wiring

TM

External Use 64 #FTF2015


Typical Equipment Costs

200MM Equipment List for .18 Micron Facility


Equipment Number Price ($M) Total ($M)
Chemical Vapor Deposition 24 3 60
Physical Vapor Deposition 23 4 81
Steppers 54 8 432
Photoresist Processing 54 2 108
Etch 55 3 187
Cleaning- Strip 30 1 18
CMP 20 1 24
Diffusion - RTP 32 1 32
Ion Implant 13 3 43
Process Control - - 60
Automation/Handling - - 15
Miscellaneous - - 67
Total 1,126

TM

External Use 65 #FTF2015


Business Aspects of
Semiconductor Fabrication

TM

External Use 66 #FTF2015


Staggering IC Design and Tooling Costs

Mask Set Cost by Technology


$2,500

$2,000

$1,500

$1,000

$500

$0
$K 0.8um 0.6um 0.35um 0.25um 180nm 130nm 90nm

TM

External Use 67 #FTF2015


Wafer Size

TM

External Use 68 #FTF2015


Research and Development

• R&D provides two major benefits:


− Increases
productivity
− Enhanced process capabilities (required to remain competitive)

R&D Spending as a % of Sales


R&D by Industry

TM

External Use 69 #FTF2015


Wafer Costs vs. Masking Steps

TM

External Use 70 #FTF2015


Drivers for Wafer Manufacturing
Change

TM

External Use 71 #FTF2015


Effect of Process Shrink: NVM Bitcells
MC68HC11 MC68F333
2T-S Flash
EEPROM 1.5T Flash
MPC555

MPC565

MPC5554

CDR1
CDR3
1T Flas h
ETOX Flash High Density
130nm
Scale Drawing High Density
ETOX Flash
High Density

TM

External Use 72 #FTF2015


Freescale 1T Flash Bit Cells at 0.35µm and Below

CDR1 0.35µm CDR3 0.25µm HiP7 130nm CMOS90 CMOS55 CMOS40


FN/FN 1T HCI/FN 1T HCI/FN 1T HCI/FN 1T HCI/FN 1T HCI/FN 1T
2.7µm2 0.995µm2 0.359µm2 0.18µm2 <0.15µm2 < 0.1µm2

All bitcells are drawn on the same scale.

TM

External Use 73 #FTF2015


Process Change for Microcontrollers

MPC555 MPC565 MPC5554


Black Oak Spanish Oak Copperhead
CDR1 0.35u CDR3 0.25u HIP7 0.13u
448K Flash 1MB Flash 2MB Flash
7 million transistors 14 million transistors 34 million transistors

TM

External Use 74 #FTF2015


Process Change for Analog ICs

8 Output Switch 16 Output Switch


0.375 ohm 0.375 ohm
SMARTMOS 2.5 SMARTMOS 5AP

TM

External Use 75 #FTF2015


Total Cost of Ownership

• Frequency
− Test time
• Frequency − EMC components
• Package − Capital equipment

• Die Test • Package


• Tape & Reel − Machinery
− Board size
− Capital equipment
− Tier 1 volume

Silicon $ + Tier1 $ = Micro $


TM

External Use 76 #FTF2015


Semiconductor 101/102 Session Closing

By now, you should understand:


• What Is An Integrated Circuit (IC)?
• Overall IC Manufacturing Flow
• Basic Drivers for Change in the Semiconductor Industry
• Answers to questions about cycle time, semiconductor fab
consolidation, failure analysis results, etc.

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External Use 77 #FTF2015


Questions?

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External Use 78 #FTF2015


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