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Introduction To Make: Example

Make is used to determine automatically which pieces of a large program need to be recompiled. Makefiles describe the relationships among files in the program, and state the commands for updating each file. By using #ifndef / #define, duplication of definitions is avoided during compilation.

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André Perdigão
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62 views6 pages

Introduction To Make: Example

Make is used to determine automatically which pieces of a large program need to be recompiled. Makefiles describe the relationships among files in the program, and state the commands for updating each file. By using #ifndef / #define, duplication of definitions is avoided during compilation.

Uploaded by

André Perdigão
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Operating Systems

Introduction to Make

Programs are made from separate source files, which correspond to different software modules of the overall program. Each of these files is then compiled into object code, by the compiler, and then linked in one executable, by the linker.

Source code (.c)

Pre-processor and Compiler (cc -o)

Object code (.o)

Linker (ld)

Executable

Example:

input.c

input.h

global.c

global.h

m ain.c defined in includes

$gcc input.c c o input.o $gcc global.c c o global.o $gcc main.c c o main.o $gcc input.c global.c main.c -o prog

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input.c #include "global.h" #include "input.h" void menu() { ... error = NO_SCREEN; } global.c #include "global.h" int error = NO_ERROR;

#ifndef _INPUT_H #define _INPUT_H extern void menu(); #endif global.h #ifndef _GLOBAL_H #define _GLOBAL_H #define NO_ERROR #define NO_SCREEN extern int error; #endif 0 1

input.h

main.c #include "global.h" #include "input.h" void main() { menu(); }

Each module is defined in a .c file. Each function that is to be accessed externally has its interface in the corresponding .h file. Global variables are declared in .c files. Their existence is declared in .h files by using extern. By using #ifndef / #define , duplication of definitions is avoided during compilation.

Make
The purpose of the make utility is to determine automatically which pieces of a large program need to be recompiled, and issue the commands to recompile them. Special files (makefiles) describe the relationships among files in the program, and state the commands for updating each file. Only needed files (the ones that were modified and their dependencies) are compiled each time. Syntax: make [-f makefile] [target ...] If a makefile is not specified, make expects a file called Makefile or makefile to be used. If a target is not specified the first in the file is chosen.

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Makefile prog:

To build this

main.o global.o input.o gcc main.o global.o input.o -o prog input.c input.h global.h gcc input.c -c input.o

I need all this and

input.o:

global.o: global.c global.h gcc global.c -c global.o main.o: main.c input.h global.h gcc main.c -c main.o

after, this command is executed

Figure 1 Direct Makefile Put a TAB between targets (e.g.: prog:) and the files on which they depend (e.g.: main.o global.o input.o). Put a TAB before the commands to execute. Leave a blank line between targets.

Makefile CC = gcc OBJS = main.o global.o input.o PROG = prog # GENERIC all: clean: ${PROG} rm ${OBJS} *~ ${PROG}

A macro

Reference to the macro

############################# input.o: input.c input.h global.h ${CC} input.c -c -o input.o

global.o: global.c global.h ${CC} global.c -c -o global.o main.o: prog: main.c input.h global.h ${CC} main.c -c -o main.o ${OBJS} ${CC} ${OBJS} -o prog
Figure 2 Introduction to macros

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Special macros (see manual): o $@ Refers to the current target name o $< Represents the name of the component that is being used to make the target

Makefile CC = gcc OBJS = main.o global.o input.o PROG = prog # GENERIC all: clean: ${PROG} rm ${OBJS} *~ ${PROG}

############################# input.o: input.c input.h global.h ${CC} input.c -c -o input.o

global.o: global.c global.h ${CC} global.c -c -o global.o main.o: prog: main.c input.h global.h ${CC} main.c -c -o main.o ${OBJS} ${CC} ${OBJS} -o prog
Figure 3 Special macros

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Makefile CC = gcc OBJS = main.o global.o input.o PROG = prog # GENERIC all: clean: ${PROG}: .c.o: ${PROG} rm ${OBJS} *~ ${PROG} ${OBJS} ${CC} ${OBJS} -o $@ ${CC} $< -c -o $@
Turns a .c into an .o

############################# input.o: input.c input.h global.h

global.o: global.c global.h main.o: main.c input.h global.h


Figure 4 Rules

Dependencies list

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Make Summary (Remember!)


input.c input.h

global.c

global.h

m ain.c defined in includes

Makefile CC = gcc OBJS = main.o global.o input.o PROG = prog # GENERIC all: clean: ${PROG}: .c.o: ${PROG} rm ${OBJS} *~ ${PROG} ${OBJS} ${CC} ${OBJS} -o $@ ${CC} $< -c -o $@

############################# input.o: input.c input.h global.h

global.o: global.c global.h main.o: main.c input.h global.h

You only have to change the shadow parts to compile different projects, or to update your files during the same project! The project becomes up-to-date on every call to Make.
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