MODULE-2 - Timer, Mem, DOS, BioS - Part 6
MODULE-2 - Timer, Mem, DOS, BioS - Part 6
MICROPROCESSOR ARCHITECTURE
& INTERFACING : INTEL x86
• Timer is a specialized type of device that is used to measure timing
intervals.
• Timers can be categorized into two main types:
– A timer which counts upwards from zero for measuring elapsed
time is often called a stopwatch
– a device which counts down from a specified time interval is
more usually called a timer.
• Timers may be designed in software or in hardware.
• When the microprocessor needs to generate a time delay, the
processor can elapse time simply using a delay routine.
• When a specialized IC is used for the generation of delays and
waveforms of different frequencies, microprocessor becomes free
from these tasks and this minimizes the software overhead of the
processor.
• Computer systems usually have at least one hardware timer.
• These are typically digital counters that either increment or
decrement at a fixed frequency, which is often configurable, and
which interrupt the processor on reaching zero.
• 8253 is one such hardware timer.
What is 8253 Timer?
• Intel 8253 programmable Timer/ counter is a specially designed chip for
Intel microcomputer applications which require timing and counting
operations.
• Designed for being compatible with INTEL microprocessors like
8085,8086, 80X86..
• 8254 is an advanced version of 8253.
• 8253/8254 are programmable using three 16-bit counters.
• Each counter has 2 input pins, Clock & Gate, and 1 pin for “OUT” output.
• To operate a counter, a 16-bit count is loaded in its register.
• On command, it begins to decrement the count until it reaches 0, then it
generates a pulse that can be used to interrupt the CPU.
• It has three independent 16-bit down counters.
• It can handle inputs clocks upto 10 MHz.
• These three counters can be programmed for either hexadecimal or
BCD count.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which
allows the user to check the count value, the programmed mode,
the current mode, and the current status of the counter.
8253
• The timers are basically 16 - bit down counters that counts at HIGH
to LOW transition of the CLK input.
• Each timer may be programmed to operate in one of the six modes,
independent of the mode of operation of the other two timers.
• The timers are software programmable.
• Each counter can be programmed separately to divide the input
frequency by a number from 1 to 65536 (216)
Functional Block diagram of 8253
Pin Diagram and Address Decoding
• Data Bus buffer is a tri-state bidirectional buffer that communicates
with CPU whenever 𝐶𝑆 (Chip Select) is low.
• Data is transmitted or received by executing the OUT PORT and IN
PORT instructions.
• The functions of Data bus buffer are
1. Programming the counters through the control words
2. Writing count to the counters
3. Reading the count value from timers.
Control Register
• The control word register is used to program the timers in different
modes and control their operations.
• It is selected when A0 and A1 pins are 1,1. If 𝐶𝑆 𝑎𝑛𝑑 𝑊𝑅 are low, it
accepts information from the data bus buffer and stores it in control
word register.
• The word stored in CR controls the operation mode of each counter,
selection of hexadecimal or BCD counting and loading of each
count register.
• This register can be written into only no read operation of this
content is available
Counters
• Each of the timers has three pins associated with it. Clock (CLK)
input, gate (GATE) control input and output (OUT).
• CLK - This clock input causes the timer to decrement. Counters
operate at HIGH to LOW transition (the negative edge) of this clock
input.
• GATE - The gate input pin is used to initiate or enable counting.
The exact effect of the gate signal depends on which of the six
modes of operation is chosen.
• OUTPUT- The output pin provides an output from the timer. Its
actual use depends on the mode of operation of the timer. The
counter can be read “on the fly” without inhibiting gate pulse or
clock input.
Operations for Various Control Inputs
Control Word Format
Modes of 8253
1. Mode 0 – Interrupt on Terminal Count
2. Mode 1 – Programmable Mono shot
3. Mode 2 – Rate Generator
4. Mode 3 – Square wave Generator
5. Mode 4 – S/w triggered Strobe
6. Mode 5 – H/w triggered Strobe
• Output is initially low after the mode is set.
• Output remains low even after the count value is loaded in the
counter.
• Counter starts decrementing after the falling edge of the
clock, if the GATE input is high.
• Output will remain low until the Counter reaches zero.
• OUT then goes high and remains high until a new count or a new
Mode 0 Control Word is written into the Counter.
• Whenever there is a rising edge at the gate, the counter starts down
counting. The output of the counter goes low and remains low during
down counting. The output is low for the no. of clock pulses whose value
is loaded in counter.
• OUT will then go high and remain high until the next count is loaded or a
trigger is applied.
• If a new count value is lowed while the output is low, it will not affect the
period of one shot pulse until the succeeding trigger.
• The one shot is retriggerable, hence the output will remain low for the full
count value after any rising edge of the gate input
• This Mode functions like a divide-by-N counter.
• OUT will initially be high. When the initial count has decremented to 1, OUT goes
low for one CLK pulse.
• OUT then goes high again, the Counter reloads the initial count and the process
is repeated.
• Mode 2 is periodic; the same sequence is repeated indefinitely. For an initial
count of N, the sequence repeats every N CLK cycles.
• Mode 3 is similar to Mode 2 except for the duty cycle of OUT signal.
• OUT will initially be high. When half the initial count has expired, OUT goes low
for the remainder of the count.
• Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of
N results in a square wave with a period of N CLK cycles.
• If the loaded count value N is odd, for (N+1)/2 pulses, OUT remains high and for
(N-1)/2 pulses, it is low.
• OUT will be initially high. When the initial count expires, OUT will go low
for one CLK pulse and then go high again.
• Similar to Mode 2, except that the counter is not reloaded automatically,
count has to be reloaded.
• OUT will initially be high.
• Counting is triggered by a rising edge of GATE.
• When the initial count has expired, OUT will go low for one CLK pulse and
then go high again.
• After writing the Control Word and initial count, the counter will not be
loaded until the CLK pulse after a trigger.
• Memory is device used to store the information or data
• Memory organization
– Each memory chip contains 2N memory locations, where N is
the no of address pin on the chip
• RAM chips have two control input signals that specify the type
of memory operation: the Read () and the Write ()
signals.
Partial Decoding
• All the address lines are not used to generate chip select,
basically used in small systems
• Individual high order address lines are used to decode the chip
select for the memory chips using less hardware
• Disadvantages: Each memory location has more than one
address called roll-over addresses (fold back or shading)
• Used to perform some very useful functions, such as displaying data
to monitor, reading data from keyboard.
EX:
MOV AH, 2
MOV DL, ‘A’
INT 21H
• Option 9: output a string of data terminated by $ to the
monitor.
• Register used:
• AH=9
• DX = offset address of data to be displayed
Ex:
• MOV AH,09 ;option 9 to display string of data
• MOV DX, OFFSET mess1
• INT 21H ; invoke the interrupt
• Option 4CH: Terminate a process, by returning control to a
parent process or to DOS.
• Register used:
• AH=4CH
• AL= binary return code
Ex:
• MOV AH,4CH ;
• INT 21H ;
• To call a BIOS routine, one use one of the80x86’s int software
interrupt instructions
• The int instruction uses the following syntax: int value
• Value is some number in the range 0..255.
• Execution will cause the 80x86 to transfer control to one of 256
different interrupt handlers
• The interrupt vector table, starting at physical memory location 0:0,
holds the addresses of these interrupt handlers
• Each address is a full segmented address, requiring four bytes
• int 0 transfers control to the routine whose address is at location 0:0
• int 1 transfers control to the routine whose address is at 0:4
• int 2 via 0:8
• int 3via 0:C, and
• int 4 via 0:10
• Input Parameter:
• AH = 00H
• AL = Mode Number