Phoenix Edu Solutions

Test-1
Multiple Choice Questions
Date: 09/06/2017 Marks: 60
Duration: 60mins

01) What will be the Boolean expression for an inverter logic gate, where input is A and
output is G

G=A

A= G

G=?

None of the above

02) The time required for a gate to change its output is called as

Decay time

start time

run time

propagation time

03) 1kb is equal to

1024 bytes

1000 bytes

100 bytes
 10,000 bytes

04) What will be Excess 3 code for decimal ( 584 )?

(0111 0100 1000).

(1000 1011 0111).

(1011 0111 1000).

(1000 0111 1110).

05) Which of these sets of logic gates are designated as universal gates?

NOR, NAND.

XOR, NOR, NAND.

OR, NOT, AND.

NOR, NAND, XNOR.

06) A half adder is a ________ circuit.

Combinational

Sequential

Both A and B

None

07) Which of the following is not a transmission medium?

Telephone lines.
 Coaxial cables.

Modem.

Microwave systems.

08) A single flip-flop can be cleared (reset) to

Both A and B

None

09) A multiplexer is a combinational logic circuit used to perform the operation

ANDAND

ANDOR

NOROR

XORNAND

10) which of the following is correct

x + x' = 1

x . x' =0

Both A and B
None
11) If clock time period is 1ms, what is its frequency
o 1 MHz
o 1 kHz
o 1 MHz
o None of the above

12) Which of these circuits have higher gate complexity 1. Carry look ahead adder 2. Ripple
carry adder

both have same

none

13) The resolution of a 12 bit analog to digital converter in percent in

0.01220
0.02441.

0.04882.

0.09760.

14) A combinational circuit can be designed using only

AND gates

OR gates
OR and XNOR gates

NOR gates
15) The number of comparators in parallel conversion type B-bit analog to digital convertor
is
8.

16.

255.

256.

16) Integrating circuit counter chips are used in numerous applications including:
o Timing operations, counting operations, sequencing and frequency multiplication
o Timing operations, counting operations, sequencing and frequency division
o Timing operations, decoding operations, sequencing and frequency multiplication
o Data generation, counting operations, sequencing and frequency multiplication

17) Synchronous counters eliminate the delay problems encountered with asynchronous
counters because
o Input clock pulse are applied only to the first and last stages
o Input clock pulse are applied only to the last stages
o Input clock pulse are not used to activate any of the counter stages
o Input clock pulse are applied simultaneously to each stages

18) What is the difference between the combinational and sequential logic?
o Combinational circuits are not triggered by timing pulses, sequential circuits are
triggered by timing pulses
o Combinational and sequential circuits are both triggered by timing pulses
o Neither circuit is triggered by timing pulses
o None of the above

19) A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency. If the
input clock frequency is 60Mhz
 o 500kHz
o 1500kHz
o 6MHz
o 5MHz

20) Which segments of a seven segment display would be required to be active to display the
decimal digit 2?
o a,b,d,e and g
o a,b,c,d and g
o a,c,d,f and g
o a,b,c,d,e and f

21) Which of the following is an invalid state output state for an 8421 BCD counter
o 1110
o 0000
o 0010
o 0001

22) How many different states does a 3 bit asynchronous counter have
o 2
o 4
o 8
o 16

23) A 5bit asynchronous binary counter is made up of five flip flops, each with a 12ns
propagation delay. The total propagation delay is
o 12ms
o 24ms
o 48ns
o 60ns
24) The final output of a modulus 8 counter occurs one time for every
o 8 clock pulses
o 16 clock pulses
o 24 clock pulses
o 32 clock pulses

25) Which of the following groups of logic devices would be the minimum required for a
MOD-64 synchronous counter
o Five flip flops, three AND gates
o Seven flip flops, five AND gates
o Four flip flops, ten AND gates
o Six flip flops, four AND gates

26) A 22MHz clock signal is put into a MOD-16 counter. What is the frequency of the
Qoutput of each stage of the counter
o Q1=22MHz, Q2=11MHz, Q3=5.5MHZ, Q4=2.75MHz
o Q1=11MHz, Q2=5.5MHz, Q3=2.75MHZ, Q4=1.375MHz
o Q1=11MHz, Q2=11MHz, Q3=11MHZ, Q4=11MHz
o Q1=22MHz, Q2=22MHz, Q3=22MHZ, Q4=22MHz

27) A decade counter will count through decimal

o 10
o 9
o 15
o 0

28) It is a characteristic of ring counter that the ______equal to the number of flip flops in the
register
o Number of invalid states is
o Number of CASE statements is
o Modulus is
o Other states are
29) Modulus refers to
o A method used to fabricate decade counter units
o The modulus of elasticity or the ability of a circuit to be stretched from one mode to
another
o An input on a counter that is used to set the counter state such as UP/DOWN
o The maximum number of states in a counter sequence

30) The technique used by one-shots to respond to an edge rather than a level is called
o Level management
o Edge triggering
o Trigger input
o Edge tapping

31) In a 6bit Johnson counter sequence there are a total of how many states or bit patterns
o 2
o 12
o 6
o 24

32) With a 200KHz clock frequency, 8bits can be serially entered into a shift registers in
o 4microsec
o 40microsec
o 400microsec
o 40milisec

33) An 8 bit serial in /serial out shift register is used with a clock frequency of 2MHz to
achieve a time delay of
o 16microsec
o 8microsec
o 4microsec
 o 2microsec

34) A 4 bit shift registers that receives 4bits of parallel data will shift to the _____by
_____position(s) for each clock pulse
o Right, one
o Right, two
o Left, one
o Left, three

35) The primary purpose of three state buffer is usually

o To provide isolation between the input device and data bus
o To provide the sink or source current required by any device connected to its output
without loading down the output device
o Temporary data storage
o To control data flow

36) What is the difference between ring shift counter and a Johnson counter
o There is no difference
o A ring is faster
o The feedback is reversed
o The Johnson is faster

37) A bidirectional 4bit shift register is storing the nibble 1110. Its right or loft input is low
the nibble 0111 is weighting to be enter on the serial data input line. After 2 clock pulses the
shift register is storing
o 1110
o 0111
o 1000
o 1001

38) In a parallel in parallel out shift register, D0=1, D1=1, D2=1, D3=0 after three clock
pulses, the data outputs are
 o 1110
o 0001
o 1100
o 1000

39) By adding recirculating lines to a 4bit parallel in serial out shift register, it becomes a
____, _____, and ____out registers
o Parallel in, serial, parallel
o serial in, parallel, serial
o serial parallel in, serial, parallel
o bidirectional in, parallel, serial

40) What type of register would of a complete binary number shifted in 1 bit at a time and
have all the stored bit shifted out 1 at a time?
o Parallel in parallel out
o Parallel in serial out
o Serial in parallel out
o Serial in serial out

41) To serially shift a nibble of data into a shift register there must be
o 1 clock pulse
o 4 clock pulses
o 8 clock pulses
o 1 clock pulse for each one in the data

42) Computers operate on data internally in a ____format

o Tristate
o Universal
o Parallel
o serial

43) Shifting a binary number to the left by one position is equivalent to

 o Multiplying by 2
o Multiplying by 4
o Dividing by 2
o Dividing by 4

44) One example of the use of an SR flipflop is as a(n)______

o Racer
o Astable oscillator
o Binary storage register
o Transition pulse generator

45) Which of the following gates is known as anticoincidence detector?

o OR gate
o XOR gate
o AND gate
o XNOR gate

46) An OR gate can be imagined as

o Switches connected in series
o Switches connected in parallel
o Transistors connected in series
o Transistors connected in parallel

47) A bubbled NAND gate is equivalent to a

o OR gate
o NAND gate
o NOR gate
o XOR gate

48) The output of a gate is HIGH if and only if all its inputs are LOW. It is true for
o NOR
o XOR
 o NAND
o XNOR

49) Which of the following codes is known as the 8421 code?

o Gray code
o XS3 code
o ASCII code
o BCD code

50) The XS3 code is a

o Cyclic code
o Weighted code
o Self-complementing code
o Error correcting code

51) Each term in the standard SOP form is called a

o Minterm
o Maxterm
o Don’t care
o Literal

52) Switching circuits are

o Analog circuits
o Digital circuits
o Hybrid circuits
o None of these

53) The devices commonly used for making digital circuits are
o Mechanical switches
o Relays
o Contact switches
o Semiconductor devices
54) The voltage levels for positive logic system
o Must necessarily be positive
o Must necessarily be negative
o May be positive or negative
o Must necessarily be 0 V and 5 V

55) The codes in which each successive code word differs from the preceding one in only one
bit position are called
o BCD codes
o Sequential codes
o Self-complementing codes
o Cyclic codes

56) A flip flop is a _______ circuit.

o Combinational
o Sequential
o Both A and B
o None

57) If clock time period is 1ms, what is its frequency

o 1 mHz
o 1 kHz
o 1 MHz
o None of the above

58) The switch which clears a flipflop is known as

o Reset
o Clear
o Both A and B
o None
59) The momentary change in the output/state of the flipflops is known as
o Tristate
o Unstable state
o Inverter
o Trigger

60) Fastest memory element is

o RAM
o ROM
o Cache
o Hard Drive